A data stream has frames of fixed, or variable but determined, length and includes a fixed length header at a predetermined position in the frame, which header has a linear systematic code structure including information digits and check digits. The check digits are employed for frame synchronization detection, as well as error detection and correction, using, for example, a modified CRC (cyclic redundancy check) decoder.
RELATED APPLICATIONS
This application is a continuation-in-part of U.S. patent application Ser. No. 116,949, filed Sep. 7, 1993, abandoned, which is a continuation of U.S. patent application Ser. No. 029,986, filed Mar. 12, 1993, abandoned, which is a continuation of U.S. patent application Ser. No. 517,254, filed May 1, 1990, abandoned.
A CRC coding circuit performs an operation of division of a receive polynomial Yh(x) indicating received data corresponding to input effective bits by the CCITT CRC-16 generating polynomial G(x) to form the residual polynomial Sh(x). The residual polynomial (the bit outputs of delay elements S0 to S15) is input to a CRC inversion operation circuit on a parallel-by-bit basis. The CRC inversion operation circuit, which is identical in arrangement to but opposite in data shift direction to the CRC coding circuit, multiplies the residual polynomial Sh(x) by x.sup.-1, then divides the result by the generating polynomial G(x), thereby detecting an error in the received data.
A method and apparatus are provided for achieving synchronization and detecting errors in a data stream such as an MPEG-2 transport packet stream. In an MPEG embodiment, the MPEG sync word is removed and replaced with a parity code that is used at the decoder for both synchronization and error detection. A syndrome calculator in the decoder can be implemented using a unique one bit in, one bit out FIR filter. Codewords used to generate the parity code can be provided by a linear block code that is a dual of a shortened cyclic code.
The probability of frame destruction is lowered while suppressing the redundancy of the transmission data. On the transmitting side, a predetermined unique word is contained in a frame n for storing the n-th data, and header information n, frame length information and header information n-1 of the frame n-1 one frame before the frame n are subjected to error-correcting coding, contained in the frame n, and transmitted. On the receiving side, the header of the frame n is received. When the frame length information is transmitted with error, the timing is specified by detecting the unique word and header information in the next frame n+1. When the header of the frame n is not successfully decoded, the information data of the frame n is decoded by using the header information n inserted into a predetermined position of the frame n+1.
A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length format packet or burst and a fixed length format packet or burst. The error detection unit is configured to detect an error detection code error when a misalignment occurs within the data stream by recursively calculating parity terms.
In a digital audio broadcasting (DAB) system having a radio-frequency (RF) transmitter and a corresponding RF receiver, a system and method for providing improved frame synchronization is provided. In accordance with the preferred embodiment, the RF transmitter formats a DAB signal into a sequence of frames, each frame having a header with a predefined grouping of psuedo-random number sequences comprising 100 symbols. Of these 100 symbols, 86 symbols of the header preferable are used for frame synchronization and characterization of a communications channel, while the remaining 14 symbols are used for interleaver and data synchronization in an interleaved fashion. The formatted DAB signal, including the frame sequences, is transmitted to the receiver preferably using quadrature phase-shift keying modulation. At the receiver, a correlator, utilizing a synchronization detection algorithm, is generally designed to match a predetermined symbol pattern within the received signal. Once the frame synchronization is established, the channel is characterized and the data symbols are recovered.
