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Claims  |
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We claim:
1. In a network of interconnected nodes;
each node including a processor (10, 12, 14, 16, 18);
each processor including means for internode communication,
said internode communication means connecting said nodes to form an array
of said processors having a hypercube topology;
each of said processors in said network being assigned a unique processor
identification (ID), said ID being comprised of bit 1, bit 2 . . . bit n,
bit n+1, bit n+2, . . . ;
the processor IDs of two processors connected to each other through port
number n, varying only in said bit n;
a first node of said nodes having an output port n;
an apparatus in a second node of said nodes for establishing a
communication path through said second node comprising:
a plurality of input ports, one of said input ports being input port n;
a plurality of output ports;
receiving means (200) at said input port n for receiving a first address
packet related to a first message from said output port n of said first
node;
said first address packet including a forward bit set to one of either a
first state or a second state, said first address packet being immediately
followed by a second address packet;
a data bus (210);
said data bus connecting said input and output ports of said second node
together such that messages received on any one input pod can be routed to
any other output port of said second node;
registering means (202) for registering a processor ID unique to said
second node;
comparing means (204) connected to said data bus, to said receiving means
(200) and to said registering means (202) for comparing a first node
address in said first address packet with each corresponding bit position,
successively, beginning with said bit n+1 of said processor ID of said
second node stored in said registering means to determine a first one bit
position of said first node address in said first address packet that is
not the same as a corresponding bit position of said processor ID of said
second node;
said comparing means (204) including means for activating for transmission
of said first address packet placed on said data bus (210) by said input
port n, the one of said plurality of output ports whose port number
corresponds to said first one bit position, where n is the number of said
input port n;
forward bit detection means for detecting that said forward bit is set to
said first state;
means connected to said forward bit detection means for discarding said
first node address in said first address packet;
said compare logic (204) including means for comparing a second node
address in said second address packet following said first address packet
with each corresponding bit position, successively beginning with a bit
n+1, of the processor ID of said second node to determine a second bit
position of said second node address in said second address packet that is
not the same as a corresponding bit position of said processor ID of said
second node; and,
means for sending said second address packet out of the port number of said
second node corresponding to said second one bit position where n is the
number of a port on which said first address packet is received.
2. The combination in accordance with claim 1 wherein:
said second node includes a local memory (20) having a memory data bus
(156) for receiving data to be stored in said local memory;
said output ports are connected to said memory data bus; and, said
comparing means (204) includes first detection means for detecting that
said node address in said first address packet and said processor ID of
said second node are the same; and,
transferring means connected to said detection means for transferring said
first message to said local memory (20) of said second node.
3. The combination in accordance with claim 1 wherein:
said receiving means (200) further includes receiving means for receiving a
second address packet related to a second message from an output port of a
second of said interconnected nodes;
said compare logic (204) includes second detection means for detecting that
said second address packet specifies the same port as said first address
packet, and,
blocking means connected to said second detection means for blocking, at
said second node, said second address packet;
said receiving means (200) includes means for generating an end of
transmission (EOT) signal upon receipt of an end of transmission (EOT)
message; and,
said compare logic (204) includes means responsive to said end of
transmission (EOT) signal for deactivating said blocking means.
4. In a network of interconnected nodes;
each node including a processor (10, 12, 14, 16, 18);
each of said processors in said network being assigned a unique processor
identification (ID), said ID being comprised of bit 1, bit 2 . . . bit n,
bit n+1, bit n+2 . . . ;
the processor IDs of two processors connected to each other through port
number n, varying only in said bit n;
each processor including means for internode communication,
said internode communication means connecting said nodes to form an array
of said processors having a hypercube topology;
a method of establishing a communication path through a node of said
network comprising the steps of:
A. receiving a first address packet related to a first message from an
output port of a first of said nodes at an input port n of a second of
said nodes, said first address packet including a forward bit set to one
of either a first state or a second state, said first address packet being
immediately followed by a second address packet;
B. comparing at said second node a node address in said first address
packet with each corresponding bit position, successively, beginning with
said bit n+1 of a processor ID of said second node to determine a first
bit position of said node address in said first address packet that is not
the same as a corresponding bit position of said processor ID of said
second node;
C. sending said first address packet out of an output port of said second
node, said output port of said second node having a port number
corresponding to said first bit position, starting at bit n+1, where n is
the number of an input port said second node on which said first address
packet is received;
D. detecting that said forward bit is set to said first state;
E. discarding said first address, in said first address packet in response
to said detecting that said forward bit is set to said first state;
F. comparing a node address in said second address packet with each
corresponding bit position, successively beginning with said bit n+1, of
the processor ID of said second node to determine a a second one bit
position of said node address in said second address packet that is not
the same as a corresponding bit position of the processor ID of said
second node; and,
G. sending said second address packet out of the port number of said second
node corresponding to said second one bit position wherein n is the number
of the port on which said first address packet was received.
5. The method in accordance with claim 4 wherein said first address packet
includes a Forward bit set to one of either a first state or a second
state, said first address packet being immediately followed by a second
address packet, further comprising the steps of:
H. detecting a condition that said first node address in said first address
packet and said processor ID of said second node are the same; and,
I. transferring said first address packet to a local memory of said second
node in response to said condition that said node address in said first
address packet and said processor ID of said second node are the same.
6. The method in accordance with claim 4 wherein step C includes the step
of sending said first address packet out of an output port which has a
number higher than an input port on which said first address packet is
received.
7. The method in accordance with claim 4 further comprising the steps of:
H. detecting that said second address packet specifies a port number that
is identical to a port number specified in said first address packet,
I. blocking, at said second node, said second address packet; and,
J. unblocking, at said second node, said second address packet upon receipt
of an end of transmission (EOT) packet that specifies said second address
packet. |
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Claims |
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Description |
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CROSS-REFERENCE TO RELATED APPLICATION
U.S. Pat. No. 5,113,523 entitled "High Performance Computer System" of
Stephen R. Colley, et al., granted on May 12, 1992, assigned to Ncube
Corporation, and incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to data-processing systems, and more particularly, to
a communication mechanism for use in a high-performance,
parallel-processing system.
2. Description of the Prior Art
The above-referenced U.S. Pat. No. 5,113,523, describes a parallel
processor comprised of a plurality of processing nodes, each node
including a processor and a memory. Each processor includes means for
executing instructions, logic means connected to the memory for
interfacing the processor with the memory and means for internode
communication. The internode communication means connect the nodes to form
a first array of order n having a hypercube topology. A second array of
order n having nodes connected together in a hypercube topology is
interconnected with the first array to form an order n+1 array. The order
n+1 array is made up of the first and second arrays of order n, such that
a parallel processor system may be structured with any number of
processors that is a power of two. A set of I/O processors are connected
to the nodes of the arrays by means of I/O channels. The means for
internode communication comprises a serial data channel driven by a clock
that is common to all of the nodes.
In U.S. Pat. No. 4,729,095 of Colley et al granted Mar. 1, 1988 and
assigned to Ncube Corporation, there is described a broadcast pointer
instruction having a source operand which is the address in memory of a
message to be broadcast to a number of processors. The broadcast pointer
instruction also includes a destination operated which is a multibit mask.
A mask register is connected to output channel registers such that every
bit position in the mask register that is set to a predetermined value
will allow the corresponding output channel address register to be loaded.
Decoding means load the mask register with the mask bits of the
destination operand of the broadcast pointer instruction. A broadcast
count instruction is provided including a source operand which is a plural
bit integer equal to the number of bytes in the message. The broadcast
count instruction includes a destination operand which is a multibit mask.
As transmission progresses, the address register is incremented and the
count is decremented by the number of bytes transferred.
The prior art apparatus requires software controls to set up data paths,
route data to nodes over the paths created, and remove paths that are no
longer in service,
It is a primary object of the present invention to provide a new
communication mechanism for use in parallel processing system that will
provide for communication path creation, data transmission over the
created path, and path removal without the need for an external control.
SUMMARY OF THE INVENTION
Briefly, the above object is accomplished in accordance with an embodiment
of the present invention as follows.
Each node in a network of interconnected nodes includes a processor and a
plurality of communication ports. Each of the processors in the network is
assigned a unique processor identification (ID), with the processor IDs of
two processors connected to each other through port number n, varying only
in the nth bit. A plurality of input ports and a plurality of output ports
are provided at each node. Control means at one of the input ports of the
node receives address packets related to a current message from an output
port of another of the nodes. A data bus connects the input and output
ports of the node together such that messages received on any one input
port can be routed to any other output port. A compare logic compares a
node address in a first address packet with the processor ID of the node
to determine the bit position of the first difference between the node
address in the first address packet with the processor ID of the node. The
compare logic includes means for activating for transmission of the
message packet placed on the data bus by the input port, the one of the
plurality of output ports whose port number corresponds to the bit
position of the first difference, starting at bit n+1, where n is the
number of the port on which the message was received.
In accordance with an aspect of the invention, the processor includes a
local memory having a memory data bus for receiving data to be stored in
the memory, with the output ports being connected to the memory data bus.
The compare logic includes means for transferring the messages to the
local memory of the node upon the condition that the node address in the
first address packet and the processor ID of the node are the same.
In accordance with another aspect of the invention, the compare logic
includes blocking means for blocking, at the node, message packets
unrelated to the current message packets that specify the same port as the
current message packet; and, means are provided for generating an end of
transmission (EOT) signal upon receipt of an end of transmission (EOT)
message. The compare logic includes means responsive to the end of
transmission (EOT) signal for deactivating the blocking means.
In accordance with a further aspect of the invention, the current address
packet includes a forward bit capable of being set to a first state and a
second state, the current address packet being immediately followed by a
next address packet. Means are provide for examining the forward bit to
determine if the forward bit is set to the first state, and if it is, and
the address in the first address packet and the processor ID are the same,
and the address matches the PID, for discarding the address packet in the
received message. The compare logic includes means for comparing the node
address in the next address packet following the discarded current address
packet with the processor ID of the node to determine the bit position of
the first difference between the node address in the address packet with
the processor ID of the node; and for sending the next address packet out
the port number of the node corresponding to the bit position of the first
difference, starting at bit n+1, where n is the number of the port on
which the message was received.
The invention has the advantage that direct interconnection of I/O ports
eliminates off-chip88 communication logic.
The invention has the advantage that automatic cut-through message routing
allows messages to pass through intermediate nodes without interrupting
the central processing units (CPUs) of intermediate nodes.
The invention has the advantage that automatic message forwarding allows
communication between remote cube spaces, and arbitrary message path
routing.
The invention has the advantage that automatic disposal of messages having
illegal addresses prevents gridlock, by removing dead-end message paths.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features, and advantages of the invention
will be apparent from the following detailed description of a preferred
embodiment of the invention, as illustrated in the accompanying drawings
wherein:
FIG. 1 is a detailed block diagram of a processor in which the present
invention is embodied;
FIG. 2 is a block diagram of the 14 serial ports of the processor shown in
FIG. 1;
FIGS. 3A, 3B and 3C comprise a composite block diagram of a single serial
port representative of one of the 14 serial ports (16) on the processor
shown in FIG. 1:
FIG. 4 illustrates the interconnect and address scheme in an eight
processor network;
FIG. 5 illustrates the format of the 32 bit long address word;
FIG. 6 illustrates the format of a remote broadcast message;
FIG. 7 is an example of how a message is sent from a node address 0000 to a
destination node whose address is XXXX;
FIG. 8 illustrates the format of an address packet;
FIG. 9 illustrates the format of a data packet;
FIG. 10 illustrates the format of an Acknowledge (ACK) command packet;
FIG. 11 illustrates the format of an End of Message command packet;
FIG. 12 illustrates the format of an End of Transmission (EOT) command
packet;
FIG. 13 illustrates the Transmission Format; of a transmission consisting
of multiple messages;
FIG. 14 illustrates a transmission consisting of a single message is
initiated with the LCNT instruction;
FIG. 15 illustrates a transmission consisting of multiple messages is
initiated with the LPCNT instruction;
FIG. 16 illustrates a message path in a dimension 3 hypercube;
FIG. 17 illustrates how to calculate the time it takes a full message of
several packets to be sent from node 110 to node 001 in the hypercube of
FIG. 16;
FIG. 18 is a flow diagram of an input ready interrupt subroutine;
FIG. 19 is a flow diagram of an output ready interrupt subroutine;
FIG. 20 is a flow diagram of a send message subroutine; and,
FIG. 21 is a flow diagram of a receive message subroutine.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Communication between processors is accomplished via messages. Message
transmission proceeds in three stages: Path Creation, Data Transmission,
and Path Removal. Each stage is performed in turn by each processor in the
message path. To accomplish this, three architectural layers are provided,
the Interconnect Layer, the Routing Layer, and the Message Layer.
Interconnect Layer
The Interconnect Layer provides the hardware required for establishing
physical communication links. The following list describes major features
of the Interconnect Layer:
28 independent serial Direct Memory Access (DMA) channels provide 14
full-duplex I/O ports, allowing systems to be designed with up to a
dimension 13 hypercube (8,192 processors).
Direct interconnection of I/O ports eliminates off-chip communication
logic.
Variable communication speed of I/O ports allows matching the port speed to
the signal propagation time of the interconnect. This provides the ability
to support very large configurations, while allowing higher communication
rates on interconnects having shorter propagation delays.
Intersystem communication with remote hypercube spaces through the System
Interconnect (SI) I/O port, allows hypercubes to be networked with each
other, as well as with other systems.
Routing Layer
The Routing Layer provides the arbitration and switching logic for
creating, maintaining, and removing communication paths between processors
in the network. The following list describes major features of the Routing
Layer:
Automatic cut-through message routing allows messages to pass through
intermediate nodes without interrupting the intermediate node CPUs.
Automatic message broadcasting allows messages to be broadcast to remote
subcubes.
Automatic message forwarding allows communication between remote cube
spaces, and arbitrary message routing.
Automatic disposal of messages having illegal addresses prevents gridlock,
by re-moving dead-end message paths.
Automatic overrun control, via internode handshaking, allows reliable
message traffic through intermediate nodes across interconnects of
differing speeds.
Message Layer
The Message Layer provides the services for reliable and efficient
point-to-point data transfer between processors. The following list
describes major features of the Message Layer:
Interrupt driven communications software reduces the load on the CPU.
Messages are automatically broken into discrete packets during transmission
automatically reconstructed upon receipt.
DMA capability allows concurrent message transmission independent of CPU
activity.
Message transmission without path removal allows sending noncontiguous
data.
Automatic error detection allows a target node to respond to errors without
interrupting the CPUs of intermediate nodes.
Messages
A message can be visualized as a chain of packets being relayed from
processor to processor. The first packet contains an address that the
Routing Layer uses to determine which port or ports to use in creating the
next link or links in the path. The Routing Layer also uses the address to
determine whether to notify the CPU of message arrival. Complex
tree-structured and multi-node paths can be created using broadcasting and
forwarding techniques.
The channels that the address packet passes through as it moves from
processor node to processor node are automatically reserved for the data
packets that follow the address packet. The system is able to buffer up to
two packets on each incoming channel. The system will request another
packet a soon as it has space for it, until an End of Transmission (EOT)
packet arrives. As an EOT packet passes through a channel, it causes the
processors to release the channel for use by other messages.
A short message of a few packets could be stored entirely within channel
buffers of intermediate processors in the path, prior to the address
packet reaching the destination processor.
Any transmission errors detected by the intermediate processors are encoded
in the packets as they pass through. The transmission errors are then
detected by the destination processor.
The Interconnect Layer
The processor in which the present invention is embodied is shown in FIG.
1, and is comprised of Floating Point Execution Unit (40), Instruction
Decoder and interrupt decoder (12), operand FIFO cache (14), 14 serial
Ports (16), and Memory Interface (18) which is attached to memory (20).
Each of the 14 serial ports (16) is an independent Direct Memory Access
(DMA) channel. Each I/O channel can be connected directly to a
corresponding channel in another processor, thus eliminating the need for
off-chip communication logic.
Refer now to FIG. 2 which is a block diagram of the 14 serial Communication
Ports (16) shown in FIG. 1. 28 DMA I/O channels are arranged in pairs.
Fourteen channels handle input and fourteen channels handle output,
providing fourteen full-duplex I/O ports. This provides full support for
system designs with up to a dimension 13 hypercube (8,192 processors),
while allowing all processors direct I/O connection with processors
outside the hypercube array.
The DMA I/O channels operate independently of the CPU. A DMA channel begins
functioning whenever its DMA Count Register is set to a nonzero value. If
the address value in the DMA Address Register is larger than the memory
space, the high-order bits are ignored. All ports are general, except that
one input channel and one output channel, together called the System
Interconnect (SI) port, are normally used to communicate with other
hypercube spaces or foreign (non-hypercube) systems.
Each of the processors in the network is assigned a unique processor
identification (ID), stored in ID register (202), with the processor IDs
of two processors connected to each other through port number n, varying
only in the nth bit. The input decoder block (200) receives address
packets related to a current message from an output port of another of the
nodes. A data bus (210) connects the input and output ports of the node
together such that messages received on any one input port, such as port
1, can be routed to any other output port, such as port 14. A compare
logic (204) compares a node address in a first address packet with the
processor ID (202) of the node to determine the bit position of the first
difference between the node address in the first address packet with the
processor ID of the node. The compare logic includes means for activating
for transmission of the message packet placed on the data bus (210) by the
input port, the one of the plurality of output ports whose port number
corresponds to the bit position of the first difference, starting at bit
n+1, where n is the number of the port on which the message was received.
The memory arbitration logic (205, 206) of each port is connected to the
memory data bus for storing data in the local memory. The compare logic
(204) includes means for transferring the messages to the local memory of
the node upon the condition that the node address in the first address
packet and the processor ID (203) of the node are the same.
The compare logic (204) also includes blocking means for blocking, at the
node, message packets unrelated to the current message packets that
specify the same port as the current message packet. Means are provided
for generating an end of transmission (EOT) signal upon receipt of an end
of transmission (EOT) message. The compare logic includes means responsive
to the end of transmission (EOT) signal for deactivating the blocking
means.
The current address packet, shown in FIG. 5, includes a forward bit capable
of being set to a first state and a second state, the current address
packet being immediately followed by a next address packet as shown in
FIG. 6. Means are provide for examining the forward bit to determine if
the forward bit is set to the first state, and if it is, and the address
in the first address packet and the processor ID are the same, and the
address matches the PID, for discarding the address packet in the received
message. The compare logic includes means for comparing the node address
in the next address packet following the discarded current address packet
with the processor ID of the node to determine the bit position of the
first difference between the node address in the address packet with the
processor ID of the node; and for sending the next address packet out the
port number of the node corresponding to the bit position of the first
difference, starting at bit n+1, where n is the number of the port on
which the message was received.
FIGS. 3A and 3B comprise a composite block diagram of a single serial port
representative of one of the 14 serial ports (16) on the processor shown
in FIG. 1. The address pointers (168, 170) each contain a pointer to the
location in memory (20) of the least significant byte of the next word to
be transferred. In an output port, the data is moved from memory (20) over
the serial transmit interface (164) via 158, 160, 162. In an input port,
the data that has been received over the serial receive interface (150)
from the output port of the sending processor is moved to memory (20) via
152, 154, 156.
Each port has all the circuitry necessary to both receive and transmit
serial messages in full duplex. The format of the messages is described in
Section 5.4.1 of the above-identified Colley, et al. application. Data are
received on the serial receive line (150) and are framed in the input
shift register (152). The information is then transferred in parallel to
the input FIFO (154) and is stored there until it is transferred to the
memory (20) on the memory data in lines (156). Similarly, data to be
transmitted is brought in from the memory data out lines (158) and stored
in the output FIFO (160). From there it is transferred to the output shift
register (162), and transmitted serially on the serial transmit line (164)
after being combined with a parity bit from the parity-bit generator
(166).
The output byte counter (172) specifies the length of message to be sent.
All of the above-described registers are initialized by the appropriate
instruction: the load address pointer instruction, the load byte counter
instruction for single channel transfer, and the broadcast count
instruction for multiple channel transfer, as described in U.S. Pat. No.
4,729,095. After a message packet is received, the input address pointer
(168) is incremented by 4. After a message packet has been sent, the
output address pointer (170) is incremented by 4 and the output byte
counter (172) is decremented by 4.
There is an input port controller (174) and an output controller (178)
which control the timing of the serial transmission. These controllers
control the timing of when the parity bit is sent out and when the parity
bit is to be checked on incoming data. They also control the various
flags. The parity error flag (180) is set by the input controller when
there is a parity error detected on an input message by parity check logic
(181). The input message pending flag (182) is set by the input controller
during the time that the input FIFO (154) is buffering a message which has
not yet been transferred into memory. The overrun error flag (184) is
never in an asserted state since the sender (controlled by 178) only sends
data when the receiver ready flag (190) is set as signalled by ACK. The
input enable flag (186) is a flag which is both readable and writable by
the user to enable interrupts that occur when the input port becomes ready
and the input message ready flag (187) is set. The input message ready
flag (187) is set in response to receipt of an End of Message or End of
Transmission packet.
On the output port there is an output enable flag (188) which, when
enabled, will generate an interrupt when the output message ready flag
(189) is set, i.e., when the output byte counter (172) goes to zero,
signifying that the entire message has been transmitted. This signals the
user that it is necessary to reinitialize the port with a new message. The
receiver ready flag (190) is set when the connected input port can receive
another word (as signalled by ACK). The broadcast flag (192) is
initialized by the broadcast count instruction. When this flag is set, it
indicates that this particular output port is a member of the current
broadcast group. When an output port is a member of the current broadcast
group, then any data coming over the memory data out bus (158) for
broadcasting will be transmitted out of this port and simultaneously out
of all other ports that have their broadcast flags on.
The port interrupt logic (194) generates interrupts if enabled when the
input or output ports have finished transmitting or receiving messages, as
signaled by the appropriate flag, input enable (186) or output enable
(188) being set.
The port memory arbitration logic (196) performs the function of
arbitrating for memory with all the other serial ports. The winner of this
arbitration must again arbitrate with other units on the chip in the
memory interface unit (18) of FIG. 1 as described in Section 8.8 of the
above-identified Colley, et al. application. When a port memory
arbitration is successful the memory request line (200) is energized. When
a memory grant is given, the memory grant line (202) indicates that data
either has been taken from the memory data in bus (156) or that the data
is available on the memory data out bus (158).
Each output channel has an output address pointer (170), an output byte
count register (172), an output message ready flag (189) and an output
enable flag (188). Each input channel has a parity error flag (180), an
overrun error flag (184) and an input enable flag (186). Besides the
enable for each channel there are two global enable flags in the Program
Status (PS) register. The global enable (II) flag disables all input
interrupts (including errors) even if the corresponding channel flag is
enabled and the global enable (IO) flag disables all output interrupts.
In order to send a message from a memory buffer on a single output channel,
a processor first either checks the channel's ready flag or enables its
interrupt and waits for a "ready" interrupt. As soon as the channel
indicates that it is ready (idle), the output address pointer (170) is set
to point to the first (low) byte of the message, which must begin on a
word boundary. This is accomplished by executing a LPTR (Load Pointer)
instruction as described in U.S. Pat. No. 4,729,095. The source (src)
operand of this instruction is the address of the message buffer and the
destination (des) operand is an integer whose value determines which of
the channel registers is to be loaded.
In order to start the automatic message output, the output byte counter
(172) must be set to the number of bytes in the message. The two low order
bits are forced to zero in both the output address pointer (170) and the
output byte counter (172); thus the message buffer must start on a word
boundary. This is done by executing a LCNT (Load Count) instruction. The
destination operand indicates the register to be loaded as explained above
for the LPTR instruction and the source operand is the count value (an
unsigned 32 bit integer). The LCNT instruction also resets the parity
(181) and overrun error flag (184) when setting up an input port. The
message transmission is automatic and as data is sent the output address
pointer (170) is incremented and the output byte counter (172) is
decremented by the number of bytes transferred. When the output byte count
becomes zero the output transmission stops, the output message ready flag
(189) is set and, if the output enable flag (188) is set, the ready
interrupt is generated.
A channel's Address Register (168, 172) contains a pointer to the least
significant byte of the next word to be transferred. If it is an output
channel, the data is moved from memory out to the channel. If it is an
input channel, the data that has been received is moved to memory. The
Count Register (172) in the output channel is set to indicate the number
of bytes to be sent. As data are sent, the output channel Address pointer
(170) is incremented by the number of bytes transferred, and the Byte
Counter (172) is decremented by the number of bytes transferred. When the
count reaches zero, an End of Message (EOM) packet or an End of
Transmission (EOT) packet is sent to the receiver, the appropriate bit in
the Output Message Ready Register or the Output Transmission Ready
Register, or both, is set, and an Output Ready interrupt is generated, if
enabled. As data is received, the input channel DMA Address Register is
incremented by the number of bytes transferred. When an EOM or EOT packet
is received, the appropriate bit in the Input Message Ready Register is
set to ready, and an Input Ready interrupt, if enabled, is generated by
interrupt logic (194).
Channel numbers are used in connection with the LPTR, LCNT, and LPCNT
Communication Control instructions to address the channel to be loaded.
The input and output port registers are addressed according to Table I.
TABLE 1
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Use To Access Use To Access
Channel Input Port Channel Output Port
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0 0 32 0
1 1 33 1
2 2 34 2
3 3 35 3
4 4 36 4
5 5 37 5
6 6 38 6
7 7 39 7
8 8 40 8
9 9 41 9
10 10 42 10
11 11 43 11
12 12 44 12
31 SI 63 SI
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Channels 0 through 12 and 31 are input channels. C | | |
