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Claims  |
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What is claimed is:
1. A method for fabricating an electronic device comprising the steps of:
utilizing a substrate having a first and a second surface;
forming a first conductive layer above said first surface of said
substrate;
forming a patterned dielectric layer above said first conductive layer; and
forming a patterned thin film conductor above said patterned dielectric
layer in a pattern to provide an inductor having a desired inductance
value and which makes electrical contact with said first conductive layer.
2. A method as in claim 1 wherein said substrate comprises a conductive or
semiconductive material, and which further comprises the step of forming
an insulating layer above said first surface of said substrate, thereby
insulating said first conductive layer from said substrate.
3. A method as in claim 2 wherein said substrate comprises silicon,
Al.sub.2 O.sub.3 -TiC, or a conductive ferromagnetic material.
4. A method as in claim 2 which further comprises the step of forming vias
in said layer of insulation to allow electrical connection between said
substrate and one or both of said conductive layer and thin film
conductor.
5. A method as in claim 1 wherein said substrate comprises an insulating
substrate.
6. A method as in claim 2 wherein said substrate comprises a semiconductive
material and which method further comprises the step of forming one or
more semiconductor devices in said semiconductive substrate.
7. A method as in claim 6 wherein said inductor is formed adjacent to said
one or more semiconductor devices.
8. A method as in claim 6 wherein said inductor is formed above said one or
more semiconductor devices.
9. A method as in claim 6 wherein said semiconductor devices are formed on
said second surface of said substrate.
10. A method as in claim 1 which further comprises the steps of fabricating
one or more devices, selected from the group consisting of thin film
resistors and capacitors, on said substrate.
11. A method as in claim 10 wherein said inductor is formed above one or
more of said thin film resistors and capacitors.
12. A method as in claim 10 wherein said inductor is formed adjacent one or
more of said thin film resistors and capacitors.
13. A method as in claim 10 wherein said substrate comprises semiconductor
material containing one or more semiconductor devices and in which said
one or more inductors, resistors, and capacitors are fabricated above at
least one of said one or more of semiconductor devices.
14. A method as in claim 1 which further comprises the step of forming a
core material on at least one side of said inductor.
15. A method as in claim 1 which further comprises the step of forming a
core material on both top and bottom of said inductor.
16. A method as in claim 14 wherein said core material comprises iron,
NiFe, sandust, or a ferromagnetic material.
17. A method as in claim 15 wherein said core material comprises iron,
NiFe, sandust, or a ferromagnetic material.
18. A method as in claim 1 which further comprises the step of forming a
set of studs for the formation of said patterned thin film conductor such
that said patterned thin film conductor is supported by said studs and,
between said studs, is separated from underlying layers.
19. A method as in claim 18 which further comprises the step of forming a
clamping layer on said conductive layer to attach said conductive later to
said studs.
20. A method as in claim 19 which further comprises the step of forming a
passivation layer on the surface of the device.
21. A method as in claim 18 which further comprises the step of passivating
said thin film with photoresist.
22. A method as in claim 1 wherein said first conductive layer comprises a
resistive layer serving as one or more resistor devices.
23. A method as in claim 1 wherein said first conductive layer comprises a
material selected from the group of materials consisting of aluminum,
copper, silver, gold, polycrystalline silicon, and alloys thereof.
24. A method as in claim 1 which further comprises a step of forming a
capacitor having said substrate serving as its first plate and said first
conductive layer serving as its second plate.
25. A method as in claim 1 wherein said first conductive layer is patterned
to form one or more electrical interconnects.
26. A method as in claim 25 wherein said first conductive layer also serves
as one plate of a capacitor.
27. A method as in claim 1 wherein said first conductive layer comprises a
resistive material selected from the group of materials consisting of TaN,
nichrome, and polycrystalline silicon.
28. A method as in claim 5 wherein said substrate comprises glass, quartz,
or ceramic material.
29. A method as in claim 6 wherein said step of forming said one or more
semiconductor devices is performed prior to said step of forming a
patterned dielectric layer above said first conductive layer and prior to
said step of forming a patterned thin film conductor, wherein said step of
forming a patterned dielectric layer and said step of forming a patterned
thin film conductor are performed at sufficiently low temperatures to
prevent a deterioration of said semiconductor devices.
30. A method as in claim 6 which further comprises the steps of fabricating
one or more devices, selected from the group consisting of thin film
resistors and capacitors, on said substrate.
31. A method as in claim 30 wherein said inductor is formed above one or
more of said thin film resistors and capacitors.
32. A method as in claim 30 wherein said inductor is formed adjacent one or
more of said thin film resistors and capacitors.
33. A method as in claim 30 wherein said substrate comprises semiconductor
material and in which said one or more inductors, resistors, and
capacitors are fabricated above said semiconductor devices.
34. A method as in claim 30 wherein said first conductive layer is
patterned to form one or more electrical interconnects.
35. A method as in claim 10 wherein said first conductive layer is
patterned to form one or more electrical interconnects.
36. A method as in claim 13 wherein said first conductive layer is
patterned to form one or more electrical interconnects.
37. A method for fabricating an electronic device utilizing a substrate
comprising the steps of:
forming a first patterned conductive layer above said substrate;
forming a first patterned dielectric layer, exposing those areas of said
first conductive layer to which electrical contact is to be made; and
forming a second conductive layer on said first patterned dielectric layer
in a pattern to form an inductor coil.
38. A method as in claim 37 wherein said substrate comprises a
semiconductor or conductive material and wherein said method comprises the
additional step of forming a base dielectric layer between said substrate
and said first conductive layer.
39. A method as in the claim 38 wherein said step of forming said base
dielectric layer comprises the step of forming said base dielectric layer
in a pattern to expose those portions of said substrate to which
electrical contact is to be made.
40. A method as in claim 37 wherein said substrate comprises glass, quartz,
Al.sub.2 O.sub.3 /TiC, or ceramic materials.
41. A method as in claim 38 wherein said substrate comprises conductive
ferromagnetic material or semiconductor material.
42. A method as in the claim 41 wherein said substrate comprises silicon.
43. A method as in claim 38 wherein said base dielectric layer comprises
silicon dioxide of approximately 10,000 .ANG. in thickness.
44. A method as in claim 37 wherein said first conductive layer comprises
aluminum, copper, silver, gold, polycrystalline silicon, or an alloy
thereof.
45. A method as in claim 44 wherein said first conductive layer is formed
to a thickness of approximately 5,000 .ANG..
46. A method as in claim 37 wherein said first dielectric layer comprises
one or more materials selected from the group of materials consisting of
silicon dioxide and silicon nitride, formed to a thickness within the
range of 2,000 to 10,000 .ANG..
47. A method as in claim 38 wherein said first dielectric layer comprises
one or more materials selected from the group of materials consisting of
silicon dioxide and silicon.
48. A method as in claim 38 wherein said base dielectric layer comprises a
layer of baked photoresist.
49. A method as in claim 48 wherein said layer of baked photoresist is
formed to a thickness within the range of approximately 1-5 microns.
50. A method as in claim 38 wherein said step of forming said base
dielectric layer comprises the steps of:
applying the photoresist material to the top surface of said device; and
stabilizing said layer of photoresist.
51. A method as in claim 50 wherein said step of stabilizing comprises
baking said photoresist.
52. A method as in claim 51 wherein said step of baking comprises baking
within the range of approximately 200.degree.-300.degree. C. for
approximately 6 to 12 hours in a vacuum or inert environment.
53. A method as in claim 50 wherein said step of stabilizing comprises
polymerizing said photoresist.
54. A method as in claim 53 wherein said step of polymerizing is performed
utilizing an electron beam.
55. A method as in claim 37 wherein said second conductive layer comprises
aluminum, copper, silver, gold, or an alloy thereof.
56. A method as in claim 37 wherein said step of forming said second
metallization layer comprising the steps of:
forming a seed layer of conductive material on the surface of the device in
a pattern resembling the desired pattern of the to-be-formed conductive
layer;
forming a layer of masking material on the surface of the device in a
pattern to expose those portions of said seed layer where the inductor
coil is to be formed;
electroplating additional metal material to exposed portions of said seed
layer;
removing said masking layer; and
removing those portions of said seed layer not covered by said additional
conductive material.
57. A method as in claim 56 wherein said seed layer comprises TiW, Cu, Pd,
Ti, Ni, Cr, Ag, Au, NiFe, or an alloy thereof.
58. A method as in claim 57 wherein said seed layer comprises a first layer
of TiW formed to a thickness of approximately 200 .ANG. and a second layer
of copper formed to a thickness of approximately 1,000 .ANG..
59. A method as in claim 56 wherein said additional metal material
comprises copper, silver, or gold, or an alloy thereof.
60. A method as in claim 56 wherein said additional metal material is
formed to a thickness in the range of approximately 3 to 10 microns.
61. A method as in claim 37 wherein said step of forming said inductor coil
comprises the steps of:
forming a layer of metallization;
forming a mask in a desired pattern to protect those portions of said
metallization layer which are to form said inductor coil; and
removing exposed portions of said metallization layer.
62. A method as in claim 37 which further comprises the step of forming a
layer of passivation on the surface of the device.
63. A method as in 62 wherein said step of forming a layer of passivation
comprises the step of forming a layer of photoresist.
64. A method as in 63 wherein said step of forming a layer of photoresist
comprises forming a layer of photoresist to a thickness within the range
of approximately 1 to 5 microns.
65. A method as in claim 63 which further comprises the step of stabilizing
said layer of photoresist.
66. A method as in claim 65 wherein said step of stabilizing said layer of
photoresist comprises the step of baking said photoresist.
67. A method as in claim 66 wherein said step of baking comprises baking
within the range of approximately 200.degree. to 300.degree. C. for
approximately 6 to 12 hours in a vacuum or inert environment.
68. A method as in claim 65 wherein said step of stabilizing comprises
polymerizing said photoresist.
69. A method as in claim 68 wherein said step of polymerizing is performed
utilizing an electron beam.
70. A method as in claims 37 wherein said step of forming a second
conductive layer comprises the steps of:
forming a second layer of dielectric on said first dielectric layer, in
areas where support studs are to be formed;
forming a third layer of dielectric material which is capable of being
selectively etched with respect to said second layer of dielectric
material;
removing said third layer of said material from above said support studs;
forming a patterned conductive layer above said second and third dielectric
layers in a pattern defining an inductor coil; and
removing at least portions of said third layer of dielectric material
beneath said inductor coil.
71. A method as in claim 70 wherein said second layer of dielectric
material comprises a durable photoresist and said third layer of
dielectric material comprises a layer of photoresist less durable than
said second layer of dielectric material.
72. A method as in claim 70 wherein said second layer material of
dielectric material comprises material selected from the group of
materials consisting of oxide, nitride, and Al.sub.2 O.sub.3.
73. A method as in claim 72 wherein said third layer of dielectric material
comprises photoresist.
74. A method as in claim 72 wherein said third layer of dielectric material
comprises material selected from the group of materials consisting of
oxide, nitride, and Al.sub.2 O.sub.3 other than the material used as said
second layer of dielectric.
75. A method as in claim 72 wherein said second layer of dielectric
material is formed to a thickness within the range of approximately 3 to
10 microns.
76. A method as in claim 72 wherein said third layer material is formed to
a thickness from the range of approximately 2 to 10 microns.
77. A method as in claim 72 wherein said step of forming said third
dielectric layer comprises the steps of:
applying photoresist material to the top surface of said device; and
stabilizing said layer of photoresist.
78. A method as in claims 77 wherein said step of stabilizing comprises
baking said photoresist.
79. A method as in claim 78 wherein said step of baking comprises baking at
approximately 100.degree. C. for approximately 30 minutes in a vacuum or
inert environment.
80. A method as in claim 70 wherein said step of forming said patterned
conductive layer comprising the steps of:
forming a seed layer of conductive material on the surface of the device in
a pattern resembling the desired pattern of the to-be-formed conductive
layer;
forming a layer of masking material on the surface of the device in a
pattern to expose those portions of said seed layer where the inductor
coil is to be formed;
electroplating additional metal material to exposed portions of said seed
layer;
removing said masking layer; and
removing those portions of said seed layer not covered by said additional
conductive material.
81. A method as in claim 80 wherein said seed layer comprises TiW, Cu, Pd,
Ti, Ni, Cr, Ag, Au, NiFe, or an alloy thereof.
82. A method as in claim 80 wherein said seed layer comprises a first layer
of TiW formed to a thickness of approximately 200 .ANG. and a second layer
of copper formed to a thickness of approximately 1,000 .ANG..
83. A method as in claim 80 wherein said additional metal material
comprises copper, silver, or gold, or an alloy thereof.
84. A method as in claim 80 wherein said additional metal material is
formed to a thickness in the range of approximately 3 to 10 microns.
85. A method as in claim 80 wherein said step of forming said patterned
conductive layer comprises the steps of:
forming a layer of metallization;
forming a mask in a desired pattern to protect those portions of said
metallization layer which are to form said inductor coil; and
removing exposed portions of said layer of metallization.
86. A method as in claim 80 further comprises the step of forming a
clamping layer above at least portions of said inductor coil.
87. A method as in claim 86 wherein said step of forming a clamping layer
comprises the step of forming a layer of material selected from the group
of materials selected from the group of materials consisting of oxide,
nitride, and photoresist.
88. A method as in claim 86 wherein said step of forming a clamping layer
is performed after said step of removing said third dielectric layer.
89. A method as in claim 86 wherein said step of forming a clamping layer
is performed before said step of removing said third dielectric layer.
90. A method as in claim 85 which further comprises the step of forming a
passivation layer.
91. A method as in claim 86 which further comprises the step of forming a
passivation layer.
92. A method as in claim 85 wherein said step of forming a layer of
metallization serving as inductor coils also forms portions of said layer
of metallization serving as electrical interconnects.
93. A method as in claim 92 wherein at least a portion of said electrical
interconnects are formed on support studs.
94. A method as in claim 37 wherein said step of forming said second
conductive layer comprises the step of:
forming a layer of core material of a desired permeability, in a desired
pattern;
forming a first layer of insulating material above said core material
layer;
forming a second conductive layer in a pattern defining one or more
inductor coils.
95. A method as in claim 94 which further comprises the steps of:
forming a second insulation layer above said second conductive layer; and
forming a second layer of core material of a desired permeability above
said second insulating layer.
96. A method as in claim 70 wherein said third layer of dielectric
comprises material which can be selectively etched with respect to said
studs.
97. A method as in claim 37 wherein said substrate comprises a
ferromagnetic material.
98. A method as in claim 37 which further comprises the steps of forming
one or more layers of ferromagnetic core material in the vicinity of said
inductor coil.
99. A method as in claim 98 wherein said one or more layers of
ferromagnetic core material comprise a layer of ferromagnetic material
located below and insulated from said inductor coil.
100. A method as in claim 98 wherein said one or more layers of
ferromagnetic core material comprise a layer of ferromagnetic material
located above and insulated from said inductor coil.
101. A method as in claim 98 wherein said layer of ferromagnetic core
material comprises Ni/Fe, sandust, iron, or ferrites.
102. A method as in claim 98 wherein said one or more layers of
ferromagnetic core material comprise Ni/Fe, having Fe within the range of
approximately 20 to 60 percent by weight.
103. A method as in claim 98 wherein said step of forming said one or more
layers of ferromagnetic core material is performed by deposition or
sputtering.
104. A method as in claim 95 wherein said step of forming said one or more
layers of ferromagnetic core material comprises the steps of:
forming a seed layer in a desired pattern; and
electroplating said ferromagnetic material onto said seed layer.
105. A method as in claim 104 wherein said seed layer is formed of Ni/Fe.
106. A method as in claim 104 wherein said seed layer is formed to a
thickness of approximately 1,000 .ANG..
107. A method as in claim 104 wherein each said layer of ferromagnetic core
material is formed to a thickness within the range of approximately 1 to 5
microns. |
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Claims |
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Description |
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FIELD OF THE INVENTION
This invention relates generally to the integration of passive components
on a single substrate, with or without other semiconductor components and
devices. In particular, it relates to integration of resistors, capacitors
and inductors on the same substrate with or without semiconductor devices.
BACKGROUND OF THE INVENTION
In the past inductors have been fabricated using conductive coils with or
without high permeability cores such as ferrites, as shown in FIG. 1. The
inductor is mounted on a substrate and then mounted on a circuit board
according to application desired. Integration of these coils with
resistors, capacitors, resistor-capacitor networks, or semiconductor
devices have not been achieved. Typically, whenever a coil is used as an
inductor, it is mounted as a separate part in series with the integrated
circuit to achieve the desired functions.
Inductors fabricated using wound coils inherently provide low resistance
for a given inductance value, because of their wire thickness and high
inductance due to the use of ferrites or other high permeability materials
as the core. The combination of coil inductor with other passive
components or integrated circuits consumes space on a printed circuit
board and also results in a performance degradation due to the necessary
interconnects. While several attempts have been made to integrate
inductors with integrated circuits, the process used for doing these
integrations is complex and expensive. Such prior art is described in
Electromagnetics for Engineers, Steven G. Schwartz, Saunders College
Publishing, 1990. FIG. 2 shows a top view of a prior art thin film
inductor, which is fabricated on a GaAs or ceramic substrate.
Many modern applications, particularly high frequency applications, lend
themselves to the integration of inductors with other passive components
such as resistors, capacitors, and semiconductor integrated circuits. The
integration necessity stems from cost savings, reliability, performance
improvements, and space savings on circuit boards and general
miniaturization in height, length, and width.
OBJECTS OF THE INVENTION
It is an object of the invention to provide a process for the fabrication
of an inductor.
It is another object of the invention to provide various options of
fabrication leading to various frequency applications of the inductor,
thus covering range of applications from 0-50 Ghz.
It is still another object of this invention to provide for integration of
inductors with other passive components such as resistors, capacitors, and
resistor-capacitor networks.
It is further an object of this invention to provide for integration of
inductors with semiconductor integrated circuits.
It is yet another object of the invention to provide methods for reducing
the parasitic capacitance of inductors to extend the inductor application
to higher frequencies.
It is further an object of the invention to fabricate inductors on top of
existing devices such as integrated circuits, and on the backside of a
substrate, to save integrated circuit surface area, leading to additional
cost saving.
It is still further an object of this invention to fabricate inductors
using various substrates such as, but not limited to, silicon, ceramic,
glass, quartz, Alumina, Al.sub.2 O.sub.3 TiC, ferromagnetic materials,
etc.
It is still further an object of this invention to provide a method of
fabricating inductor networks, inductor-capacitor networks,
inductor-resistor networks, and inductor-capacitor- and resistor networks.
It is further an object of this invention to provide a method for the
fabrication of inductors with high permeability cores to increase
inductance, and which are capable of being integrated with other
components or circuits.
It is further an object of this invention to fabricate inductor-diode
networks, with or without integration with resistors, capacitors, or
resistor-capacitor networks.
It is still further an object of this invention to provide a variety of
packaging and bonding options for inductors and inductors integrated with
other components.
It is still further an object of this invention to provide a variety of
passivation options for the fabrication of inductors and integrated
inductors.
It is still further an object of this invention to provide multilayer
and/or multiturn inductors for applications in various frequency ranges
(i.e. from 1 turn to greater than 100 turns).
It is another object of this invention to provide a method and structure
for clamping inductor coils or interconnects to minimize damage during
handling, processing, packaging, or use of passive or active devices.
SUMMARY
The foregoing and other objects of the invention may generally be achieved
by the fabrication of the passive components or semiconductor devices with
known techniques or new techniques and then fabricating inductors as
described in this invention.
In another embodiment of this invention, an inductor is fabricated
initially on a substrate and then integrated with other devices
subsequently formed on the substrate. In this embodiment, process steps
used to fabricate such other devices utilize temperatures sufficiently low
to prevent damaging or destroying the characteristics of the inductor.
In one embodiment of this invention, the fabrication of an inductor is
achieved through photoresist masking and plating techniques. In
alternative embodiments, fabrication of an inductor is achieved by
sputtering, photoresist processes and etching/ion-milling techniques. A
combination of various individual process steps from various embodiments
are suitable for use to fabricate the individual layers to achieve a
structure of this invention.
The inductor fabricated in accordance with this invention is connected to
other passive or active components through metal interconnections in order
to improve the frequency performance of the inductor. In certain
embodiments, parasitic capacitance of the inductor is significantly
reduced by fabricating inductor coils on dielectric bridges. In certain
embodiments, a magnetic core of ferromagnetic material such as NiFe alloy,
sandust, or ferrite is used to improve the performance of the inductor at
frequencies below about 100 MHz.
BRIEF DESCRIPTION OF DRAWINGS
The foregoing and other objects of the invention will become apparent in
reading the following detailed description and in reference to the
following drawings:
FIG. 1 shows a prior art inductor fabricated using a wire coil;
FIG. 2 shows the layout of a prior art thin film inductor;
FIG. 3 shows the layout of one embodiment of an integrated LRC network
constructed in accordance with the present invention;
FIG. 4 is a schematic diagram of the LRC network of FIG. 3;
FIG. 5 is a cross-sectional view of an integrated LRC network such as that
shown in FIG. 3;
FIGS. 6a-6f depict the cross-sectional views of the fabrication steps of a
medium frequency inductor without a magnetic core in accordance with this
invention;
FIGS. 7-1 and 7-2 depict cross-sectional views of alternative fabrication
steps which may be employed to fabricate patterned metalization layer 63
of FIG. 6e;
FIGS. 8a-8g depict cross-sectional views of the fabrication steps of an
inductor placed on air bridge and having inherent low parasitic
capacitances making it suitable for high frequency applications;
FIG. 9 is a top view of one embodiment of an air bridge inductor fabricated
in accordance with the present invention;
FIGS. 10a-10i are cross-sectional views depicting an inductor fabricated
with a magnetic core in accordance with one embodiment of this invention;
FIG. 11 depicts a cross sectional view of an inductor fabricated in
accordance with one embodiment of this invention which is integrated with
a semiconductor device;
FIG. 12 is a cross-sectional view depicting one embodiment of this
invention in which semiconductor devices are fabricated on one surface of
a substrate and passive components such as inductors are fabricated on the
opposite surface of the substrate; and
FIG. 13 is a cross sectional view of one embodiment of a multiple layer
thin film inductor structure of this invention.
DETAILED DESCRIPTION
FIG. 3 is a top view of an example of a structure constructed in accordance
with the teachings of this invention which includes a plurality of RLC
networks, each including a thin film resistor (39-1 through 39-3),
capacitor (40-1 through 40-3), and inductor (36-1 through 36-3).
FIG. 4 is a schematic diagram depicting one way of interconnecting one set
of thin film resistor, capacitor, and inductor of the circuit of FIG. 3 as
an RLC network, with similar reference numerals used. Thus, referring to
FIGS. 3 and 4, this embodiment includes an inductor 36 having an inductor
coil terminal pad 38 suitable for connection to external devices. As show
in FIG. 3, thin film resistor 39 is formed as a patterned thin film
resistive layer and capacitor 40 is formed of two plates. In the
embodiment in which the substrate on which a thin film network of FIGS. 3
and 4 is formed comprises a semiconductor material, one plate of capacitor
40 is, if desired, conveniently formed as a portion of that semiconductor
material, with terminal 41 serving as a connection to that substrate plate
of capacitor 40. Naturally, it will be appreciated by those of ordinary
skill in the art in light of the teachings of this invention that the
combination of thin film resistor, capacitor, and inductor can be
electrically interconnected in different ways to obtain different
electrical characteristics and furthermore that the electrical
characteristic of each component can be selected over a wide range.
Furthermore, any number, including zero, of each of thin film resistors,
capacitors, and inductors can be integrated to achieve more complex
circuit functions. Also, such combination of thin film resistors,
capacitors, and inductors can be integrated with semiconductor devices
such as those which are fabricated using well known semiconductor
processing techniques prior to the formation of the thin film resistors,
capacitors, and inductors, which thin film devices are constructed in
accordance with certain embodiments of this invention utilizing low
temperature processes which will not adversely affect previously
fabricated semiconductor devices and regions.
FIG. 5 is a cross-sectional view of the embodiment of FIG. 3, with similar
reference numerals used. As shown in FIG. 5, layer 33 serves as a
resistive layer, thereby forming resistor 39 at the location shown.
Resistive layer 33 is conveniently formed of a suitable resistive material
and, if necessary, doped or otherwise treated to have a desired
resistivity. Suitable materials for resistive layer 33 include TaN,
Nichrome, polycrystalline silicon, etc. Still referring to FIG. 5,
resistive layer 33 serves as a top plate of capacitor 40 which is
inherently connected to one end of resistor 39 and which is connected
through via 48 to one end of inductor 36 for the circuit configuration of
this example which is shown in FIG. 4. Substrate 30 serves as the opposite
plate of capacitor 40 in this example, and contact to this substrate plate
capacitor 40 could be made on the top surface of the device utilizing a
suitable via making contact with substrate 30, or through a backside
contact 41 as shown in FIG. 5. A passivation layer 49 protects the surface
of the device. Also shown in FIG. 5 are dielectric layers 31 and 32,
inductor coil terminal pad 34, and dielectric layers 35 and 37.
FIGS. 6a-6f are cross-sectional views illustrating an inductor fabricated
in accordance with one embodiment of this invention. This embodiment
provides an inductor suitable for medium frequency (approximately 50 MHz-1
GHz) applications. In this exemplary embodiment, substrate 71 is heavily
doped N type silicon. However other substrates such as glass, quartz,
Al.sub.2 O.sub.3 /TiC, ceramics, ferromagnetic materials, and
semiconductor materials other than silicon are also appropriate substrate
materials, and different doping types and levels are also suitable when
semiconductor material is used as substrate 71. In one embodiment,
substrate 71 is silicon of <100> crystal orientation, consistent with
typical semiconductor silicon substrates, although other silicon of other
crystal orientations is suitable for use as substrate 71. Also, when a
semiconductor material is used as substrate 71, either P or N conductivity
type is suitable, as well as any convenient doping level, although heavier
doping is desirable when capacitors are formed in accordance with this
invention in which one capacitor plate is formed as a portion of substrate
71.
A layer of dielectric material 72 is grown or deposited on the surface of
substrate 71, as shown in FIG. 6a. In one embodiment, dielectric layer 72
is formed of thermally grown silicon dioxide of approximately 10,000 .ANG.
in thickness. Alternatively, other dielectric material can be used as
dielectric layer 72, such as silicon nitride or a sandwich of oxide and
nitride.
As shown in FIG. 6b, a layer of metal 73 is formed on the surface of
dielectric layer 72. In one embodiment, metal layer 73 is aluminum or an
aluminum alloy, which is formed by sputtering to an approximate thickness
of 5000 .ANG.. Other metals and conductive materials are also suitable,
such as copper, aluminum, silver, gold, and the like, which may be formed
to desired thicknesses based on conductivity, current handling, and
reliability requirements.
Referring to FIG. 6b, metal layer 73 is patterned to form the desired
electrical interconnect pattern (not shown) and inductor coil terminal pad
78 for, ultimately, external connection to one side of the to-be-formed
inductor. This step of patterning metal layer 73 may be conveniently
performed using conventional photoresist masking techniques, followed by
removal of exposed portions of metal layer 73, for example by conventional
processes such as plasma or chemical etching, or ion milling. If desired,
this step of forming conductive interconnects can be simultaneously used
to fabricate electrical interconnects for use with active components
previously formed in a semiconductor substrate 71.
Another layer of dielectric material 74 is formed on the surface of the
device, as shown in FIG. 6c. In one embodiment dielectric layer 74 is
silicon dioxide or nitride deposited by a Chemical Vapor Deposition (CVD)
process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process,
for example to a thickness within the range of approximately 2000 .ANG. to
10,000 .ANG.. Alternatively, a layer of baked photoresist (typical
thickness of 1-5 microns) is used as dielectric layer 74, which is
selectively patterned to remain at desired areas through a conventional
photoresist masking process and then baked at approximately
200.degree.-300.degree. C. for approximately six to twelve hours in a
vacuum or inert environment to form desired dielectric layer 74.
Alternatively, an electron beam is used to polymerize photoresist to form
a stable dielectric layer.
In an embodiment in which dielectric layer 74 is oxide or nitride,
conventional photoresist and etching processes are used to remove portions
of dielectric layer 74 from selected areas to allow electrical connection
to portions of metal layer 74, such as at area 75 to allow electrical
contact to inductor coil terminal pad 78 and thus one end of the inductor.
Such a photoresist process typically consists of applying photoresist,
bake, exposure to ultraviolet light with an appropriate mask, photoresist
develop, and removal of undesired portions of the dielectric, for example
by chemical or oxygen plasma, as is well known in the art. This exposes a
portion of dielectric layer 74 where contact to underlying metal is to be
made, for example to inductor terminal pad 78.
An inductor coil is now formed on dielectric layer 74, in one of a number
of possible ways, each of which consists of forming an inductor coil of
conductive traces 76 (FIG. 6f). Any one or more of a number of conductive
materials can be used to form conductive traces 76, including but not
limited to aluminum, copper, silver, and gold. The thickness and area of
conductive traces 76 is chosen based on desired conductivity, reliability,
and performance desired.
In one embodiment, depicted in FIGS. 6d and 6e, a layer of conductive
material 61 is formed and masked to expose the desired inductor coil
pattern, with any desired electrical interconnects (not shown) being
formed simultaneously and which can, if desired, make physical and
electrical contact to inductor coil terminal pad 78. In this embodiment, a
conductive layer 61 serves as a seed layer is formed on the surface of the
device. The seed layer may comprise any one or more materials which
provide a suitable interface with good adhesion qualities, such as but not
necessarily limited to any one or combination of TiW, Cu, Pd, Ti, Ni, Cr,
Ag, Au, and NiFe. In one embodiment, seed layer 61 is formed of a first
layer of TiW of a thickness of approximately 200 .ANG., and a second layer
of copper formed to a thickness of approximately 1000 .ANG., which layers
may be conveniently formed using conventional sputtering or other vacuum
deposition techniques. A layer of photoresist 62 is then formed and
patterned to expose those portions of seed layer 61 where the inductor
coil is to be formed. The inductor coil is then formed, for example by
electroplating to exposed portions of seed layer 61 another layer of
conductive material 63 (FIG. 6e), such as copper, gold or silver, which
may be conveniently formed by a conventional electroplating process onto
the seed layer inductor coil pattern, for example to a thickness of
approximately 3-10 microns. Other conductive materials can be used for
form inductor coils 76, which have adequate electrical and thermal
conductivity and are suitably reliable. Patterned photoresist layer 62 is
then removed, followed by an etch of the portions of seed layer 61 which
were protected by photoresist layer 62 and thus not covered by conductive
material 63. When seed layer 61 is of TiW, it may be removed where not
covered by the electroplated material 63 forming inductor coils 76 by, for
example, etching in 5% NH.sub.4 HSO.sub.4, followed by etching in mixture
of H.sub.2 O.sub.2, H.sub.2 SO.sub.4 and DI water. This process forms
coils 76 as an inductor, without conductive material remaining between the
inductor coil traces. Conductive material 63 may, depending on the etchant
used to remove exposed portions of seed layer 61, be slightly etched by an
inconsequential amount. Seed layer 61 may also, alternatively, be removed
by dry etching processes such as plasma etch, sputter etch, or ion
milling.
In an alternative embodiment, patterned conductive layer 63 is formed in
any other convenient manner, for example by utilizing standard
metalization and patterning techniques. This is shown, for example, in the
cross-sectional views of FIGS. 7-1 and 7-2. Referring to FIG. 7-1,
following the exemplary process steps depicted in FIGS. 6a-6c, a
metalization layer 51, (as shown in FIG. 7-1) is formed, for example by
sputtering or vacuum depositing aluminum, gold, silver, or other suitable
conductive material. Then, as shown in the cross-sectional view of FIG.
7-2, a layer of photoresist 52 is formed and patterned to protect those
portions of metalization layer 51 which are to remain in order to form
inductor coils 76 (FIG. 6f) and any desired interconnection pattern to be
formed from metalization layer 51. Undesired portions of metalization 51
which are thus exposed by patterned photoresist layer 52 are then removed,
for example by conventional etching techniques such as wet or plasma
etching, or ion milling. This results in a structure as shown in FIG. 6e,
including a patterned metalization layer 63.
With the structure of FIG. 6e attained in any convenient manner, including
the alternative embodiments described above, the surface of the device,
including one or more inductor coils 76, are passivation protected by
applying a suitable passivation layer 77 (FIG. 6f), followed by a pad mask
step to remove portions of the passivation layer covering areas such as
bonding pads to which external connection is to be made. In one
embodiment, photoresist itself (typical thickness about 1-5 microns) is
used as passivation layer 77, for example by using a standard
photolithographic process followed by photoresist bake at approximately
200.degree.-300.degree. C. The photolithography process leaves photoresist
as a passivation layer in the desired areas while removing it from areas
such as bonding pads. Alternatively, an electron beam is used to
polymerize photoresist to form a suitable and durable passivation layer.
FIGS. 8a-8g illustrate an inductor fabricated in accordance with an
alternative embodiment of this invention. This embodiment provides
inductors suitable for high frequency (approximately 100 MHz to 50 Ghz).
In this embodiment coils are placed on studs, lowering the parasitic
capacitances.
Referring to FIG. 8a, substrate 81 is a suitable substrate, for example
heavily doped N type silicon. However, other substrates such as ceramic,
glass, quartz, ferromagnetic materials, Al.sub.2 O.sub.3 /TiC are also
appropriate, as is semiconductor materials of any doping type or dose.
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