A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry. The least significant bit positions of the header and the padding bits are shifted out of the data register prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry such that the least significant bit of the data register is a 1, if no single error occurred, and is a 0 if a single error occurred.
The present invention provides an access control device and a testing method that can simplify the software operations in an access control operation such as a JTAG control operation, and enable the hardware to perform a high-speed control operation. The access control device conducts a test or diagnosis on an object by accessing a serial interface based on a command and data that specify a testing or diagnosing route. Under the control of a processor, a control circuit in the access control device executes an access sequence in accordance with a command string and an input data string stored in a memory, and stores the data outputted from the object to be tested or diagnosed in the memory as an output data string. The control circuit sets a state transition route for each objective state in advance, so that a transition route can be readily determined for an objective state specified by the command string.
Integrated circuit component with terminals for connection to an external communication channel or bus, serial test interface and a configuration register whose content defines operational modes of the integrated circuit, in which the configuration register is loaded with a default configuration, applied externally, through the serial test interface in the course of an initializing phase in which a reset signal applied to the integrated circuit is asserted and in which the default configuration is modifiable via SW or FW, through the external communication channel when the reset signal is deasserted.
A processing system having a testing mechanism that can read out data from a memory such as a ROM without increasing the number of logic circuits to simplify the circuit construction by utilizing the testing mechanism. The processing system includes an address register in the testing mechanism of a chip part connected to the memory in parallel with the other registers, a selector for selecting and sending out either test data from the testing mechanisms or read-out data from the memory. A control unit is further provided so as to set a leading address of the data to be read out from the memory to the address register by the shift operation, to switch the selector to send out the read-out data from the memory, and then, to count up the address of the address register in accordance with a data number to read out, and to read out the data from the memory. This processing system can be applied to a system having the testing mechanism of a JTAG circuit and the like.
A processor-based device incorporating an on-chip instruction trace cache capable of providing information for reconstructing instruction execution flow. The trace information can be captured without halting normal processor operation. Both serial and parallel communication channels are provided for communicating the trace information to external devices. In the disclosed embodiment of the invention, instructions that disrupt the instruction flow are reported, particularly instructions in which the target address is in some way data dependent. For example, call instructions or unconditional branch instructions in which the target address is provided from a data register (or other memory location such as a stack) cause a trace cache entry to be generated. In the case of many unconditional branches or sequential instructions, no entry is placed into the trace cache because the target address can be completely determined from the instruction stream. Other information provided by the instruction trace cache includes: the target address of a trap or interrupt handler, the target address of a return instruction, addresses from procedure returns, task identifiers, and trace capture stop/start information. The disclosed on-chip instruction trace cache allows less expensive external capture hardware to be utilized and also alleviates various of the bandwidth and clock synchronization issues confronting many existing solutions.
