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Compact adapter package providing peripheral to area translation for an integrated circuit chip    
United States Patent5379191   
Link to this pagehttp://www.wikipatents.com/5379191.html
Inventor(s)Carey; David H. (Austin, TX); Whalen; Barry H. (Austin, TX)
AbstractAn peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.
   














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Patent Text Patent PDF Print Page Summary File History
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Drawing from US Patent 5379191
Compact adapter package providing peripheral to area translation for an

     integrated circuit chip - US Patent 5379191 Drawing
Compact adapter package providing peripheral to area translation for an integrated circuit chip
Inventor     Carey; David H. (Austin, TX); Whalen; Barry H. (Austin, TX)
Owner/Assignee     Microelectronics and Computer Technology Corporation (Austin, TX)
Patent assignment
All assignments
Publication Date     January 3, 1995
Application Number     08/257,235
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     June 9, 1994
US Classification     361/777 257/778 257/E23.065 257/E23.067 257/E23.092 257/E23.124 257/E23.194 361/749 361/760 361/807 439/68 439/69
Int'l Classification     H05K 007/02 H01R 009/09
Examiner     Picard; Leo P.
Assistant Examiner     Sparks; Donald A.
Attorney/Law Firm     Sigmond; David M.
Address
Parent Case     CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of U.S. Ser. No. 08/176,924 filed Jan. 3, 1994 now abandoned, which is a continuation of U.S. Ser. No. 08/017,580 filed Feb. 16, 1993, U.S. Pat. No. 5,289,346, which is a continuation of U.S. Ser. No. 07/887,198 filed May 21, 1992 now abandoned, which is a continuation of U.S. Ser. No. 07/661,579 filed Feb. 26, 1991 now abandoned. These applications are incorporated herein by reference.
Priority Data    
USPTO Field of Search     228/180.21 228/180.22 257/700 257/723 257/777 257/778 257/774 257/728 361/760 361/764 361/767 361/768 361/770 361/771 361/777 361/807 361/808 361/809 437/209 439/44 439/65 439/66 439/68 439/69 439/74 439/83
Patent Tags     compact adapter package providing peripheral area translation an integrated circuit chip
   
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 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. A compact adapter package providing peripheral to area translation for an integrated circuit chip, comprising:

a single integrated circuit chip having top and bottom surfaces and having a plurality of conductive terminals disposed on the bottom surface wherein the entire bottom surface of the chip forms a major surface area of the chip and a portion of the major surface area inside the terminals towards the center of the chip forms an inner surface area of the chip;

a dielectric support having upper and lower surfaces wherein the support is positioned entirely within the inner surface area of the chip and the bottom surface of the chip is spaced from and faces the upper surface of the support;

a plurality of electrically conductive pads extending laterally from the upper surface of the support wherein the pads are aligned with and bonded in one-to-one relationship to the terminals thereby attaching the chip to the support wherein the pads, terminals and bonds are positioned entirely within the major surface area of the chip outside the inner surface area of the chip;

a plurality of flat electrically conductive horizontal reroute lines on the upper surface of the support wherein each reroute line includes a first end at one of said pads and a second end within the inner surface area of the chip wherein the reroute lines are positioned entirely within the major surface area of the chip and disposed entirely above and parallel to the upper surface of the support;

a plurality of electrically conductive vertical vias extending through the support between the upper and lower surfaces of the support wherein each via is positioned entirely within the inner surface area of the chip and positioned directly beneath and electrically connected to the second end of one of said reroute lines; and

a plurality of coupling elements in an array pattern on the bottom surface of the support wherein each coupling element is positioned entirely within the inner surface area of the chip and includes a portion directly beneath and electrically connected to one of said vias such that each terminal is electrically connected to one of said coupling elements;

wherein each terminal is electrically connected to a single pad, reroute line, via and coupling element, the reroute lines provide all horizontal translation between the terminals and the coupling elements, and the vias provide all vertical translation between the terminals and the coupling elements.

2. The adapter package of claim 1 wherein the bonds between the terminals and the pads constitute the sole means for attaching the chip to the support.

3. The adapter package of claim 1 wherein the support is a flexible tape-automated-bonding frame.

4. A compact adapter package providing peripheral to area translation for an integrated circuit chip, comprising:

a single integrated circuit chip having top and bottom surfaces and having a plurality of conductive terminals disposed on the bottom surface wherein the entire bottom surface of the chip forms a major surface area of the chip and a portion of the major surface area inside the terminals towards the center of the chip forms an inner surface area of the chip;

a dielectric support having upper and lower surfaces wherein the support is positioned entirely within the inner surface area of the chip and the bottom surface of the chip is spaced from and faces the upper surface of the support;

a compressible supportive insulator between the bottom surface of the chip and the upper surface of the support wherein the compressible supportive insulator is positioned entirely within the inner surface area of the chip and outer sidewalls of the compressible supportive insulator are aligned with outer sidewalls of the support;

a plurality of electrically conductive pads extending laterally from the upper surface of the support wherein the pads are aligned with and bonded in one-to-one relationship to the terminals thereby attaching the chip to the support wherein the pads, terminals and bonds are positioned entirely within the major surface area of the chip outside the inner surface area of the chip;

a plurality of flat electrically conductive horizontal reroute lines on the upper surface of the support wherein each reroute line includes a first end at one of said pads and a second end within the inner surface area of the chip wherein the reroute lines are positioned entirely within the major surface area of the chip and disposed entirely above and parallel to the upper surface of the support;

a plurality of electrically conductive vertical vias extending through the support between the upper and lower surfaces of the support wherein each via is positioned entirely within the inner surface area of the chip and positioned directly beneath and electrically connected to the second end of one of said reroute lines; and

a plurality of coupling elements in an array pattern on the bottom surface the support wherein each coupling element is positioned entirely within the inner surface area of the chip and includes a portion directly beneath and electrically connected to one of said vias such that each terminal is electrically connected to one of said coupling elements;

wherein each terminal is electrically connected to a single pad, reroute line, via and coupling element, the reroute lines provide all horizontal translation between the terminals and the coupling elements, and the vias provide all vertical translation between the terminals and the coupling elements.

5. The adapter package of claim 4 wherein the compressible supportive insulator contacts the bottom surface of the chip, the upper surface of the support and the reroute lines.

6. The adapter package of claim 4 wherein the compressible supportive insulator is selected from the group consisting of silicone, rubber and elastomeric polymer foam.

7. The adapter package of claim 4 wherein the bonds between the terminals and the pads constitute the sole means for attaching the chip to the support.

8. The adapter package of claim 4 wherein the support is a flexible tape-automated-bonding frame.
 Description Submit all comments and votes
 


BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a carrier adapter use between an integrated circuit chip with peripheral terminals and an underlying substrate with area-patterned bond sites, and more particularly to an adapter with mating pads on the top surface of the adapter that can be aligned with, connected directly with and bonded to peripheral terminals on a chip, reroute lines on the top surface of the adapter with first ends connected to the pads, and vertical through-vias connected to the second ends of the reroute lines that terminate at coupling elements in an array pattern on the bottom of the adapter.

2. Description of the Related Art

Current multi-chip circuitry design requires attachment of numerous electronic devices to an electrical interconnect substrate. Terminals on the electrical devices can be connected to pads on the surface of the substrates. The substrate can further include buried metal lines which interconnect selected pads, thereby providing electrical interconnection for the electronic devices.

Typically the conductive terminals on a high density integrated circuit chip are distributed over a very small area along the periphery of the top surface of the chip Flip-chip bonding involves inverting the chip, aligning the terminals on the chip with pads on the substrate, contacting the terminals to the pads and then bonding the terminals to the pads.

There also exist adapters which can be sandwiched between an inverted integrated circuit and an underlying interconnect substrate. In particular, existing adapters can translate the conductive terminals on a chip to an array pattern of coupling elements, to be bonded to the substrate, which can be positioned inside the area of the chip and have substantially larger bonding faces than the terminals. The array pattern of coupling elements can also have generic configurations and dimensions suitable for a wide variety of substrates.

Kyocera has developed an adapter which uses the internal layers of a multilayer ceramic carrier to accomplish the translation, but must modify the ceramic fabrication process in order to customize the adapter for a terminal configuration. An adapter by Fujitsu connects the inner ends of bent leads to the terminals on the bottom of a chip, and the outer ends of the bent leads to the pads on an adapter, but requires two bonding steps for each terminal.

Accordingly, there exists a need for an improved adapter capable of providing peripheral to area translation for the terminals on an integrated circuit chip.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an adapter for integrated circuit chips that contains pads on the top surface customized to directly contact the conductive peripheral terminals on a specific integrated circuit chip, planar reroute lines on the top surface that are customized to translate the terminals into a standardized array pattern, and vias through a dielectric support that connects the reroute lines to coupling elements on the bottom of the adapter. All of the peripheral to area translation for the terminals is performed by the reroute lines.

Another object of the present invention is to improve the assembly and testability of an integrated circuit-interconnect substrate structure without a substantial real estate penalty.

A further object of the present invention is to provide an improved technique for single chip mounting to multi chip modules and printed wiring boards.

Still a further object of the present invention is to translate a perimeter format on a chip into a compact area array no larger than the area of the chip.

A feature of the present invention is to provide a peripheral to area adapter of the type adapted to receive an integrated circuit, the integrated circuit including a top surface, a bottom surface, and a plurality of conductive terminals positioned along the periphery of the bottom surface, including a dielectric support having an upper surface and a lower surface; a plurality of electrically conductive pads above the upper surface of the support and arranged in a pattern corresponding to the terminals on the integrated circuit, so that the bottom surface of the integrated circuit can be positioned above the upper surface of the support to align, directly contact and bond the terminals to the pads; a plurality of electrically conductive planar reroute lines above the upper surface of the support, each of the reroute lines having a first end at a pad and a second end; a plurality of electrically conductive vertical vias extendi