Overconstraints in a system, such as an electrical circuit layout, are identified using port abstraction graphs. Intercell pitchmatching constraints are represented by meta-edges between cells. Classes of edges which can be represented by a support edge are created, and the value of the class edges are increased to the value of the support edge. The edge values are updated in the graphs, and the redundant edges eliminated. Overconstraints are identified as positive cycles in the graphs, and a database of the layout is annotated and graphically displayed. The graphical display responds to user inputs to manipulate the display of the relations between constraints. The use of the port abstraction graphs also reduces the number of equations that need to be solved to compact the layout.

Overconstraints in a system, such as an electrical circuit layout, are identified using port abstraction graphs. Intercell pitchmatching constraints are represented by meta-edges between cells. Classes of edges which can be represented by a support edge are created, and the value of the class edges are increased to the value of the support edge. The edge values are updated in the graphs, and the redundant edges eliminated. Overconstraints are identified as positive cycles in the graphs, and a database of the layout is annotated and graphically displayed. The graphical display responds to user inputs to manipulate the display of the relations between constraints. The use of the port abstraction graphs also reduces the number of equations that need to be solved to compact the layout.

A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

In graphic data representing a symbolic layout for a semiconductor integrated circuit, a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles are set. First, the graphic data is cut along said first cutting lines to produce a plurality of first segment data items. These first segment data items are each compacted in the direction of the second cutting line. These compacted first segment data items are connected according to the first cutting lines. This connected first segment data is cut along the second cutting lines to produce a plurality of second segment data items. These second segment data items are each compacted in the direction of the first cutting line. These compacted second segment data items are connected to one another to produce a compacted mask layout.

A layout amendment specification section includes an input means such as a mouse and gives instructions to an section for compacting within allowable spacing, a wiring compaction section, a rewiring section, and an allowable spacing calculation section. The layout amendment specification section produces vertical ranking data for elements of terminals, via-holes, and wiring divided by each bent point of the wiring route. The allowable spacing calculation section produces vertical and horizontal sequence data that places all elements in order vertically and horizontally, and moreover, calculates the allowable spacing between terminals and via-holes. Based on the allowable spacing data, section for compacting within allowable spacing shifts the terminals and via-holes by pushing them down, and in addition, shifting the terminals and via-holes while maintaining a spacing of a gap compensation amount wherever possible that can accommodate one wire between a terminal or via-hole and an adjacent element.