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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more
particularly, to a circuit for performing a voltage stress test with
respect to a DRAM (dynamic random-access memory).
2. Description of the Related Art
In a DRAM, the highest electric field (voltage stress) is applied to the
gate insulating film of the transfer gate transistor (cell transistor) of
each memory cell having a gate electrode to which a word line is
connected. Consequently, there is a high probability that a reliability
problem may occur at the gate insulating film. In addition, the refresh
cycle is doubled every time devices of a new generation are developed. For
this reason, in repeating a normal cycle, the duty ratio at which a high
electric field is applied to the word lines is reduced to half for each
coming generation.
In a conventional burn-in test of a DRAM, an electric field applied to the
gate insulating film of each cell transistor is accelerated by boosting a
supply voltage. Since the word lines are sequentially selected, it takes
too much time to perform screening of the gate insulating film of each
cell transistor. If, therefore, the total time required to screen the gate
insulating film of each cell transistor is kept constant even with a
change in generation of DRAMs, the burn-in test time is doubled for each
coming generation.
Under the circumstances, there is an increasing demand to shorten the
burn-in test time of a DRAM. As a measure to meet this demand, it is
proposed that a DRAM incorporate a mode in which a larger number of word
lines are simultaneously selected than in a normal operation, and a DC
voltage is applied to the selected word lines. This mode will be referred
to as a quick DC burn-in test mode in order to discriminate it from the
conventional normal burn-in test mode. According to a means for realizing
this quick DC burn-in test mode, special voltage stress test pads which
are not used in a normal operation are additionally arranged on a chip,
and a stress voltage is applied to the pads in a burn-in test, thereby
simultaneously selecting word lines larger in number than those selected
in a normal operation. In this state, a burn-in test is performed.
However, in the burn-in test mode using the above-mentioned special voltage
stress test pads, a voltage stress test cannot be performed with respect
to a DRAM sealed in a package. In consideration of such a situation, for
example, Japanese Patent Application No. 4-225182 discloses a means for
realizing a quick DC burn-in test mode. According to this means, by
inputting an external control signal, signals on the input or outside side
of a word line selection circuit are forcibly controlled to a constant
level to simultaneously select all the word lines, thus performing a
burn-in test in this state. With this operation, no special voltage stress
test pads are required, and the DC burn-in test mode can be set in a wafer
state or a packaged state. In a circuit arrangement for setting the quick
DC burn-in test mode by externally inputting a control signal, as
described above, the number of circuits other than those required for the
normal operation mode is preferably minimized to suppress an increase in
chip area. In addition, in setting the quick DC burn-in test mode, not
only a row decoder but also other circuits must or preferably be
controlled simultaneously. There are demands for practical measures to
meet these requirements.
On the other hand, a decrease in breakdown voltage between adjacent word
lines due to dust must be screened in advance. For example, Japanese
Patent Application No. 2-418374 discloses a mode in which the word lines
of a word line array are divided into two groups, i.e., an even-numbered
word line group and an odd-numbered word line group, and high voltages are
simultaneously applied to the two groups, thereby performing a burn-in
test by applying a sufficient voltage between adjacent word lines. This
mode will be referred to as a quick AC burn-in test mode hereinafter.
FIGS. 1 to 3 show circuits for realizing the quick AC burn-in test mode
disclosed in Japanese Patent Application No. 2-418374. The circuit shown
in FIG. 1 is used in a DRAM of a bootstrap word line driving scheme, in
which a control clock signal .phi..sub.BOOT is caused to rise in the
burn-in test mode to transfer charges, prestored in a bootstrap capacitor
C.sub.BOOT, to selected word lines WLOi to WLi through n-channel MOS
transistors 140 to 142. In the AC burn-in test mode, some of bits A0 to An
of an address signal are set at "L" level in both "true and complementary"
signals so as to simultaneously select a plurality of NOR type decoders
144 or 145, thereby simultaneously applying a voltage stress to word lines
which are not adjacent to each other. In this case, the potential of a bit
line BL is fixed at the ground potential through a transfer gate 146 and a
pad 147 controlled by a bit line precharging signal .phi..sub.PRE. In each
of the circuits shown in FIGS. 2 and 3, special voltage stress test pads
148 to 150 are arranged, and a transfer gate 151 or 152 is connected to
one end of each of all word lines WL0i, WL1i, . . . The transfer gates 151
and 152 are selectively driven to select the even-numbered or odd-numbered
word line group of the word line array, thereby simultaneously applying a
voltage stress to the selected word line group (every other word line in
the word line array) through the pad connected to the other end of each of
the selected word lines. However, in the burn-in test mode using the
special voltage stress test pads, shown in FIGS. 1 to 3, a voltage stress
test cannot be performed with respect to a DRAM sealed in a package. In
the circuits shown in FIGS. 1 to 3, in realizing the quick AC burn-in test
mode, since a normal operation (DRAM operation) cannot be performed,
failure modes which can occur in a normal operation but are difficult to
predict, such as a decrease in breakdown voltage between adjacent bit
lines, cannot be screened in advance.
In order to set the quick DC burn-in test mode in wafer state or a packaged
state of a DRAM without requiring special voltage stress test pads, as
disclosed in Japanese Patent Application No. 2-418371, a burn-in test must
be performed while signals on the input or output side of a word line
selecting circuit are forcibly controlled to a constant level by
externally inputting a control signal, and a larger number of word lines
are simultaneously selected than in a normal operation. As described
above, in a circuit arrangement for setting the quick burn-in test mode by
externally inputting a control signal, the number of circuits other than
those required for the normal operation mode is preferably minimized to
reduce an increase in chip area. In addition, in setting the quick burn-in
test mode, not only a row decoder but also other circuits must or
preferably be controlled simultaneously. Demands have arisen for practical
measures to meet these requirements.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above
situation, and has as its object to provide a semiconductor memory device
in which the AC voltage stress test mode, in which the duty ratio at which
a high voltage is applied to word lines in a wafer state or a packaged
state is high, can be set, without using special voltage stress test pads,
to minimize the number of circuits other than those required for a normal
operation so as to reduce an increase in chip area, and failure modes
which can occur in a normal operation but are difficult to predict, such
as a decrease in breakdown voltage between adjacent word lines or adjacent
bit lines, can be simultaneously screened by operating the device in
substantially the same manner as in a normal operation.
It is another object of the present invention to provide a semiconductor
memory device in which the DC voltage stress test mode can be set, without
using special voltage stress test pads, to minimize the number of circuits
other than those required for a normal operation so as to reduce an
increase in chip area.
According to an aspect of the present invention, a semiconductor memory
device comprises a DRAM circuit, a voltage stress test mode signal
generating circuit for generating a voltage stress test mode signal on the
basis of a predetermined signal input through some of external terminals
used in a normal operation of the DRAM circuit, and a control circuit for
receiving the test mode signal from the voltage stress test mode signal
generating circuit, and performing control such that a plurality of bits
of an output signal from a refresh address counter of the DRAM circuit are
fixed at the same level, and bits other than the plurality of bits are
subjected to a normal count operation.
According to another aspect of the present invention, a semiconductor
memory device comprises a DRAM circuit, a voltage stress test mode signal
generating circuit for generating a voltage stress test mode signal on the
basis of a predetermined signal input through some of external terminals
used in a normal operation of the DRAM circuit, and a control circuit for
receiving the test mode signal from the voltage stress test mode signal
generating circuit, and performing control such that upper bits, of an
output signal from a refresh address counter of the DRAM circuit, which
are more significant than a specific bit are fixed at the same level, and
lower bits which are less significant than the specific bit are subjected
to a normal count operation.
According to still another aspect of the present invention, a semiconductor
memory device comprises a DRAM circuit, a voltage stress test mode signal
generating circuit for generating a voltage stress test mode signal on the
basis of a predetermined signal input through some of external terminals
used in a normal operation of the DRAM circuit, and a control circuit for
receiving the test mode signal from the voltage stress test mode signal
generating circuit, and performing control such that all bits of an output
signal from a refresh address counter of the DRAM circuit are fixed at the
same level so as to cause a word line driving circuit of the DRAM circuit
to simultaneously drive all word lines.
A voltage stress test mode signal is generated on the basis of a
predetermined signal input through some of external terminals used in a
normal operation of the DRAM circuit. Upon reception of this signal, only
the upper bits of an output signal from the refresh address counter are
fixed at the same level. In this case, since the lower bits of the output
signal from the refresh address counter change in accordance with a
counter operation, the AC voltage stress test mode can be set, in which
the duty ratio at which a high voltage is applied to the word lines of the
DRAM circuit is higher than that in a normal operation. Therefore, a
decrease in breakdown voltage at the insulating film of the transfer gate
of each memory cell can be screened in a short period of time. In
addition, a voltage stress test mode signal is generated on the basis of a
predetermined signal input through some of external terminals used in a
normal operation of the DRAM circuit. Upon reception of this signal, all
the bits of each of complementary output signals from the refresh address
counter are fixed at the same level. With this operation, a desired
voltage test mode (e.g., the quick DC burn-in test mode) can be set. As
described above, no special pads are required to set a voltage stress test
mode, and a voltage stress test mode can be set in a wafer state or a
packaged state of a DRAM. In addition, the number of circuits other than
those required for a normal operation can be minimized to reduce an
increase in chip area. Furthermore, by performing substantially the same
operation as a normal DRAM operation, failure modes which can occur in a
normal operation but are difficult to predict, such as a decrease in
breakdown voltage between adjacent word lines or adjacent bit lines, can
be simultaneously screened. In this case, "substantially the same
operation" means that the screening time is shortened by simultaneously
selecting word lines in memory cell blocks which are considered to be
independent with respect to a breakdown voltage reduction failure mode
because the word lines of the respective blocks are sufficiently spaced
apart from each other.
Additional objects and advantages of the invention will be set forth in the
description which follows, and in part will be obvious from the
description, or may be learned by practice of the invention. The objects
and advantages of the invention may be realized and obtained by means of
the instrumentalities and combinations particularly pointed out in the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part
of the specification, illustrate presently preferred embodiments of the
invention, and together with the general description given above and the
detailed description of the preferred embodiments given below, serve to
explain the principles of the invention.
FIG. 1 is a circuit diagram showing a circuit for realizing the quick AC
burn-in test mode of a conventional DRAM;
FIG. 2 is a circuit diagram showing another circuit for realizing the quick
AC burn-in test mode of a conventional DRAM;
FIG. 3 is a circuit diagram showing still another circuit for realizing the
quick AC burn-in test mode of a conventional DRAM;
FIG. 4 is a block diagram showing part of a DRAM incorporating an AC/DC
burn-in test mode according to the first embodiment of the present
invention;
FIG. 5 is a circuit diagram showing part of a row address buffer circuit in
FIG. 4;
FIG. 6 is a circuit diagram showing a one-stage portion of a refresh
address counter and part of an AC burn-in test mode control circuit in
FIG. 4;
FIG. 7 is a circuit diagram showing the one-stage portion of the refresh
address counter and part of a DC burn-in test mode control circuit in FIG.
4;
FIG. 8 is a circuit diagram showing part of an address switching circuit in
FIG. 4;
FIG. 9 is a timing chart showing operations of the circuits in FIGS. 5 to 8
in the normal operation mode;
FIG. 10 is a timing chart showing operations of the circuits in FIGS. 5 to
8 in the refresh operation mode;
FIG. 11 is a timing chart showing operations of the circuits in FIGS. 5, 6,
and 8 in the quick AC burn-in test mode;
FIG. 12 is a timing chart showing operations of the circuits in FIGS. 5, 7,
and 8 in the quick DC burn-in test mode;
FIGS. 13A and 13B are a circuit diagram of an AC burn-in test mode signal
generating circuit and a timing chart thereof in FIG. 4, respectively;
FIGS. 14A and 14B are a circuit diagram of a DC burn-in test mode signal
generating circuit and a timing chart thereof in FIG. 4, respectively;
FIG. 15 is a circuit diagram showing part of a row decoder circuit and a
word line driving circuit in FIG. 4;
FIG. 16 is a timing chart showing an operation of the circuit in FIG. 15;
FIG. 17 is a circuit diagram showing a spare row decoder/word line driving
circuit in FIG. 4;
FIG. 18 is a circuit diagram showing a one-column portion of a memory cell
array and part of a memory cell peripheral circuit in FIG. 4;
FIG. 19 is a circuit diagram showing a one-column portion of a memory cell
array and part of a memory cell peripheral circuit in FIG. 4;
FIG. 20 is a circuit diagram showing a signal generating circuit for
generating signals .phi.T and EQL in FIG. 18;
FIG. 21 is a circuit diagram showing a signal generating circuit for
generating signals .phi.T and EQL in FIG. 19;
FIG. 22 is a circuit diagram showing a VBL generating circuit in FIG. 4;
FIG. 23 is a circuit diagram showing a word line driving voltage source and
a VPP-VCC short circuit in FIG. 4;
FIG. 24 is a circuit diagram showing a supply voltage decreasing circuit
and a VCC-VDD short circuit arranged in a DRAM according to the second
embodiment of the present invention;
FIG. 25 is a timing chart showing a cycle for setting the quick AC burn-in
test mode, an AC stress test cycle, and a test terminating cycle with
respect to the DRAM of the present invention;
FIG. 26 is a timing chart showing a cycle for setting the quick DC burn-in
test mode, a DC stress test cycle, and a test terminating cycle with
respect to the DRAM of the present invention; and
FIG. 27 is a circuit diagram showing part of another row address buffer
circuit in FIG. 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The embodiments of the present invention will be described below with
reference to the accompanying drawings.
FIG. 4 shows part of a DRAM incorporating a quick AC/DC burn-in test mode
according to the first embodiment of the present invention.
The DRAM shown in FIG. 4 will be briefly described first. In addition to a
normal access mode, a normal burn-in mode, and a standardized multiple-bit
parallel test mode, a DRAM circuit 10 has a quick AC/DC burn-in test mode
in which AC/DC voltage stresses are simultaneously applied to word lines
larger in number than those selected in a normal operation. The DRAM
circuit 10 comprises: a memory cell array 1 having a plurality of dynamic
memory cells arranged in the form of a matrix; word lines WL, each
connected to memory cells in the same row; bit lines BL, each connected to
memory cells in the same column; external terminals 2 (power supply
terminal 2a to which a supply voltage is externally input, and input
terminals 2b for receiving an address signal and various control signals
(e.g., a write enable signal WE, a row address strobe signal RAS, and a
column address strobe signal CAS)); an address buffer circuit 3 for
amplifying an external address signal input through some of the external
terminals 2; a refresh address counter 4 for generating a refresh address
signal for refreshing the memory cells; an address switching circuit 5 for
selecting either an output signal from the refresh address counter 4 or a
row address signal output from the address buffer circuit 3; a row decoder
circuit (word line selecting circuit) 6 having a word line selecting
function for selecting an arbitrary row in accordance with an internal row
address signal output from the address switching circuit 5; a word line
driving voltage source 7; a word line driving circuit 8 having at least
one word line driving MOS transistor (a PMOS transistor in this
embodiment) connected between the word line driving voltage source 7 and
the word lines WL and designed to drive the word lines WL in accordance
with an output signal from the row decoder circuit 6; a bit line transfer
gate TG which is connected between the input nodes of a sense amplifier SA
and the bit lines BL and is ON/OFF-controlled by a control signal .phi.T;
the sense amplifier SA for detecting information read out from the memory
cells to the bit lines BL; a column decoder circuit 9; a column selecting
circuit CS; a bit line precharging/equalizing circuit 11 which is
connected to the bit lines BL and is ON/OFF-controlled by a bit line
equalizing signal EQL; and a bit line precharging potential (VBL)
generating circuit 12 for applying a potential VBL to the bit line
precharging/equalizing circuit 11. In addition, the DRAM circuit 10
includes a fail-safe redundant arrangement (spare memory cells, spare word
lines SWL, a spare row decoder, a word line driving circuit 13, and the
like). The word line driving voltage source 7 is a booster circuit for
generating a word line driving voltage VPP by boosting a supply voltage
VCC, applied from the outside of the semiconductor chip, on the chip, and
applying the word line driving voltage VPP as power to the word line
driving circuit 8. In this case, although a charge pump type booster
circuit may be used as the word line driving voltage source 7, a booster
circuit having a large current driving capacity (constituted by, e.g., a
ring oscillation circuit and a rectifying circuit) is preferably used. The
DRAM circuit 10 may have a switching circuit (not shown) for selecting an
output from the above-mentioned booster circuit in a normal operation, and
selecting an externally applied word line driving voltage and applying the
selected voltage as a word line driving voltage in a voltage stress test.
However, this embodiment includes a VPP-VCC short circuit 14 for
connecting the output node of the word line driving voltage source 7 to
the power supply terminal 2a by short-circuiting so as to externally apply
a word line driving voltage in a voltage stress test.
A burn-in test mode signal generating circuit 20 generates a burn-in test
mode signal BITAC/BITDC on the basis of a predetermined signal input
through some of the external terminals 2 used in a normal operation of the
DRAM circuit 10. In the embodiment, the burn-in test mode signal
BITAC/BITDC is set at high ("H") level in an active state, and is set at
low ("L") level in an inactive state. For example, in a WCBR cycle to be
described later (the WE and CAS signal inputs are activated before the RAS
signal input), the burn-in test mode signal generating circuit 20 loads a
row address signal input at the time when the RAS signal is activated. If
the row address signal input coincides with a predetermined address
combination, the burn-in test mode signal generating circuit 20 sets the
signal BITAC/BITDC at "H" level. As described above, when the burn-in test
mode is set in accordance with a WCBR cycle, upper-level compatibility
with respect to the multiple-bit parallel test mode as one of the existing
function test modes can be ensured as follows. When a WCBR cycle is
performed upon setting a normal supply voltage (e.g., 3 V) for a normal
operation, the conventional multiple-bit parallel test mode is set. When a
WCBR cycle is performed upon setting a high supply voltage (e.g., 6 V)
falling outside a normal operation range, the signal BITAC/BITDC is set at
"H" level. Assume that there are a plurality of types of burn-in test
modes. In this case, the following mode setting scheme may be employed.
when the RAS signal input is activated in a WCBR cycle upon setting a high
supply voltage falling outside a normal operation range, some bits of the
address signal constitute a predetermined combination (in the embodiment,
both bits A0R and A1R are set "L" level), thereby setting the quick AC/DC
burn-in test mode. Note that if the DRAM circuit 10 incorporates only the
quick AC/DC burn-in test mode, the above-described complicated mode
setting scheme need not be employed. For example, the quick AC/DC burn-in
test mode may be set when only a WCBR cycle is performed. Alternatively, a
specific external terminal is set at a voltage other than a normal applied
voltage (e.g., a voltage higher than a normal supply voltage: a super
voltage), and the AC/DC burn-in test mode is set by detecting this
voltage.
A burn-in test mode control circuit 21 receives a burn-in test mode signal
BITAC from the burn-in test mode signal generating circuit 20, and fixes
only the upper bits of each of complementary output signals from the
refresh address counter 4 of the DRAM circuit 10 at the same level,
thereby setting an AC stress test mode (e.g., a quick AC burn-in test
mode) in which the duty ratio at which a high voltage is applied to the
word lines WL of the DRAM circuit 10 is higher than that in a normal
operation. In addition, the burn-in test mode control circuit 21 receives
a burn-in test mode signal BITDC from the burn-in test mode signal
generating circuit 20, and fixes all the bits of an output signal from the
refresh address counter 4 of the DRAM circuit 10 at the same level,
thereby controlling the word line driving circuit 8 of the DRAM circuit 10
to simultaneously drive all the word lines (setting a quick DC burn-in
test mode). The burn-in test mode control circuit 21 is preferably
designed to control other circuits in proper circuit states in accordance
with the AC burn-in test mode, in addition to receiving the burn-in test
mode signal BITAC from the burn-in test mode signal generating circuit 20
to fix only the upper bits of each of complementary output signals from
the refresh address counter 4 of the DRAM circuit 10 at the same level.
More specifically, the burn-in test mode control circuit 21 preferably
performs control to selectively drive the spare word lines SWL at the same
duty ratio as that for the normal word lines WL, and limits the capacity
of a driving transistor for the sense amplifier SA to forcibly control the
control signal .phi.T at an active level (i.e., controlling the bit line
transfer gate TG in an ON state in a voltage stress test). In addition,
the burn-in test mode control circuit 21 is preferably designed to control
other circuits in proper circuit states in accordance with the DC burn-in
test mode, in addition to receiving the burn-in test mode BITDC from the
burn-in test mode signal generating circuit 20 to fix all the bits of each
of complementary output signals from the refresh address counter 4 of the
DRAM circuit 10 at the same level. More specifically, the burn-in test
mode control circuit 21 preferably performs control to selectively drive
the spare word lines SWL, controls the control signal .phi.T and the bit
line equalizing signal EQL at an active level (i.e., controlling the bit
line transfer gate TG and the bit line precharging/equalizing circuit 11
in an ON state in a voltage stress test), controls the bit precharging
voltage VBL at a low level, and performs control to inhibit the operation
of the sense amplifier SA and circuits on its output side (e.g., a buffer
circuit connected to the data lines).
According to the DRAM shown in FIG. 4, when the burn-in test mode signal
BITAC is generated by the burn-in test mode signal generating circuit 20
on the basis of a predetermined signal input through some of the external
terminals 2, of the DRAM circuit 10, used in a normal operation, only the
upper bits of each output signal from the refresh address counter 4 of the
DRAM circuit 10 are fixed at the same level, thereby setting the quick AC
burn-in test mode. In this case, since the lower bits of each output
signal from the refresh address counter 4 change in accordance with a
counter operation, the AC voltage stress test mode can be set, in which
the duty ratio at which a high voltage is applied to the word lines WL of
the DRAM circuit 10 is higher than that in a normal operation, thereby
allowing a quick screening test of a decrease in the breakdown voltage of
the insulating film of the bit line transfer gate TG of each memory cell.
In addition, when the burn-in test mode signal BITDC is generated on the
basis of a predetermined signal input through some of the external
terminals 2, of the DRAM circuit 10, used in a normal operation, all the
bits of each of complementary output signals from the refresh address
counter 4 of the DRAM circuit 10 are fixed at the same level, thereby
setting the quick DC burn-in test mode.
No specific pads, therefore, are required to set the quick AC/DC burn-in
test mode, and the number of circuits other than the circuits required for
the normal operation mode can be minimized, thus reducing an increase in
chip area. In addition, since no specific pads are required to set the
quick AC/DC burn-in test mode, the quick burn-in test mode can be set in a
wafer state or after packaging. For this reason, in a quick AC/DC burn-in
test in a wafer state, test units (e.g., a probe card) used for a normal
function test can be used. In a quick AC/DC burn-in test after packaging,
a general memory tester can be used.
Portions associated with the present invention shown in FIG. 4 will be
described next with reference to FIGS. 5 to 17. Note that the suffix "n"
of each reference numeral in FIGS. 5 to 17 indicates that each portion
denoted by each reference numeral corresponds to one of cell blocks
constituting the memory cell array 1.
FIG. 5 is a circuit diagram showing part of a row address buffer
(corresponding to one bit) of the address buffer circuit 3 in FIG. 4.
Referring to FIG. 5, reference symbol VCC denotes a supply potential; VSS,
a ground potential; P1, a p-channel MOS transistor; N1 to N5, n-channel
MOS transistors; and C1 and C2, MOS capacitors through which the drains
and sources of the n-channel MOS transistors are commonly connected to the
VSS node. Reference numeral 22 denotes a differential latch circuit.
Reference symbol RLTC, a latch control signal; AINj (j=0 to 10), an
externally input address signal; Vref, a reference potential; RACP and
RHLD, gate control signals; and AIjR and AIjR, complementary row address
buffer output signals.
FIGS. 6 and 7 are circuit diagrams respectively showing part (corresponding
to one stage) of the refresh address counter 4 and the burn-in test mode
control circuit 21 in FIG. 4. Referring to FIG. 6, reference numerals 31
to 34 denote clocked inverters; and 35, an inverter. For example,
two-input NOR gates 36 as part of the burn-in test mode control circuit 21
are inserted between the complementary output terminals of the respective
stages of the address counter. A signal BITACj (j=0 to 10) is input to one
input terminal of each of the NOR gates 36. This signal BITACj is set as
follows. Assume that in the DRAM circuit 10 in FIG. 4, the shared sense
amplifier scheme, in which the sense amplifier SA is used according to the
time division scheme between adjacent memory cell blocks, is not employed,
or the transfer gate control signal .phi.T is forcibly set at "H" level in
the AC burn-in test mode, as will be described later. In this case, the
signal BITAC signal is input to one input terminal of each of the NOR
gates 36 inserted between output terminals, of the address counter 4,
which correspond to upper bits, e.g., 9 bits (j=2 to 10 bits). The
potential VSS ("L" level) is input to one input terminal of each of the
NOR gates 36 inserted between output terminals, of the address counter 4,
which correspond to the remaining lower 2 bits (j=0 and 1 bits) (i.e., the
NOR gates 36 serve as inverters). In contrast to this, assume that in the
DRAM circuit 10 in FIG. 4, the shared sense amplifier scheme is employed
to use the 8th bit of the address counter output so as to perform address
selection of cell blocks on both sides of the sense amplifier SA, and that
the transfer gate control signal .phi.T is not forcibly set at "H" level
in the AC burn-in test mode, as will be described later. In this case, the
signal BITAC is input to one input terminal of each of the NOR gates 36
inserted between output terminals, of the address counter 4, which
correspond to upper bits, e.g., upper 8 bits (j=3 to 10 bits). The
potential VSS ("L" level) is input to one input terminal of each of the
NOR gates 36 inserted between output terminals, of the address counter 4,
which correspond to the remaining lower 3 bits (j=0, 1, and 2 bits) (i.e.,
the NOR gates 36 serve as inverters). j=2 corresponds to addresses for
selecting cell blocks on both sides of the shared sense amplifier. Note
that reference symbols CTj and CTj (j=0 to 10) denote complementary output
signals from the address counter 4. Referring to FIG. 7, the signal BITDC
is input to one input terminal of each of the NOR gates 36. Reference
symbols CTj and CTj denote complementary output signals from the address
counter 4.
FIG. 8 is a circuit diagram showing part (corresponding to one bit) of the
address switching circuit 5 in FIG. 4. Referring to FIG. 8, reference
numeral 41 denotes an address switching NMOS transistor; and 42, an
inverter for a latch circuit. Reference symbol RTRS denotes a switching
signal for selecting a row address buffer output; CT, a switching signal
for selecting an address counter output; and AjR and AjR, selection
outputs (internal row address signals ).
The circuits shown in FIGS. 5 to 8 are logically designed to realize
operations such as those indicated by the timing charts shown in FIGS. 9,
10, 11, and 12 in accordance with the normal operation mode, refresh
operation mode, quick AC burn-in test mode, and quick DC burn-in test mode
of the DRAM. The state of the row address buffer circuit 3 is determined
by signals RACP, RHLD, RLTC, RTRS, AIjR, and AIjR.
In the normal operation mode shown in FIG. 9, the signal BITAC/BITDC is at
"L" level, and the DRAM circuit 10 operates in the same manner as the
conventional DRAM. More specifically, in loading a column address signal
by activating the signal CAS signal after loading a row address signal by
activating the signal RAS, the signal CT is kept at "L" level, and the
signal RTRS is kept at "H" level. With this operation, the row address
buffer output signals AIjR and AIjR are selected and loaded as the
internal row address signals AjR and AjR.
FIG. 10 shows an automatic refresh operation based on the execution of a
CBR cycle (i.e., activating the signal CAS earlier than the signal RAS).
In this refresh operation, the signal RTRS is immediately set at "L" level
to inhibit selection of the row address buffer output signals AIjR and
AIjR. At the same time, the signal CT is activated to select the output
signals CTj and CTj stored in the address counter 4 at this time so as to
load them as internal row address signals RABj and RABj, thus refreshing
memory cells selected by the resulting word line selection signal.
In the AC burn-in test mode shown in FIG. 11, the signal BITAC is set at
"H" level, and the upper 9 bits (j=2 to 10) of each of the output signals
CTj and CTj from the refresh address counter 4 are fixed at "L" level. The
lower 2 bits (j=0 and 1) of each of the output signals CTj and CTj from
the address counter 4 change in accordance with a counter operation. When
a CBR cycle is executed at this time, the upper 9 bits (j=2 to 10) of each
of the internal row address signals AjR and AjR are fixed at "H" level,
and the lower 2 bits (j=0 and 1) of each of the internal row address
signals AjR and AjR change in accordance with a counter operation. As a
result, only some output nodes of the word line driving circuit 8 are
selected, and only some of the word lines WL are selected and set at "H"
level. In the DC burn-in test mode shown in FIG. 12, the signal BITDC is
set at "H" level, and all the bits of each of the output signals CTj and
CTj from the refresh address counter 4 are fixed at "L" level. When a CBR
cycle executed at this time, all the bits of each of the internal row
address signals AjR and AjR are fixed at "H" level. That is, all the bits
of the word line selection signal are fixed at the "H" level.
Consequently, all the output nodes of the word line driving circuit 8 are
selected, and all the word lines WL are selected and set at "H" level.
FIGS. 13A and 14A are circuit diagrams exemplifying the burn-in test mode
signal generating circuit 20. Referring to FIG. 13A, reference symbol WCBR
denotes a signal generated when a clock for a WCBR cycle is input; A0R and
A1R, bits of an internal row address signal obtained when the signal input
RAS is activated; and ROR, a signal generated when a clock for an ROR
cycle (an RAS only refresh cycle for temporarily activating only the
signal RAS) is input. Reference numeral 61 denotes a three-input NAND
gate; 62, a flip-flop circuit; and 63, an inverter. In FIG. 14A, the bit
A1R of an internal row address signal is input, instead of the bit A1R in
FIG. 13A, to generate the signal BITDC.
The circuit shown in FIG. 13A is logically designed to realize an operation
such as the one indicated by the timing chart shown in FIG. 13B. More
specifically, if a WCBR cycle is performed when both the bits A0R and A1R
of an address signal are set at "L" level, the signal BITAC is set at "H"
level. When an ROR cycle is executed upon completion of the AC burn-in
test mode, the signal BITAC goes to "L" level. The circuit shown in FIG.
14A is logically designed to realize an operation such as the one
indicated by the timing chart shown in FIG. 14B. More specifically, if a
WCBR cycle is performed when bits A0 and A1 of an address signal are set
at "L" level and "H" level, respectively, the signal BITDC is set at "H"
level. When an ROR cycle is executed upon completion of | | |
