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Claims  |
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What is claimed is:
1. A semiconductor device comprising:
a semiconductor die having a planar surface, a centroid, a peripheral area,
an interior area within the peripheral area, an axis defined on the planar
surface of the semiconductor die which passes substantially over the
centroid, and a width perpendicular to the axis;
circuitry formed within the die;
a first plurality of relatively many bond pads disposed on the planar
surface of the die in a linear configuration along the axis;
a second plurality of relatively few bond pads disposed on the planar
surface of the die, within the interior area and spaced away from the
centerline, the second plurality of bond pads being disposed on either
side of the first plurality of bond pads; and
further comprising:
a first limit line defined on the surface of the die to one side of the
axis, parallel to the axis and located a first distance from the axis
equal to approximately one-quarter of the width of the die;
a second limit line defined on the surface of the die to an opposite side
of the axis, parallel to the axis and located a second distance from the
axis equal to approximately one-quarter of the width of the die; and
a placement area on the surface of the die between the first limit line and
the second limit line;
wherein:
the second plurality of bond pads is disposed entirely within the placement
area.
2. A semiconductor device, according to claim 1, wherein:
the first bond pads are disposed at selected first longitudinal positions
along the axis;
the second bond pads are disposed at selected second longitudinal
positions, offset from the axis; and
at least a portion of the selected second longitudinal positions are
distinct from the selected first longitudinal positions.
3. A semiconductor device, according to claim 1, wherein:
the first bond pads are disposed at selected first longitudinal positions
along the axis;
the second bond pads are disposed at selected second longitudinal
positions, offset from the axis; and
at least a portion of the selected second longitudinal positions are
coincident with a portion of the selected first longitudinal positions.
4. A semiconductor device, according to claim 1, further comprising:
the first plurality of bond pads carry signals to and from circuit elements
formed within the die.
5. A semiconductor device, according to claim 1, wherein:
the second plurality of bond pads carry power to and from circuit elements
formed within the die.
6. A semiconductor device, according to claim 6, wherein:
at least two bond pads in the second plurality of bond pads are disposed in
a collinear arrangement, on opposite sides of the axis, along a line
perpendicular to the axis.
7. A semiconductor device comprising:
a semiconductor die having a planar surface, a centroid, a peripheral area,
an interior area within the peripheral area, an axis defined on the planar
surface of the semiconductor die which passes substantially over the
centroid, and a width perpendicular to the axis;
circuitry formed within the die;
a first plurality of relatively many bond pads disposed on the planar
surface of the die in a linear configuration along the axis; and
a second plurality of relatively few bond pads disposed on the planar
surface of the die, within the interior area and spaced away from the
centerline, the second plurality of bond pads being disposed on either
side of the first plurality of bond pads;
wherein:
at least two bond pads in the second plurality of bond pads are disposed in
a collinear arrangement, on opposite sides of the axis, along a line
perpendicular to the axis; and
further comprising:
a first limit line defined on the surface of the die to one side of the
axis, parallel to the axis and located a first distance from the axis
equal to approximately one-quarter of the width of the die;
a second limit line defined on the surface of the die to an opposite side
of the axis, parallel to the axis and located a second distance from the
axis equal to approximately one-quarter of the width of the die; and
a placement area on the surface of the die between the first limit line and
the second limit line;
wherein:
the second plurality of bond pads is disposed entirely within the placement
area.
8. A semiconductor device, according to claim 1, wherein:
at least two of the bond pads in the second plurality of bond pads are
disposed in a collinear arrangement, on a common side of the axis, along a
line perpendicular to the axis.
9. A semiconductor device comprising:
a semiconductor die having a planar surface, a centroid, a peripheral area,
an interior area within the peripheral area, an axis defined on the planar
surface of the semiconductor die which passes substantially over the
centroid, and a width perpendicular to the axis;
circuitry formed within the die;
a first plurality of relatively many bond pads disposed on the planar
surface of the die in a linear configuration along the axis;
a second plurality of relatively few bond pads disposed on the planar
surface of the die, within the interior area and spaced away from the
centerline, the second plurality of bond pads being disposed on either
side of the first plurality of bond pads; and
wherein:
at least two of the bond pads in the second plurality of bond pads are
disposed in a collinear arrangement, on a common side of the axis, along a
line perpendicular to the axis; and
further comprising:
a first limit line defined on the surface of the die to one side of the
axis, parallel to the axis and located a first distance from the axis
equal to approximately one-quarter of the width of the die;
a second limit line defined on the surface of the die to an opposite side
of the axis, parallel to the axis and located a second distance from the
axis equal to approximately one-quarter of the width of the die; and
a placement area on the surface of the die between the first limit line and
the second limit line;
wherein:
the second plurality of bond pads is disposed entirely within the placement
area.
10. A semiconductor device assembly comprising:
a semiconductor die having a planar surface, four edges, a centroid, a
peripheral area, an interior area within the peripheral area, an axis
defined on the planar surface of the semiconductor die which passes
substantially over the centroid, and a width perpendicular to the axis;
circuitry formed within the die;
a first plurality of bond pads disposed on the planar surface of the die in
a linear configuration along the axis;
a second plurality of bond pads disposed on the planar surface of the die,
within the interior area and spaced away from the centerline; and
a leadframe having a first, a second, a third and a fourth pluralities of
conductive fingers, wherein:
the first plurality of conductive fingers extend from a one edge of the die
to a first portion of the first plurality of bond pads;
the second plurality of conductive fingers extend from an opposite edge of
the die to a first portion of the first plurality of bond pads;
the third plurality of conductive fingers extend from the one edge of the
die to a first portion of the second plurality of bond pads; and
the fourth plurality of conductive fingers extend from the opposite edge of
the die to a first portion of the second plurality of bond pads.
11. A semiconductor device assembly, according to claim 10, wherein:
at least two bond pads in the second plurality of bond pads are disposed in
a collinear arrangement, on opposite sides of the axis, along a line
perpendicular to the axis; and
at least one of the third plurality of conductive fingers is connected to
the at least two collinear bond pads in the second plurality of bond pads.
12. A semiconductor device assembly, according to claim 10, wherein:
at least two bond pads in the second plurality of bond pads are disposed in
a collinear arrangement, on a common side of the axis, along a line
perpendicular to the axis; and
at least one of the third plurality of conductive fingers is connected to
the at least two collinear bond pads in the second plurality of bond pads.
13. A semiconductor device, according to claim 1, wherein:
the bond pads of the first and second plurality of bond pads are of the
type suitable for making solder-bump type connections to conductive
fingers of a leadframe.
14. A semiconductor device assembly, according to claim 10, wherein:
the bond pads of the first and second plurality of bond pads are connected
to the respective pluralities of conductive fingers by solder-bump type
connections.
15. A semiconductor device assembly, according to claim 10, wherein:
the first bond pads are disposed at selected first longitudinal positions
along the axis;
the second bond pads are disposed at selected second longitudinal
positions, offset from the axis; and
at least a portion of the selected second longitudinal positions are
distinct from the selected first longitudinal positions.
16. A semiconductor device assembly according to claim 10, wherein:
the first bond pads are disposed at selected first longitudinal positions
along the axis;
the second bond pads are disposed at selected second longitudinal
positions, offset from the axis; and
at least a portion of the selected second longitudinal positions are
coincident with a portion of the selected first longitudinal positions.
17. A semiconductor device assembly, according to claim 10, further
comprising:
a first limit line defined on the surface of the die to one side of the
axis, parallel to the axis and located a first distance from the axis
equal to approximately one-quarter of the width of the die;
a second limit line defined on the surface of the die to an opposite side
of the axis, parallel to the axis and located a second distance from the
axis equal to approximately one-quarter of the width of the die; and
a placement area on the surface of the die between the first limit line and
the second limit line;
wherein:
the second plurality of bond pads is disposed entirely within the placement
area.
18. A semiconductor device assembly, according to claim 10, wherein:
at least two of the bond pads in the second plurality of bond pads are
disposed in a collinear arrangement, on a common side of the axis, along a
line perpendicular to the axis. |
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Claims |
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Description |
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TECHNICAL FIELD OF THE INVENTION
The invention relates to integrated circuit fabrication techniques, and
more particularly to techniques for forming electrical connections with an
integrated circuit die.
BACKGROUND OF THE INVENTION
As used herein, the term "semiconductor device" refers to a silicon chip or
die containing circuitry, and the term "semi conductor device package"
refers to the semi conductor device and associated packaging containing
the chip, including leads such as for connecting to a socket or a circuit
board, and internal connections, such as bond wires or solder bump (e.g.,
micro-bump) connections, of the chip to the leads.
In a typical modern semiconductor device package, a semiconductor die
(device) is disposed within a package and is connected to conductive leads
of the semiconductor device package (assembly) by means of bond wires or
"solder bump" (micro-bump) connections. The connections to the
semiconductor die are accomplished via metallic connection points or "bond
pads" (I/O pads) disposed on a planar surface of the die, around the
periphery (along the edges) thereof in a "peripheral area". The peripheral
area is a ring-shaped area on the surface of the die, essentially a narrow
band between the edges of the die and the "interior area" of the die. The
conductive leads of the semiconductor device package may be provided by a
leadframe, such as in a molded plastic or TAB (Tape Automated Bonding)
semi conductor device package, or by printed traces, such as in a ceramic
or overmolded printed circuit board package. The conductive leads approach
the semiconductor die within the semi conductor device package in a
generally radial pattern. They may also approach the die in parallel
ranks, from one or more edges of the die.
Typically, a leadframe is stamped (or etched) from a sheet (foil) of
conductive material, simultaneously forming all of the conductive leads of
the leadframe. Often, the leadframe is held together by sacrificial
"bridges" between the leads, which are removed after the leadframe is
assembled to a die and a package body is formed. The leads are then
effectively separate. However, by virtue of their common mounting within a
package body, they continue to behave, in many respects, as a unit.
As the circuitry on a die operates, it dissipates power and heats up.
Often, there is a mismatch between the thermal coefficients of expansion
(TCE) of a semiconductor die and the leadframe (and package body) to which
it is attached. This is especially troublesome where solder bump
(micro-bump) connections are used to connect the die to the leadframe. (It
is assumed that the heating of the die as it operates is fairly uniform).
The die expands about its "centroid" (center of mass) as temperature
rises, as do the leadframe and package body. However, the die expands at a
different rate than the leadframe and package body, causing a great deal
of mechanical stress at the interface between the leadframe and the bond
pads (the solder bump connections). This stress creates a tendency of the
bond pads to tear away from the die.
On any thermally expanding body, the further a point on the body is from
the centroid, the greater the absolute distance it travels (displaces)
during expansion. Since semiconductor dies are typically rectangularly
shaped and the bond pads are typically disposed along the edges of the
rectangular shape (in the peripheral area), the bond pads undergo a fairly
large absolute displacement as compared to points located closer to the
center of the die. Any bond pads located at the corners of the die, being
furthest from the centroid, undergo the greatest displacement during
thermal expansion. As a consequence of the absolute thermal displacements
that any two different points undergo on the surface of the die, they
undergo differential thermal displacements relative to one another. The
further from one another that any two points on the surface of an
expanding die are, the greater the differential thermal displacement
between them. The leadframe and package body combination also expands
about its centroid, albeit at a different rate. The center of expansion of
the leadframe/package body combination is generally located fairly close
to the centroid of the die, since the die is the heat source which causes
the expansion. As a result, any differential thermal displacement causing
mechanical stress at the bond pads of a semiconductor device is greatest
at the corners of the die. The common practice of disposing bond pads
along the edges of the die, therefore, would seem to create the worst
possible circumstances from the point of view of thermal expansion.
Although the thermal expansion problem is most severe with micro-bump
(solder bump) connections to a relatively rigid leadframe assembly, the
same expansion characteristics apply to the die and leadframe/package body
even if bond wires are used to connect the bond pads on the die to the
leadframe. While bond wire connections are considerably more flexible and
resilient than are solder bump connections, thermal flexing of bond wire
connections can create long-term reliability problems.
One of the most significant reasons that bond pads are typically disposed
about the edges (periphery) of a die is that the peripheral location of
bond pads permits a relatively large number of connections to the die
without causing connections (e.g., bond wires) to cross over one another.
Current trends are towards providing smaller bond pads so that even
greater numbers of I/O (and power) connections to the die may be
accommodated. Unfortunately, these smaller bond pads are even more fragile
than "ordinary" (larger) size bond pads, making such techniques even more
prone to thermal stress problems.
Another problem with locating bond pads along the periphery of a die is
that many of the connections are made to circuitry that lies well within
the interior area of the die, requiring that the signals to and from that
circuitry (and, in some cases, power to the circuitry) travel a relatively
great distance within the die along the die's minute wiring structures
(conductive lines) before they reach the bond pad connection. Hence, a
"pad buffer" circuit is usually provided at or near a bond pad associated
with an output signal to buffer the output signal at the bond pad. These
factors can contribute to timing "skew", or differences in signal timing
due to different wiring delays, particularly for very high speed circuits,
which presents additional challenges to the circuit designer. The wiring
structures (interconnections, or conductive lines) on the die are
extremely small and exhibit relatively high (i.e., non-trivial)
resistance. Even a tiny bond wire is a massive conductor compared to the
relatively tiny interconnection lines on a die.
Power distribution to the chip is also hampered to some degree by the
location of bond pads in the peripheral area. Circuits located close to
the centerline (centrally located circuits) of the die receive power from
the pads at the periphery of the die, usually along a branched "bus"
structure formed in the wiring layers of the die. Power is distributed to
other circuits between the pads and the centrally located circuits before
it reaches the center of the die. While the power "bus" structure is
typically routed in a fairly direct fashion, some branches of the power
distribution bus can become fairly tortuous in reaching certain circuits.
Many circuits located within the interior area of the die, particularly
centrally located circuits, may receive power along a wiring path the
length of which is greater than one half of the distance across the die.
As a result, line losses and electrical noise problems may be experienced
by those circuits which are most distant from the power distribution
(bond) pads, particularly the centrally located circuits.
In order to minimize such line losses and electrical noise, it is common
practice to provide multiple bond pads distributed about the periphery of
the die for each power supply voltage. However, this does not solve the
problem of the length of the power distribution path in the internal
wiring layers of a die required to reach centrally located circuits.
Attention is directed to the following U.S. Patents, incorporated herein by
reference, and of general interest with respect to leadframe-type semi
conductor device packages and methods for manufacture thereof: U.S. Pat.
No. 4,701,999 issued Oct. 27, 1987 to Palmer, U.S. Pat. No. 4,774,635
issued Sep. 27, 1988 to Greenberg et al., U.S. Pat. No. 4,894,704 issued
Jan. 16, 1990 to Endo, U.S. Pat. No. 4,897,602 issued Jan. 30, 1990 to Lin
et al., and U.S. Pat. No. 5,051,813 issued Sep. 24, 1991 to Schneider et
al.
Attention is further directed to the following U.S. Patents, incorporated
herein by reference, and of general interest with respect to micro-bump
(e.g., solder bump) bonding: U.S. Pat. No. 3,429,040 issued Feb. 25, 1969
to Miller, U.S. Pat. No. 3,811,186 issued May 21, 1974 to Larnerd et al.,
U.S. Pat. No. 3,871,014 issued Mar. 11, 1975 to King et al., U.S. Pat. No.
3,984,860 issued Oct. 5, 1976 to Logue, U.S. Pat. No. 4,190,855 issued
Feb. 26, 1980 to Inoue, U.S. Pat. No. 4,772,936 issued Sep. 20, 1988 to
Reding et al., U.S. Pat. No. 4,803,546 issued Feb. 7, 1989 to Sugimoto et
al., U.S. Pat. No. 4,825,284 issued Apr. 25, 1989 to Soga et al., U.S.
Pat. No. 4,926,241 issued May 15, 1990 to Carey, and U.S. Pat. No.
4,970,575 issued Nov. 13, 1990 to Soga et al.
Other information relating to microbump bonding techniques may be found in
Japanese Patent number 61-145838A issued on Jul. 3, 1986 to Kishio
Yokouchi, and in "LED Array Modules by New Technology Microbump Bonding
Method," by Hatada, Fujimoto, Ochi, and Ishida, IEEE Trans. Comp.,
Hybrids, and Manuf. Tech., Volume 13 no. 3, Sep. 1990, incorporated by
reference herein.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide an improved
technique for distributing power to circuits of (circuitry within) a die.
It is a further object of the present invention to provide a technique for
shortening the maximum length of power distribution wiring paths
(conductive lines, in the die) to circuits on a semi conductor die.
It is a further object of the present invention to provide a technique for
minimizing line losses in distributing power to various circuit elements
in a semiconductor (integrated circuit) die.
It is a further object of the present invention to provide a technique for
minimizing electrical noise resulting from power distribution to a
semiconductor die, by providing a technique that more directly supplies
power to the circuitry on a die via substantially direct (non-tortuous)
paths.
It is a further object of the present invention to accomplish the foregoing
objects in the context of both bond wire and micro-bump connections to
semiconductor dies.
It is a further object of the present invention to accomplish the foregoing
objects in the context of minimizing thermally created stresses at bond
pad interfaces to semiconductor dies.
Hereinafter, the planar surface area of a semiconductor die in the
immediate vicinity of the edges of the die will be referred to as the
"peripheral area", and bond pads disposed in this peripheral area will be
referred to as "peripheral bond pads". Also, the planar surface area of
the die located inside of (surrounded by) the peripheral area will be
referred to as the "interior area" of the die, and bond pads disposed
within the "interior area" will be referred to as "interior bond pads".
According to the invention, it is posited that differential thermal
displacements between points on a body due to thermal expansion of the
body are proportional to the distance between the points. It is further
posited that the absolute thermal displacement of a point on a body
relative to the thermal center of expansion is proportional to the
distance between the point and the thermal center of expansion. Also, if
two bodies have different thermal coefficients of expansion and are
thermally coupled at a point near their respective centroids, then
differential thermal displacement and absolute thermal displacements
between points on the different bodies will behave similarly.
It is further posited that leadframe fingers and/or bond wires are
considerably stiffer relative to end displacement in a longitudinal
direction (along their length) than to end displacement in a lateral
direction (perpendicular to their length). Therefore, lateral thermal
displacements of the ends of bond wires or leadframe fingers due to
differential expansion create less mechanical stress on bond pad
interfaces than do longitudinal thermal displacements. Accordingly, the
present invention seeks to place signal-carrying bond pads along an "axis"
of a semiconductor die. The "axis" is an imaginary line which passes over
(or near) the centroid (center of mass and/or center of thermal expansion)
of the die. Since the axis lies over the centroid of the die, bond pads
placed along the axis experience only longitudinal displacement (along the
axis), and little or no lateral thermal displacement (away from the axis).
On-axis bond pads do, however, displace thermally along the length
(longitudinally along) the axis. Since bond wires and/or leadframe fingers
will approach the bond pads from a direction substantially perpendicular
to the axis, this longitudinal thermal displacement of bond pads along the
axis translates to lateral end displacement of the bond wires and/or
leadframe fingers. Since lateral displacement of the bond pads relative to
the axis is minimal, longitudinal end displacements of the leadframe
fingers and/or bond wires are correspondingly small. In this manner, by
orienting the bond pads along a line substantially perpendicular to the
leadframe fingers (or bond wires), problems associated with
thermally-induced migration of the bond pads can be minimized.
According to a feature of the invention, in order to better distribute
power to the semiconductor die, power-carrying bond pads are disposed in
an off-axis configuration in an area centered about the axis (centerline)
equal to about one half of the total die area.
In one embodiment of the invention, a semiconductor device with off-axis
interior bond pads for power distribution comprises a semiconductor die,
circuitry formed within the die, a first plurality of bond pads disposed
on the die in a linear configuration along an axis of the die, and a
second plurality of bond pads disposed on the die, within an interior area
of the die and spaced away from the axis (e.g., centerline). Signal
connections (to a leadframe or to bond wires) are formed between the first
plurality of bond pads and the circuitry, and power connections (to a lead
frame or to bond wires) are formed between the second plurality of bond
pads and the circuitry.
According to one aspect of the invention, a first limit line and a second
limit line are defined on the surface of the die, located on opposite
sides of the axis, parallel to the axis and located a distance from the
axis equal to one-quarter of the width of the die. A placement area is
defined on the surface of the die between the first limit line and the
second limit line. The second plurality of bond pads is disposed entirely
within the placement area.
According to another aspect of the invention, at least two of the bond pads
in the second plurality of bond pads are disposed in a collinear
arrangement, on opposite sides of the axis, along a line perpendicular to
the axis.
According to another aspect of the invention, at least two of the bond pads
in the second plurality of bond pads are disposed in a collinear
arrangement, on a common side of the axis, along a line perpendicular to
the axis.
Other embodiments of the invention are directed to forming the semi
conductor device arrangements described above.
Both the first (signal-carrying) and the second (power-distributing)
pluralities of bond pads are preferably "interior" bond pads, located in
an interior (non-peripheral) area of the die.
Further, according to the invention, if circuits on a semiconductor die are
located distant from the desired "interior" bond pad locations, that
existing and/or extra wiring (metallization) layers may be employed to
provide connection between these circuits and bond pads at the desired
locations. This is particularly useful in applying the present inventive
technique to semiconductor dies which were originally laid out for bond
pads in the peripheral area. Existing and/or additional wiring layers may
be employed to route signals from the original (designed) bond pad
positions to the new (desired, according to the inventive technique)
interior bond pad positions.
Other objects, features and advantages of the invention will become
apparent in light of the following description thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top view of a semiconductor die with an off-axis bond pad
pattern for power distribution, according to the present invention.
FIG. 2a is a top view of a semiconductor die with a compound off-axis bond
pad pattern for power distribution, according to an alternate embodiment
of the invention.
FIG. 2b is a side view of a leadframe finger connection to an off-axis
compound pair of bond pads, according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
According to the invention, it is posited that if an array of bond pads on
a semiconductor die is tightly (closely) grouped (arranged or clustered),
then the amount of differential thermal expansion between those bond pads
will be correspondingly small, and that if such a small array of bond pads
is located close to the centroid of the die, then the absolute thermal
displacement of the bond pads will be correspondingly small.
Similarly, if the ends of the conductive leads of a leadframe (or bond
wires) connecting to the die form a small pattern, the differential
thermal displacement of the ends of the leads will be correspondingly
small. Also, if the small pattern formed by the ends of the conductive
leads is located close to the center of expansion of the leadframe, then
the absolute thermal displacement of the ends of the conductive leads will
be correspondingly small. According to the invention, these principles may
be used to great advantage in the packaging of semi conductor dies.
While the industry trend is largely towards increasing the number of
connections to a semiconductor die, certain types of semiconductor
devices, despite great complexity, do not require large numbers of I/O
connections. One example of this type of semiconductor device is any type
of memory device (e.g., ROMs, RAMs, including dynamic RAM and static RAM,
etc.) Memory devices are highly repetitive arrays of circuitry with a
relatively small number of I/O connections thereto. In cases such as
these, there is no need to use the large bond pad capacity of the
periphery of the die. In fact, according to the invention, it is extremely
advantageous (from a thermal expansion point of view) to locate the bond
pads in a relatively small array, preferably, but not necessarily, towards
the centroid of the die.
Leadframe fingers and, to a lesser degree, bond wires are stiffest (most
rigid and unbending) along their length, since any displacement of the end
of the leadframe finger or bond wire tends to put it in compression.
Although bond wires are considerably more tolerant of any kind of end
displacement th | | |
