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Claims  |
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What is claimed is:
1. A method for reducing an amount of power used by a system having one or
more devices, said method comprising the steps of:
determining a plurality of power supply modes for a device of said system,
said plurality of power supply modes being stored in a scoreboard;
selecting from said plurality of power supply modes a lowest power mode for
said device; and
altering an amount of power supplied to said device, said altering step
comprising placing said device in said selected lowest power mode.
2. The method of claim 1, wherein said lowest power mode includes one of a
depowered mode, a low voltage mode, a low voltage self-refresh mode, a
self-refresh mode and an active mode.
3. The method of claim 2, wherein said lowest power mode comprises said
depowered mode and said placing step comprises the steps of:
determining whether said device has been accessed in a predetermined amount
of time; and
reducing a voltage level of said device to zero volts, when said device has
not been accessed in said predetermined amount of time.
4. The method of claim 3, wherein said placing step further includes the
step of updating said scoreboard to reflect said lowest power mode.
5. The method of claim 2, wherein said lowest power mode comprises said low
voltage self-refresh mode and said placing step comprises the steps of:
reducing a voltage level of said device to a predetermined level;
initiating a self-refresh cycle; and
updating said scoreboard to reflect said lowest power mode.
6. The method of claim 2, wherein said lowest power mode comprises said low
voltage mode and said placing step comprises the steps of:
reducing a voltage level of said device to a predetermined level; and
updating said scoreboard to reflect said lowest power mode.
7. The method of claim 2, wherein said lowest power mode comprises said
self-refresh mode and said placing step comprises the steps of:
initiating a self-refresh cycle; and
updating said scoreboard to reflect said lowest power mode.
8. The method of claim 1, wherein said system has more than one device and
each of said more than one device has a plurality of power supply modes
associated therewith.
9. The method of claim 1, wherein the scoreboard is programmable.
10. The method of claim 1, wherein said plurality of power supply modes
comprises more than two power supply modes.
11. A system for reducing an amount of power used by a system having one or
more devices, said system comprising:
means for determining a plurality of power supply modes supported by a
device of said system, said plurality of power supply modes being stored
in a scoreboard;
means for selecting from said plurality of power supply modes a lowest
power mode for said device; and
means for altering an amount of power supplied to said device, said
altering means comprising means for placing said device in said lowest
power mode.
12. The system of claim 11, wherein said lowest power mode includes one of
a depowered mode, a low voltage mode, a low voltage self-refresh mode, a
self-refresh mode and an active mode.
13. The system of claim 12, wherein said lowest power mode comprises said
depowered mode and said means for placing comprises:
means for determining whether said device has been accessed in a
predetermined amount of time; and
means for reducing a voltage level of said device to zero volts, when said
device has not been accessed in said predetermined amount of time.
14. The system of claim 13, wherein said means for placing further
comprises means for updating said scoreboard to reflect said lowest power
mode.
15. The system of claim 12, wherein said lowest power mode comprises said
low voltage self-refresh mode and said means for placing comprises:
means for reducing a voltage level of said device to a predetermined level;
means for initiating a self-refresh cycle; and
means for updating said scoreboard to reflect said lowest power mode.
16. The system of claim 12, wherein said lowest power mode comprises said
low voltage mode and said means for placing comprises:
means for reducing a voltage level of said device to a predetermined level;
and
means for updating said scoreboard to reflect said lowest power mode.
17. The system of claim 12, wherein said lowest power mode comprises said
self-refresh mode and said means for placing comprises:
means for initiating a self-refresh cycle; and
means for updating said scoreboard to reflect said lowest power mode.
18. The system of claim 11, wherein said system has more than one device
and each of said more than one device has a plurality of power supply
modes associated therewith.
19. The system of claim 11, wherein the scoreboard is programmable.
20. The system of claim 11, wherein said plurality of power supply modes
comprises more than two power supply modes.
21. A method for automatically reducing an amount of power utilized by a
system having one or more devices, said method comprising the steps of:
determining whether a device of said system has been accessed within a
preselected amount of time;
selecting from a scoreboard an amount of power to be supplied to said
device; and
supplying to said device said selected amount of power when said device has
not been accessed within said preselected amount of time.
22. The method of claim 21, wherein said selecting step includes the steps
of:
determining a plurality of power supply modes for said device; and
selecting from said plurality of power supply modes a lowest power mode for
said device.
23. The method of claim 22, wherein said lowest power mode includes one of
a depowered mode, a low voltage mode, a low voltage self-refresh mode, a
self-refresh mode and an active mode.
24. The method of claim 21, wherein the scoreboard is programmable.
25. A system for automatically reducing an amount of power utilized by a
system having one or more devices, said system comprising:
means for determining whether a device of said system has been accessed
within a preselected amount of time;
means for selecting from a scoreboard an amount of power to be supplied to
said device; and
means for supplying to said device said selected amount of power when said
device has not been accessed within said preselected amount of time.
26. The system of claim 25, wherein said means for selecting comprises:
means for determining a plurality of available power supply modes for said
device; and
means for selecting from said plurality of power supply modes a lowest
power mode for said device.
27. The system of claim 26, wherein said lowest power mode includes one of
a depowered mode, a low voltage mode, a low voltage self-refresh mode, a
self-refresh mode and an active mode.
28. The system of claim 25, wherein the scoreboard is programmable.
29. A memory controller for a computer system having one or more devices,
said memory controller comprising a computer interface having circuitry to
perform a number of functions, said circuitry including a scoreboard for
storing a plurality of power modes for at least one of said one or more
devices and means for determining a lowest power mode stored in said
scoreboard for at least one of said one or more devices.
30. The memory controller of claim 29, wherein said memory controller is
coupled to a voltage generation means and wherein said voltage generation
means receives from said memory controller a voltage value indicative of
said lowest power mode.
31. The memory controller of claim 30, further comprising at least one
counter, said at least one counter being used to indicate whether said at
least one of said one or more devices has been accessed in a predetermined
amount of time.
32. A method for reducing an amount of power used by a system having one or
more devices, said method comprising the steps of:
determining more than two voltage supply levels for a device of said
system, said more than two voltage supply levels being stored within said
system;
selecting from said more than two voltage supply levels a lowest voltage
level for said device; and
placing said device at said selected lowest voltage level.
33. A system for reducing an amount of power used by a system having one or
more devices, said system comprising:
means for determining more than two voltage supply levels for a device of
said system, said more than two voltage supply levels being stored within
said system;
means for selecting from said more than two voltage supply levels a lowest
voltage level for said device; and
means for placing said device at said lowest voltage level.
34. A method for reducing an amount of power used by a system having one or
more memory banks, said method comprising the steps of:
determining a plurality of power modes for a memory bank of said system,
said plurality of power modes being stored within said system;
selecting from said plurality of power modes a lowest power mode for said
memory bank; and
placing said memory bank in said lowest power mode.
35. The method of claim 34, wherein said system has a plurality of memory
banks and wherein said determining step determines a plurality of power
modes for each memory bank, and wherein said selecting step selects for
each memory bank a lowest power mode for that memory bank, and wherein
said placing step places each memory bank in its lowest power mode.
36. A system for reducing an amount of power used by a system having one or
more memory banks, said method comprising:
means for determining a plurality of power modes for a memory bank of said
system, said plurality of power modes being stored within said system;
means for selecting from said plurality of power modes a lowest power mode
for said memory bank; and
means for placing said memory bank in said lowest power mode.
37. The system of claim 36, wherein said system has a plurality of memory
banks and wherein said means for determining determines a plurality of
power modes for each memory bank, and wherein said means for selecting
selects for each memory bank a lowest power mode for that memory bank, and
wherein said means for placing places each memory bank in its lowest power
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Claims |
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Description |
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TECHNICAL FIELD
This invention relates in general to power management, and more
particularly, to a method and system for managing the power utilized by a
system such that the required amount of power for the system is reduced.
BACKGROUND ART
Power management in systems, such as personal and laptop computers, is
essential to maximizing battery life, reducing the amount of power
utilized by the system and enhancing the reliability of system components.
Many components within a computer system utilize power, including the
system memory.
Typically, only a portion of the supplied amount of system memory is used,
however, the entire amount of memory continues to use valuable power
resources. This needlessly increases the amount of power being used by the
system and possibly decreases the reliability of one or more system
components.
Therefore, a need exists for a technique to manage the utilization of power
by a system such that the required amount of power is reduced. Further, a
need exists for a technique which is capable of reducing the amount of
power used by a system in a manner which is dynamic and independent of the
system processor. A further need exists for a power management method and
system which automatically places a device in its lowest available power
mode when the device has not been accessed for a predetermined amount of
time.
DISCLOSURE OF INVENTION
The shortcomings of the prior art are overcome and additional advantages
are provided in accordance with the principles of the present invention
through the provision of a method for reducing an amount of power used by
a system having N devices. The method includes determining a plurality of
power modes for at least one of the N devices, selecting from the
plurality of power modes a lowest available power mode in which at least
one of the N devices may be placed and placing at least one of the N
devices in the lowest available power mode.
In one embodiment, the plurality of power modes is retrieved from a
scoreboard and the lowest available power mode includes one of a depowered
mode, a low voltage mode, a low voltage self-refresh mode, a self-refresh
mode or an active mode. Further, placing a device in a depowered mode
includes determining whether the device has been accessed in a
predetermined amount of time and reducing a voltage level of the device to
zero volts when the device has not been accessed within the predetermined
amount of time.
In another aspect of the invention, a system for reducing an amount of
power used by a system having N devices is provided. The system includes
means for determining a plurality of power modes supported by at least one
of the devices, means for selecting from the plurality of power modes a
lowest available power mode in which at least one of the devices may be
placed and placing at least one of the devices in the lowest available
power mode.
In a further aspect of the invention, a method for automatically reducing
an amount of power utilized by a system having N devices is provided. The
method includes determining whether at least one of the N devices has been
accessed within a preselected amount of time and decreasing an amount of
power used by at least one of the devices, when the device has not been
accessed within the preselected amount of time.
In one embodiment, decreasing the amount of power includes determining a
plurality of available power modes for at least one of the N devices,
selecting from the plurality of power modes a lowest available power mode
for at least one of the N devices and reducing the power used by at least
one of the N devices to the selected lowest power level.
In yet a further aspect of the present invention, a memory controller for a
computer system having N devices is provided. The memory controller
includes a computer interface having circuitry to perform a number of
functions. The circuitry includes a scoreboard for storing a plurality of
available power modes for at least one of the N devices and means for
determining a lowest available power mode stored in the scoreboard for at
least one of the N devices.
The power management technique of the present invention reduces the amount
of power required by a system without the need for processor intervention
or software or microcode modifications. The method and system of the
present invention for managing the utilization of power provides for
dynamic reduction in the amount of power used by one or more devices such
that the total amount of power used by the system is reduced. Further, a
user is capable of determining how many of the devices or how much of the
memory may receive a reduction in power or even no power.
BRIEF DESCRIPTION OF DRAWINGS
The subject matter which is regarded as the invention is particularly
pointed out and distinctly claimed in the claims at the conclusion of the
specification. The foregoing and other objects, features and advantages of
the invention will be apparent from the following detailed description
taken in conjunction with the accompanying drawings in which:
FIG. 1 depicts a block diagram of one embodiment of a computer processing
system associated with the power management technique of the present
invention;
FIG. 2 illustrates one example of the main components associated with the
memory subsystem depicted in FIG. 1, in accordance with the principles of
the present invention;
FIG. 3 depicts one embodiment of the main components of the memory
controller depicted in FIG. 1, of the present invention;
FIG. 4 depicts one embodiment of the main components of a power management
scoreboard of the present invention;
FIG. 5 depicts one example of a logic flow diagram for powering up a memory
subsystem, in accordance with the principles of the present invention;
FIG. 6 depicts one example of a logic flow diagram for placing one or more
banks of a memory subsystem in a lowest supported power level for each
bank, in accordance with the principles of the present invention; and
FIG. 7 depicts one example of a logic flow diagram for accessing a location
within system memory, in accordance with the principles of the present
invention.
BEST MODE FOR CARRYING OUT THE INVENTION
In accordance with the principles of the present invention, a method and
system for managing power are described in detail herein. The power
management technique of the present invention may be used to manage the
power associated with a variety of devices. For instance, the power
management method and system of the present invention may be used to
manage the power associated with a memory subsystem or to manage the power
being supplied to a number of disk drives or tape drives. In addition, the
power management technique may be used in any situation in which it is
desired to reduce the power being supplied to a number of devices. Device
as used herein is meant to encompass all of the above situations. It
includes, for instance, a memory chip, a memory bank or another segment of
memory, a disk drive, a tape drive, a cartridge or any other components in
which the technique of the present invention may be applied.
One example of a preferred embodiment of the method and system for managing
power is described in detail herein with reference to the drawings. The
method and system are described as they relate to power management for a
computer memory subsystem (such as, for example, a memory subsystem in a
personal computer or a laptop computer). It will be apparent to those of
ordinary skill in the art that the method and system of power utilization,
as described herein, may be used in a variety of computer systems and
other systems.
Depicted in FIG. 1 is one example of the main components associated with a
computer processing system 10. System 10 includes, for instance, a
standard central processing unit (CPU) 12, a memory subsystem 14 and a
standard input/output (I/O) unit 16. In one embodiment, memory subsystem
14 includes a conventional system configuration device 18, a memory
controller 20, a system memory 22 and a programable memory power system
24. Each of the above-referenced components is described in further detail
herein.
Central processing unit 12 contains the sequencing and processing
facilities for controlling the operation of system 10 and is coupled to
system configuration device 18 and memory controller 20 via a central
processing unit bus 26. System configuration device 18 includes the
configuration data for system 10 and may be, for example, an electrically
erasable programmable read only memory (EEPROM) or read only memory (ROM).
Memory controller 20 is coupled to system memory 22 and programmable memory
power system 24 and is used to control the access, activation and
deactivation of system memory 22, in accordance with the principles of the
present invention. The voltage supplied to system memory 22 is controlled,
in accordance with the present invention, by programmable memory power
system 24, which is coupled to system memory 22. As described in detail
below, programmable memory power system 24 receives a number of inputs
from memory controller 20 and based on the inputs determines how much
voltage is to be supplied to system memory 22. This provides the
flexibility of dynamically altering the voltage being supplied to system
memory 22. (Programmable memory power system 24 is used, in accordance
with the principles of the present invention, to reduce the voltage to one
or more devices, thereby reducing the power to the device. It is also
possible, however, to reduce the power of a device, as described in detail
below, without altering the voltage and using the programmable memory
power system.)
Memory controller 20 is also coupled to input/output unit 16 via an
expansion bus 28. Input/output unit 16, includes, for instance, one or
more typical input/output devices for providing information to or
receiving information from system 10.
Memory subsystem 14 is described in greater detail with reference to FIG.
2. Referring to FIG. 2, system memory 22 is, for example, dynamic random
access memory (DRAM) and includes, for instance, a number of memory
devices or banks 30. As used herein, a bank of memory designates the
lowest granularity of memory that can be placed into a low power mode, in
accordance with the principles of the present invention. A bank may be,
for instance, a RAS (row address strobe) bank, a CAS (column address
strobe) bank, one or more memory chips, one or more memory modules Or a
segment of memory. In one embodiment, each bank is at least the width of
CPU bus 26. As one example, if system memory 22 has sixteen megabytes of
data, then the memory may include four banks of four megabytes each.
As depicted in FIG. 2, system memory 22 includes N banks 30 and each bank
includes a number of inputs and one or more outputs. Input into each bank
30 are memory address lines 32, which specify the address of a memory
location in a bank in which data may be read from or written to; a
bidirectional memory data bus 34, which is the transport of data between
memory controller 20 and system memory 22; a control bus 36, which
includes the controls for each of the banks (e.g., RAS and CAS lines,
read/write lines) and programmable memory power system 24; and a voltage
input 38, which provides voltage to each of the banks of memory. As shown,
in accordance with the principles of the present invention, each bank 30
has a separate voltage input 38 such that the power of each bank may be
regulated separately.
One output of each bank is a presence detects bus 40. In one example,
presence detects bus 40 is an encoded binary sequence of signals which
represents a plurality of attributes such as, DRAM (memory) size,
addressing, memory configuration, timing, and, in accordance with the
present invention, the power modes for a bank, as described further below.
Presence detects bus 40 may be either a serial bus or a parallel bus. The
information on the presence detects bus 40 is passed either to central
processing unit 12 (reference number 42) or directly to memory controller
20 (reference number 44). Should the information be passed to the central
processing unit, the information is programmed through standard
programmable input/output cycles and then, the programmed information is
passed to the memory controller in order to advise the controller of the
attributes of system memory 22.
As previously mentioned, control bank buses 36 are input into programmable
memory power system 24, as well as, a voltage programmable bus 46. Control
buses 36 indicate to programmable memory power system 24 which bank the
data coming in on voltage programmable bus 46 is to be applied. Voltage
Programmable bus 46 passes from memory controller 20 to programmable
memory power system 24 a digital encoding of the voltage to be applied to
the bank indicated by control bank buses 36. In one embodiment,
programmable memory power system 24 includes a voltage regulator (e.g., a
DC/DC regulator) for each bank in the memory. Each regulator receives a
corresponding control bank bus 36 input and voltage programmable bus 46
input. The inputs are used to produce a voltage output signal 48 for each
of the banks. Each of the voltage output signals go through a standard
deglitch circuit 50 (one example of a deglitch circuit is offered by
Toshiba and is described in Toshiba MOS Memory Products Package K-149
H3K-830, October 1991, which is hereby incorporated by reference). Each
output of deglitch circuit 50 is the actual voltage signal 38 to be input
to a respective bank 30.
Referring to FIG. 3, memory controller 20 is described in greater detail.
Memory controller 20 is the unit that controls system memory 22 and
includes, for instance, one or more buffers 52, a main central processing
unit (CPU) machine 54, a controller program registers unit 56, an address
compare/bank select/remapping unit 58, a system memory machine 60, a
refresh control unit 61, a main I/O machine 62, a power management
scoreboard 64, a power management machine 66 and an initialize diagnostics
power up unit 68. Each of the main components of memory controller 20 is
described in detail below.
Buffers 52 are optional and are used to reduce latency by stacking command
and data which cannot be used at the time it is received by controller 20.
For example, should the central processing unit want to write data to a
bank of memory which is not powered up yet, then the data may be stored in
one or more buffers so that the processor may continue working while the
bank is being powered up.
Main CPU machine 54 is a conventional state machine which receives from
central processing unit bus 26 each cycle that is input to controller 20.
Main CPU machine 54 determines what type of cycle is being inputted, such
as a read, write or input/output. In addition, it provides the timing,
sequencing and coordination activities between central processing unit 12
and memory controller 20.
Controller program registers unit 56 includes one or more registers which
receive and store the configuration information for system memory 22. Unit
56 includes, for instance, attributes (such as timing information, how
long to hold the RAS or CAS, information concerning refresh), address
support and bank address ranges for system memory 22.
Address compare/bank select/remapping unit 58 receives an address from the
central processing unit or another component and performs an address
compare to determine which bank corresponds to the address. In addition,
the remapping portion of unit 58 handles remapping of one address to
another.
System memory machine 60 is a state machine which handles the real time
interface between the central processing unit and system memory 22. In
accordance with the principles of the present invention, additional timing
sequences have been added to system memory machine 60 to accommodate power
up, depowered, pause and self-refresh cycles initiated by power management
machine 66, as described in detail below. System memory machine 60
receives the address and bank information which is provided by address
compare/bank select/remapping unit 58 and converts the address to RAS and
CAS lines so that data may be written to or retrieved from the system
memory.
Refresh control unit 61 is used to provide the necessary timing and
controls to accomplish a refresh. As is known, refresh control unit 61
typically is present within the memory controller but it (or a portion of
it) can reside outside of the controller.
Main I/O machine 62 is, for instance, a conventional state machine which
manages the interface, in a two bus system, between the memory controller
and input/output unit 16. If the system is a one bus system, then main CPU
machine 54 and main I/O machine 62 may be combined.
In accordance with the principles of the present invention, power
management scoreboard 64, power management machine 66 and initialize
diagnostics power up unit 68 have been added to memory controller 20 in
order to support the method and system for managing power utilization of
the present invention.
Power management scoreboard 64 includes, for example, a global
configuration register 70 (FIG. 4), a bank configuration register 72 and a
bank status register 74, each of which is described in detail with
reference to FIG. 4.
Referring to FIG. 4, global configuration register 70 includes, for
instance, a 4-bit minimum base memory size 75, which indicates the
smallest size a bank of memory may be (e.g., 1M, 2M or 4M); a 4-bit
incremental size 77, which indicates the amount of memory to be added when
an increase in memory is desired; an 8-bit timeout value 79, which is
referenced by each memory bank and indicates the amount of time that may
elapse before a memory bank is lowered to a lower power mode; a 1-bit
enable global power management indicator 81, which indicates whether power
management is desired; a 1-bit enable self-refresh indicator 83, which
indicates whether self-refresh mode is available; a 1-bit enable voltage
switch indicator 85, which indicates whether a change in voltage is
supported within the system; a 1-bit enable power on diagnostics indicator
87, which indicates whether diagnostics is to be performed when a bank is
powered up; a 1-bit initial power up of all memory indicator 89, which
indicates whether it is desired to have all of the memory banks initially
powered up; and a 1-bit enable bank deallocation on error indicator 91,
which indicates whether bank deallocation should take place if an error is
encountered on bank power up. The information in the global configuration
register is provided, for example, via both system detection of installed
memory (e.g., presence detects 40) and customer provided memory usage
parameters.
In one embodiment, there exists two copies of global configuration register
70: one for AC operation and one for DC operation. This provides the
flexibility of having different global values for the system memory
depending on the type of system operation. For example, timeout value 79
may equal, e.g., thirty minutes when the system is operating with AC and
five minutes when operating with DC.
Bank configuration register 72 includes, for instance, a 1-bit bank
installed indicator 93, which indicates whether a particular bank is
installed; a 3-bit bank size value 95, which indicates the size of the
memory bank; a 3-bit allowable voltage levels indicator 97, which
indicates the acceptable voltage levels for a particular bank (e.g., 5
volts, 3.3 volts, 2.5 volts, 0 volts); and a 2-bit allowable refresh modes
indicator 99, which indicates the supported refresh modes for a bank
(e.g., self-refresh, low voltage self-refresh, refresh). Data is provided
to the bank configuration register upon system interpretation of memory
presence detects, as described further below. There exists one bank
configuration register 72 for each memory bank 30 within system memory 22.
Bank status register 74 includes, for instance, a 3-bit current voltage
level 101, which indicates the voltage level in which a bank is currently
operating; a 2-bit current refresh mode 103, which indicates the present
refresh mode of a particular bank; an 8-bit timer status 105, which
indicates the amount of time which has elapsed since the bank was last
accessed; a 1-bit bank accessed indicator 107, which indicates whether the
bank has been accessed since diagnostics (excluding refresh); and a bank
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