Apparatus and methods are provided for producing a zoomed image signal from an input image signal. The input image signal is separated into a number of block signals each representing a subarea of the input image. Class codes are produced based on the block signals. Each class code identifies predetermined image data of a zoomed image portion which corresponds to the subarea represented by the block signal on which the class code is based. The predetermined image data is generated in response to each class code. Shifted display positions are assigned for image data of the selected block signals, and the zoomed image signal is synthesized from the image data having shifted display positions and the predetermined image data such that the predetermined image data are assigned display positions intermediate the shifted display positions of the other data.
In digital image processing, it is often necessary to alter the image by performing a zoom operation thereon. Such an operation is carried out with the use of a spatial interpolation unit. Described herein is a spatial interpolation unit which comprises a discrete set of filters for which at least some of the cut-off frequencies are logarithmically spaced.
A signal converting apparatus and a signal converting method which predictively produce highly accurate interpolated pixels in accordance with a classification which precisely reflects a variety of signal characteristics of inputted video signals to provide a high resolution video signal. An activity is evaluated and classified for each block of an inputted video signal (S.sub.1), and stepwise classifications are executed on each block of the inputted video signal (S.sub.1) in accordance with an activity code (c0) obtained as a result of the activity classification. In this way, the accuracy of subsequent classifications can be increased, reflecting the activity characteristic of each block of the inputted video signal (S.sub.1), thus achieving, as a whole, a highly accurate classification of the inputted video signal (S.sub.1). Appropriate prediction coefficients (d1) are read based on the activity code (c0) and a class code (c1) for each block of the inputted video signal (S.sub.1) to produce highly accurate interpolated pixels, thus providing a high resolution video signal (S.sub.2).
A digital signal process of a plurality of functions is enabled by a common hardware constructed on one chip having input terminals t1, t2 and t2'; output terminals t3 and t4; and a control signal input terminal t5. The chip is constructed to include class sorting circuits 111a and 111b; delay and selecting circuits 112a and 112b; switching circuits 113a and 113b; switching circuits 114a and 114b; coefficient memories 115a and 115b; filter operating circuits 116a and 116b; a line delay circuit 117; a product sum operating circuit 118; and a switching circuit 119. Signal flow and circuit functions are selectively controlled by control signals. The functions of the chip can be consequently switched and a plurality of signal processes are realized by one chip.
In a case that a zooming magnification is less than 2 times, the switch (SW) is connected to the terminal "a" and a zooming process in the horizontal direction is performed when reading out from the line memory (13) in conjunction with performing the zooming process in the vertical direction in the CCD (10). Further, in a case that the zooming magnification is more than 2 times, the switch (SW) is connected to the terminal "b" and the zooming process in the horizontal direction is performed with combining occasions when reading out from the memory (12) and reading out from the line memory (13) in conjunction with performing the zooming process in the horizontal direction when reading out from the memory (12).
An integrated circuit formed on a single chip, such as a large-scale integration (LSI) chip, which enables a plurality of digital signal processing functions to be performed. A desired digital signal processing function may be selected from among the plurality of available processing functions by the use of a control signal or signals supplied from outside the LSI chip. The LSI chip may include input terminals t1, t2, and t2'; output terminals t3 and t4; and a control signal input terminal t5. Additionally, the LSI chip may further include class sorting circuits, delay and switching circuits, switching circuits, coefficient memories, filter operating circuits, a line delay circuit, and a product sum operating circuit.