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Description  |
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FIELD OF THE INVENTION
This invention relates to a semiconductor memory device and, more
particularly, to a diagnostic circuit incorporated in the semiconductor
memory device for diagnosing memory cells.
DESCRIPTION OF THE RELATED ART
Most of the semiconductor memory devices, such as a dynamic random access
memory device, have an interface unit for a single-bit input/output data
signal or a four-bit input/output data signal. For a standard 1 mega-bit
dynamic random access memory device with a single-bit interface, the data
bits stored in the memory cell array are, by way of example, accessible at
80 nanoseconds, and the minimum cycle time is about 150 nanoseconds.
When the 1 mega-bit dynamic random access memory devices are fabricated
through a process sequence, the memory cells are subjected to inspections
to see whether or not any potential defects are incorporated therein. A
test data bit of either logic "1" or "0" level is simply written into and
read out from the memory cells during one of the inspections, and the
simple inspection consumes about 1.4 seconds. The manufacturer makes
inspections on not only the memory cell array but also the other component
units such as a built-in refreshing system, and total time period for the
inspections is never ignoreable.
The dynamic random access memory device progressively increases the memory
capacity, and the increased memory capacity prolongs the time period for
the inspections. For example, the simple inspection for a 4 mega-bit
dynamic random access memory device is prolonged from 1.4 seconds to 5.7
seconds, and the complicate circuit arrangement drastically prolongs the
total time period for the inspections.
One of the approaches against the prolonged time period for the inspections
is a parallel testing sequence. Built-in testing circuits allows an
external diagnostic system to carry out inspections on the memory cells in
a parallel fashion, and shrinks the total time period for the inspections.
Another background of the present invention is a parallel access. The
1-megabit to 4-megabit generation incorporates a 16-bit data interface
therein, and the next generation will incorporate a 32-bit data interface
and a 36-bit data interface for 32-bit data code with 2 parity-bits. Such
an increased parallel access is matched with the parallel processing on a
microprocessor, and enhances the processing speed, a space utility and
simplicity of the arrangement of peripheral circuits. Thus, the parallel
access is one of the recent tendencies of the data processing field.
A typical example of the dynamic random access memory device is illustrated
in FIG. 1 of the drawings, and comprises a plurality of addressable memory
cells arranged in a memory cell array 10, a plurality of read/write data
amplifier circuits 21, 22 , . . . and 2m coupled with the memory cell
array 10 for amplifying read-out data bits and write-in data bits in the
form of potential difference, a plurality of input/output data buffer
circuits 31, 32 , . . . and 3m for converting the read-out data bits and
the write-in data bits between the potential differences and a multi-bit
input/output data signal, a plurality of data line pairs 41, 42 , . . .
and 4m coupled between the read/write data amplifier circuits 21 to 2m and
the input/output data buffer circuits 31 to 3m, and a plurality of
input/output data pins 51, 52 , . . . and 5m coupled with the input/output
data buffer circuits 31 to 3m. In the next generation, m may be 16, 32 or
36.
A microprocessor (not shown) transfers m-bit data signal to the
input/output data pins 51 to 5m, and the input/output data buffer circuits
31 to 3m, simultaneously produce m potential differences on the data line
pairs 41 to 4m from the m-bit data signal. The m potential differences are
amplified by the read/write data amplifier circuits 21 to 2m, and are
transferred to the memory cell array 10 so that m memory cell sub-arrays
respectively store the m data bits.
When the microprocessor accesses data information indicated by the m data
bits, an addressing system (not shown) of the dynamic random access memory
device specifies an address of the memory cell array 10, and the m data
bits are concurrently read out from the m memory cell sub-arrays to the
read/write data amplifier circuits 21 to 2m. The m data bits in the form
of potential difference are amplified, and the potential differences are
propagated through the data line pairs 41 to 4m to the input/output data
buffer circuits 31 to 3m. The input/output data buffer circuits 31 to 3m,
produces an m-bit output data signal from the potential differences, and
delivers the m-bit output data signal from the input/output data pins 51
to 5m to the microprocessor.
Thus, the dynamic random access memory device is directly communicable with
the m-bit microprocessor, and the parallel access improves an access speed
per bit.
As described hereinbefore, the increased memory capacity prolongs the time
period for the inspections, and the parallel testing sequence is effective
against the prolonged time period. However, the parallel testing sequence
is available for the dynamic random access memory device as long as the
multi-bit interface thereof is equal in the number of pins to or less than
the interface of the diagnostic system. If the manufacturer enhances the
parallel access, the parallel testing sequence can not fully demonstrate
the ability. Of course, if new diagnostic systems are installed for every
generation, the parallel testing sequence is effective against the
prolonged time period. However, such a frequent renewal is very expensive.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a
semiconductor memory device which allows a parallel testing sequence to
fully demonstrate the ability without renewal of a diagnostic system.
To accomplish the object, the present invention proposes to internally
carry out a serial-to-parallel conversion.
In accordance with the present invention, there is provided a semiconductor
memory device selectively entering a standard mode and a diagnostic mode
of operation, comprising: a) a plurality of memory cell arrays each having
a plurality of addressable memory cells; b) an addressing system selecting
one of the plurality of addressable memory cells from each of the
plurality of memory cell arrays; c) a data propagation system having c-1)
a plurality of first data bus means associated with the plurality of
memory cell arrays, and respectively propagating data bits and test bits
from and to the plurality of memory cell arrays in both standard and
diagnostic modes of operation, c-2) a plurality of second data bus means
respectively connectable with the plurality of second data bus means, c-3)
a switching means operative to isolate the plurality of first data bus
means from the plurality of second data bus means in the diagnostic mode
and to transfer the data bits between the plurality of first data bus
means and the plurality of second data bus means in the standard mode, and
c-4) an input/output means operative to transfer the data bits in parallel
to the plurality of second data bus means in the standard mode and to
selectively transfer the test bits in serial to the plurality of second
data bus means; and d) a diagnostic system having d-1) a controller
responsive to external control signals for controlling a test sequence
carried out in the diagnostic mode, d-2) a write register coupled with
predetermined second data bus means supplied in serial with the test bits,
and storing the test bits, the test bits being supplied in parallel to the
plurality of first data bus means for writing the test bits into the
memory cells respectively selected from the plurality of memory cell
arrays in the diagnostic mode, and d-3) a comparator operative to compare
the test bits read out in parallel from the plurality of memory cell
arrays to the plurality of first data bus means with the test bits stored
in the write register in the diagnostic mode to see whether or not the
test bits on the plurality of first data bus means are consistent with the
test bits in the write register, and supplying a diagnostic signal
indicative of consistence or inconsistence to the predetermined second
data bus means for outputting the diagnostic signal through the
input/output means.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the semiconductor memory device according to
the present invention will be more clearly understood from the following
description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram showing the arrangement of the prior art dynamic
random access memory device;
FIG. 2 is a block diagram showing the arrangement of a dynamic random
access memory device according to the present invention;
FIG. 3 is a circuit diagram showing the circuit arrangement of a switching
circuit incorporated in the dynamic random access memory device according
to the present invention;
FIG. 4 is a circuit diagram showing the circuit arrangement of a controller
incorporated in the dynamic random access memory device according to the
present invention;
FIG. 5 is a circuit diagram showing the circuit arrangement of a shift
register incorporated in the dynamic random access memory device according
to the present invention;
FIG. 6 is a circuit diagram showing the circuit arrangement of a flip-flop
circuit forming a part of the shift register.
FIG. 7 is a circuit diagram showing the circuit arrangement of a comparator
incorporated in the dynamic random access memory device according to the
present invention;
FIG. 8 is a timing chart showing a test sequence in a diagnostic mode for
the dynamic random access memory device according to the present
invention; and
FIG. 9 is a circuit diagram showing the circuit arrangement of a shift
register incorporated in another dynamic random access memory device
according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
Referring to FIG. 2 of the drawings, a dynamic random access memory device
is fabricated on a single semiconductor chip 100, and largely comprises a
memory cell array 110, an addressing system 120, a data propagation system
130 and a diagnostic system 140. Although other systems are further
incorporated in the dynamic random access memory device, FIG. 1 does not
show them, because they are less important for understanding the present
invention.
Upon completion of the fabrication, the dynamic random access memory device
is subjected to various inspections through testing sequences under the
control of the diagnostic system 140. One of the testing sequences is
available for checking the memory cell array 110 to see whether or not a
defective memory cell is incorporated in the memory cell array 110.
Another testing sequence is used for checking the data holding
characteristics of the memory cell array 110, and a refreshing sequence is
checked through yet another testing sequence.
After installation of the dynamic random access memory device in an
electronic system, m-bit data are written into the memory cell array 110
through a write-in sequence, and the m-bit data are read out therefrom
through a read-out sequence. The write-in sequence and the read-out
sequence are carried out in a write-in mode and a read-out mode, and the
write-in mode and the read-out mode form a standard mode of operation.
The memory cell array 110 is broken down into m memory cell sub-arrays 111,
112 , . . . and 11m, and each of the memory cell sub-arrays 111 to 11m is
implemented by memory cells respectively represented by small circles. A
plurality of word lines WL1 to WLi are shared between the memory cell
sub-arrays 111 to 11m, and are coupled with the rows of memory cells of
the memory cell sub-arrays 111 to 11m for making the rows of memory cells
selectively accessible. A plurality of bit line pairs BL11 to BL1j, BL21
to BL2j , . . . and BLm1 to BLmj are associated with the columns of memory
cells of the memory cell sub-arrays 111 to 11m, and propagate data bits in
the form of potential difference to and from the accessible rows of memory
cells.
The addressing system 120 comprises a row address decoder/word line driver
unit 121 responsive to row address predecoded signals and a column address
decoder/column selector unit 122 responsive to column address predecoded
signals. The row address decoder/word line driver unit 121 selectively
drives the word lines WL1 to WLi, and couples the memory cells associated
therewith with the bit line pairs BL11 to BLmj. The column address
decoder/column selector unit 122 selects one of the bit line pairs from
each bit line pair group BL11/BL1j, BL21/BL2j . . . or BLm1/BLmj, and the
data bits are transferred between the selected bit line pairs and the data
propagation system 130.
The data propagation system 130 comprises a plurality of first data line
pairs 141, 142 , . . . and 14m, a plurality of read/write data amplifier
circuits 151, 152 . . . and 15m coupled with the first data line pairs 141
to 14m, a plurality of second data line pairs 161, 162 . . . and 16m, a
plurality of switching circuits 171, 172 , . . . and 17m coupled between
the first data line pairs 141 to 14m and the second data line pairs 161 to
16m, and a plurality of input/output data buffer circuits 181, 182 . . .
and 18m coupled between the second data line pairs 181 to 18m and
input/output data pins 191, 192 , . . . and 19m.
Potential differences indicative of the data bits on the first data line
pairs 141 to 14m are increased in magnitude by the read/write data
amplifier circuits 151 to 15m, and are propagated on the first data line
pairs 141 to 14m between the column address decoder/column selector unit
122 and the transfer gates 171 to 17m.
All of the switching circuits 171 to 17m are similarly arranged, and the
switching circuit 171 is, by way of example, illustrated in FIG. 3. The
switching circuit 171 comprises a pair of transfer gates TG1, i.e.,
parallel combinations of p-channel enhancement type switching transistors
and n-channel enhancement type switching transistors coupled in parallel
between the first data line pair 141 and the second data line pair 161, an
inverter INV1 for producing the complementary signal CCL1 of a first test
control signal CL1, and a pair of memory loops ML1 coupled with the first
data line pair 141. The first test control signal CL1 and the
complementary signal thereof CCL1 are supplied to the pair of transfer
gates TG1 so that the first data line pair 141 is conducted with or
blocked from the second data line pair 161. The pair of memory loops ML1
is implemented by two pairs of inverters, and the output node of one of
the inverters of each pair is coupled with the input node of the other of
the inverters. Therefore, the potential difference on the first data line
pair 141 is stored in the two pairs of inverters. In summary, all of the
switching circuits 171 to 17m are responsive to the first control signal
CL1 from the diagnostic system 140 for coupling the first data line pairs
141 to 14m with the second data line pairs 161 to 16m, and the potential
differences on the first data line pairs 141 to 14m are temporally stored
in the switching circuits 171 to 17m, respectively.
Turning back to FIG. 2, while the dynamic random access memory device is
staying in the write-in mode for the write-in sequence, input data signals
indicative of an m-bit data is transferred from the input/output data pins
191 to 19m, and the input/output data buffer circuits 181 to 18m produces
potential differences on the second data line pairs 161 to 16m from the
input data signals. On the other hand, while the read-out mode for the
read-out sequence is being established in the dynamic random access memory
device, the input/output data buffer circuits 181 to 18m produces output
data signals indicative of the m-bit data from the potential differences
on the second data line pairs 161 to 16m, and the output data signals are
supplied from the input/output data buffer circuits 181 to 18m to the
input/output data pins 191 to 19m.
As will be described in conjunction with the diagnostic system 140, while
the dynamic random access memory device is being subjected to an
inspection of the memory cell array 110 through a testing sequence, an
m-bit test data bits are supplied in serial from an external diagnostic
system (not shown) to the input/output data pin 191, and the associated
input/output data buffer circuit 181 sequentially produces potential
differences.
The diagnostic system 140 comprises a controller 141, a shift register 142
and a comparator 143. The controller 141 is responsive to external test
control signals applied to control pins WEB, RASB and CASB as well as to
address pins An and A(n+1), and produces second and third test control
signals CL2 and CL3 as well as the first test control signal CL1. The
external test control signal at the address pin An exceeds the positive
power voltage level Vdd in the diagnostic mode, and the address pin A(n+1)
over the positive power voltage level releases the dynamic random access
memory device from the diagnostic mode.
The shift register 142 is reset with the first test control signal CL1, and
sequentially shifts the m-bit test data from stage to stage in response to
the second test control signal CL2. When the third test control signal CL3
is changed to active level, the shift register 142 supplies the m-bit test
data in parallel to the first data line pairs 141 to 14m.
The comparator 143 is enabled with the first test control signal CL1, and
compares the m-bit test data on the first data line pairs 141 to 14m with
the m-bit test data in the shift register 142 to see whether or not the
m-bit test data are consistent with each other. The comparator 143 is
further responsive to the third test control signal CL3 for supplying a
diagnostic signal DG indicative of consistence or inconsistence between
the m-bit test data to the second data line pair 161. The diagnostic
signal DG is supplied to the input/output data buffer 191, and reports the
diagnosis to the external diagnostic system (not shown).
Turning to FIG. 4 of the drawings, the controller 141 comprises a mode
discriminating circuit 141a, an excess voltage discriminating circuit 141b
and a signal producing circuit 141c. The mode discriminating circuit 141a
monitors the control signal pins WEB, RASB and CASB, and produces control
signals CL11, CL12 and CL13 when the external control signals at the
control signal pins WEB, RASB and CASB form a predetermined pattern
indicative of the diagnostic mode. The predetermined pattern is referred
to as "Write-CAS-Before-RAS Timing", and the control signals at the signal
pins WEB and CASB go down before the step-down of the control signal at
the signal pin RASB for the diagnostic mode. When the excess voltage
discriminating circuit 141b acknowledges the voltage level over the
positive power voltage level, the discriminating circuits 141a and 141b
allows the dynamic random access memory device to enter the diagnostic
mode, and the signal producing circuit 141c are responsive to the external
test control signal at the control signal pin WEB and the control signals
CL11 to CL13 for produces the first, second and third test control signals
CL1 to CL3 at appropriate timings. If the address pin A(n+1) goes up over
the positive power voltage level Vdd, the first test control signal CL1
goes down to the inactive low level.
Turning to FIG. 5 of the drawings, the shift register 142 comprises a
series of master-slave type flip-flop circuits FF1 to FFm and three-state
inverters 1421, 1422 . . . and 142m enabled with the third test control
signal CL3. The flip-flop circuits FF1 to FFm are arranged as shown in
FIG. 6, and each of the flip-flop circuits FF1 to FFm latches the voltage
level on one of the data lines of the second data line pair 161 or at the
output node Q of the previous stage in synchronism with the second test
control signal CL2 at the clock node C. The voltage level at the input
node D is stored in a memory loop ML2 consisting of an inverter and a NAND
gate, and is transfers to a memory loop ML3 also consisting of an inverter
and a NAND gate in synchronism with the next second control signal CL2.
The voltage level thus stored in the memory loop ML3 is output from the
output node Q through an associated signal line Q1, Q2 . . . or Qm to a
first input node of the comparator 143 at all times. However, the
complementary voltage signal is controlled with the third test control
signal, and is output from the output node CQ directly to and through the
three-state inverter 1421, 1422 or 142m to the associated first data line
pair in response to the third test control signal CL3 at the output enable
node E. The voltage level stored in the memory loop ML3 is canceled with
the first test control signal CL1 at the reset node R.
FIG. 7 illustrates the circuit arrangement of the comparator 143, showing
the first input nodes respectively connected with the signal lines Q1 to
Qm, and second input nodes respectively connected with the first data
lines respectively corresponding to the signal lines Q1 to Qm. Namely, the
comparator 143 has a plurality of exclusive-OR gates EX1 to EXm each
coupled with one of the signal lines Q1 to Qm and the corresponding first
data line of one of the first data line pairs 141 to 14m, and a NOR gate
NR1 checks the output signals of the exclusive-OR gates EX1 to EXm to see
whether or not at least one test bit is inconsistent with the
corresponding test bit. While the m-bit test data on the first data line
pairs 141 to 14m is being consistent with the m-bit test data in the shift
register 142, the NOR gate produces the output signal of logic "1" level
equivalent to the high voltage level, and inverters INV2 and INV3 supply
the diagnostic signal DG in the form of potential difference to the second
data line pair 161 in response to an enable signal ENB1 produced in the
concurrent presence of the first and third test control signal CL1 and
CL3.
Description is made on the test sequence of the memory cell array 110 with
reference to FIG. 8 of the drawings. The external test control signals at
the pins CASB and WEB go down at time t21, and the external test control
signal at the pin RASB goes down at time t22. The address pin Pn is lifted
over the positive power voltage level Vdd, and the mode discriminating
circuit 141a acknowledges the diagnostic mode. Therefore, the dynamic
random access memory device enters the diagnostic mode in phase 1, and the
first test control signal CL1 goes up at time t23. With the first test
control signal CL1 of the high voltage level, all of the flip-flop
circuits FF1 to FFm are reset, and the shift register enters ready state
for storing test data bits. Moreover, the first test control signal CL1
causes the switching circuits 171 to 17m to isolates the first data line
pairs 141 to 14m from the second data line pairs 161 to 16m.
The test data bits are serially supplied from the external diagnostic
system to the input/output data pin 191, and are sequentially transferred
from the second data line pair 161 to the input node D of the flip-flop
circuit FF1. The test data bits are shifted from the flip-flop circuit FF1
to the flip-flop circuit FFm in synchronism with the second test control
signal CL2 through phases 2 and 3, and an m-bit test data are finally
stored in the shift register 142.
Though not shown in FIG. 8, when the m-bit test data is stored in the shift
register 142, the third test control signal is changed to active level,
and the flip-flop circuits FF1 to FFm concurrently supply the m-bit test
data to the first data line pairs 141 to 14m. The m-bit test data is
written into the memory cells of the memory cell sub-arrays 111 to 11m
assigned the addresses identical with the addresses represented by the
address signals at the address pins through phases 4 and 5.
The m-bit test data is read out from the memory cell sub-arrays 111 to 11m,
and is transferred to the first data line pairs 141 to 14m. The comparator
143 compares the m-bit test data on the first data line pairs 141 to 14m
with the m-bit test data in the shift register 142, and supplies the
diagnostic signal DG through the second data line pair 161 and the
input/output data buffer circuit 181 to the data pin 191 in phase 6.
The write-in cycle and read-out/comparing cycle are repeated, and the
diagnostic system 140 diagnoses the memory cell array 110. Upon completion
of the diagnosis, the external diagnostic syst | | |
