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Document Number
US Patent 5408142
Issued Date
April 18, 1995
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Abstract
A hold circuit has a purpose to provide a hold circuit capable of controlling a hold error of an analog hold in the minimum during transferring. A hold circuit keeps a voltage signal, whose voltage level is compensated by operational amplifiers Amp.sub.1 and Amp.sub.2, at capacitances C.sub.1 and C.sub.2 by two steps, and holding and transferring of voltage data is performed at the different timing. The accuracy is compensated, as well.
Drawing
Hold circuit - US Patent 5408142 Drawing
Drawing from US Patent 5408142
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Number of Claims:
1
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Owner
Yozan Inc. (Tokyo,JP)
Published
April 18, 1995
Application Number
08/156,766
Filed
November 24, 1993
US Classification
327/91   327/94
Int'l Classification
G11C   27/02   (20060101)   G11C   27/00   (20060101)  
Assistant Examiner
Attorney/Law Firm
Priority Data
Nov 25, 1992 [JP] 4-339722
USPTO Field of Search
307/520   307/521   307/352   307/353   328/151   328/167  
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Description
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