Semiconductor integrated circuits with power reduction mechanism

Claims

What is claimed is:

1. A semiconductor integrated circuit operating at an operating voltage of which the absolute value is about 2.5 V or below, comprising:

a plurality of circuit blocks;

at least two circuit terminals through which a desired operating voltage of said circuit blocks is applied; and

current controlling means provided between each of said circuit blocks and at least one of said circuit terminals,

wherein each of said plurality of circuit blocks includes an MOS transistor in which substantially a leakage current flows between a drain and a source of said MOS transistor even under a condition that a gate voltage is equal to a source voltage in said MOS transistor,

wherein said current controlling means controls said leakage current in each of said circuit blocks, and

wherein a certain one of said circuit blocks logically operates during a period including a part of the period in which said leakage current in at least another one of said circuit blocks is controlled by said current controlling means, and said leakage current is controlled by said current controlling means during a period including a part of the period in which at least another one said circuit blocks logically operates.

2. A semiconductor integrated circuit according to claim 1,

wherein said circuit blocks are formed of CMOS logic circuits,

wherein at least another one of said circuit blocks does not logically operate during a part of the period in which said certain one of said circuit blocks logically operates, and

wherein when said current controlling means is short-circuited, the leakage current in at least one of said circuit blocks which does not logically operate during a part of the period in which said certain one of said circuit blocks logically operates is equivalent to or larger than a current dissipation of at least one of said circuit blocks which logically operates.

3. A semiconductor integrated circuit according to claim 1,

wherein a circuit terminal which is connected to said current controlling means and circuit block is connected to the source of said MOS transistor within said circuit block,

wherein the absolute value of the difference between a gate-source voltage of said MOS transistor and a constant current threshold voltage of said MOS transistor is about 0.4 V or above during the period in which said current controlling means controls said leakage current, and

wherein said constant current threshold voltage is the gate-source voltage at which a drain current of 10 nA flows at room temperature when the ratio between an effective gate width and an effective gate length is 30.

4. A semiconductor integrated circuit according to claim 3, further comprising:

means for applying a constant voltage independently of the state of said current controlling means,

wherein the voltage at a circuit terminal connected to said current controlling means and said circuit blocks is kept constant by said constant voltage applying means during the period in which said current controlling means control said leakage current.

5. A semiconductor integrated circuit according to claim 1,

wherein said plurality of circuit blocks are of a similar configuration,

wherein said current controlling means are provided between said circuit blocks and said circuit terminals through which a first operating voltage is applied as a desired operating voltage to said circuit blocks during a desired period of time, and

wherein at least one of said current controlling means is selected so that said first operating voltage is applied through said current controlling means to the corresponding circuit block.

6. A semiconductor integrated circuit according to claim 5,

wherein said current controlling means are provided between said circuit blocks and said circuit terminals through which a second operating voltage is applied as a desired operating voltage to said circuit blocks during a desired period of time, and

wherein at least one of said current controlling means is selected so that said second operating voltage is applied through said current controlling means to the corresponding circuit block.

7. A semiconductor integrated circuit according to claim 5, further comprising:

a plurality of column lines and a plurality of row lines for selecting said current controlling means,

wherein said current controlling means are arranged according to a matrix shape of said plurality of column lines and said plurality of row lines.

8. A semiconductor integrated circuit according to claim 5, further comprising:

a circuit terminal at which said first operating voltage is applied during a desired period of time;

a power line to which said plurality of current controlling means are connected; and

second current controlling means provided between said circuit terminal at which said first operating voltage is applied during a desired period of time and said power line to which said plurality of current controlling means are connected,

wherein said first operating voltage is applied through said second current controlling means to said power line, and one of said current controlling means connected to said circuit blocks is selected so that said first operating voltage is applied through said current controlling means to the corresponding circuit block.

9. A semiconductor integrated circuit according to claim 8, further comprising:

a circuit terminal to which said first operating voltage is applied during a desired period of time;

a second power line to which said plurality of second current controlling means are connected; and

third current controlling means provided between said circuit terminal to which said first operating voltage is applied during a desired period of time and said second power line to which said plurality of second current controlling means are connected,

wherein said power line is formed of a plurality of power lines, said second current controlling means is formed of a plurality of current controlling means, and

wherein said first operating voltage is applied through said third current controlling means to said second power line, and ones of said second current controlling means and said current controlling means connected to said circuit blocks are selected so that said first operating voltage is applied through said second current controlling means and said current controlling means to the corresponding circuit block.

10. A semiconductor integrated circuit according to claim 1,

wherein a circuit block selecting signal for controlling said current controlling means is generated according to at least part of an address signal.

11. A semiconductor integrated circuit chip operating at an operating voltage of 2.5 V or below, comprising:

a first terminal at which a first operating potential is applied;

a second terminal at which a second operating potential is applied;

a first circuit block coupled between said first terminal and said second terminal; and

a second circuit block coupled between said first terminal and said second terminal;

wherein said first circuit block permits an active current to flow between said first terminal and an output terminal when said first circuit responds to an input signal to its input terminal to produce an output signal at its output terminal,

wherein said second circuit block includes a plurality of subcircuit blocks each of which includes a MOS transistor having its source connected to a first node and its gate connected to the input terminal and a load having one end connected to the drain of said MOS transistor and the other end connected to a second node,

wherein the MOS transistor of each of said plurality of subcircuit blocks causes a subthreshold current in its source-drain path when the gate-source voltage is substantially 0,

wherein said plurality of first nodes of said plurality of subcircuit blocks are coupled through a plurality of switching elements to said first terminal, and said plurality of second nodes of said plurality of subcircuit blocks are coupled to said second terminal,

wherein the constants of said plurality of switching elements are set so that the leak currents of said plurality of switching elements in their off-state are smaller than the subthreshold current of the MOS transistor of the corresponding one of said plurality of subcircuit blocks; and

wherein the current dissipation in each of said plurality of subcircuit blocks of said second circuit block is limited to a leak current value of the corresponding one of said plurality of switching elements by turning off said plurality of switching elements so that the sum of the dissipation current in said plurality of subcircuit blocks is made smaller than said active current of said first circuit block.

12. A semiconductor integrated circuit chip according to claim 11,

wherein each of said plurality of subcircuit blocks of said second circuit block causes an active current to flow between said first terminal and the output terminal of each of said subcircuit blocks when said second circuit block responds to an input signal to its input terminal to produce an output signal at its output,

wherein each of the plurality of subcircuit blocks of said first circuit block includes a MOS transistor having its source connected to said first node and its gate connected to said input terminal, and a load having its one end connected to the drain of said MOS transistor and the other end connected to said second node,

wherein said MOS transistor of each of said plurality of subcircuit blocks of said first circuit block causes the subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,

wherein said plurality of first nodes of said plurality of subcircuit blocks of said first circuit block are coupled through a plurality of switching elements to said first terminal, and said plurality of second nodes of said plurality of subcircuit blocks of said first circuit block are coupled to said second terminal,

wherein the constants of said plurality of switching elements of said first circuit block are fixed so that the leak currents of said plurality of switching elements of said first circuit block in their off-state is smaller than the threshold current of the MOS transistor of the corresponding one of said plurality of subcircuit blocks of said first circuit block, and

wherein said plurality of subcircuit blocks of said second circuit block are made active by turning on said plurality of switching elements of said second circuit block, and the current dissipation in each of said plurality of subcircuit blocks of said first circuit block is limited to a leak current value of the corresponding one of said plurality of switching elements so that the sum of the dissipation currents in said plurality of subcircuit blocks is made smaller than that of the active currents of said second circuit block.

13. A semiconductor integrated circuit according to claim 11,

wherein the MOS transistor of each of said plurality of subcircuit blocks is a p-channel MOS transistor, and

wherein the load for each of said plurality of subcircuit blocks is an n-channel MOS transistor.

14. A semiconductor integrated circuit according to claim 12,

wherein the MOS transistor of each of said plurality of subcircuit blocks of said first circuit block is a p-channel MOS transistor,

wherein the load of each of said plurality of subcircuit blocks of said first circuit block is an n-channel MOS transistor,

wherein the MOS transistor of each of said subcircuit blocks of said second circuit block is a p-channel MOS transistor, and

wherein the load for each of said plurality of subcircuit blocks of said second circuit block is an n-channel MOS transistor.

15. A semiconductor integrated circuit according to claim 14,

wherein each of said plurality of switching elements of said first circuit block is a MOS transistor, and the absolute value of the constant current threshold voltage is larger than that of the MOS transistor of the corresponding one of said plurality of subcircuit blocks of said first circuit block, and

wherein each of said plurality of switching elements of said second circuit block is a MOS transistor, and the absolute value of the constant current threshold voltage is larger than that of the MOS transistor of the corresponding one of said plurality of subcircuit blocks of said second circuit block.

16. A semiconductor integrated circuit according to claim 11,

wherein each of said plurality of switching elements is a MOS transistor, and the source-drain path thereof makes a current path between said first node and said first terminal.

17. A semiconductor integrated circuit according to claim 11, further comprising:

potential setting means for setting said first node of each of said plurality of subcircuit blocks at a predetermined potential.

18. A semiconductor integrated circuit according to claim 13, further comprising:

a memory array formed of a large number of memory cells,

wherein said plurality of subcircuit blocks are drivers for driving word lines which select a desired one of said many memory cells.

19. A semiconductor integrated circuit according to claim 13, further comprising:

a memory array formed of a large number of memory cells,

wherein said plurality of subcircuit blocks are decoders for decoding an address signal which is used for selecting a desired one of said many memory cells.

20. A semiconductor integrated circuit according to claim 13, further comprising:

a memory array formed of a large number of memory cells; and

sense amplifiers for detecting a read signal to a desired one of said many memory cells,

wherein said plurality of subcircuit blocks are sense amplifier driving circuits which drive said sense amplifiers.

21. A semiconductor integrated circuit chip comprising:

a plurality of first circuit blocks;

a plurality of first switching elements;

a first operation potential power line coupled common to said plurality of said first switching elements; and

a second switching element coupled between said first operation potential power line and a first operation potential point,

wherein each of a plurality of first nodes of said plurality of first circuit block is coupled to said first operation potential power line through the corresponding one of said plurality of first switching elements,

wherein a plurality of second nodes of said plurality of first circuit blocks are coupled to a second operation potential power line,

wherein each of said plurality of first circuit blocks includes a MOS transistor having its source connected to the corresponding one of said first nodes and its gate connected to the input terminal, and a load having its one end connected to the drain of said MOS transistor and the other end connected to said second nodes,

wherein said MOS transistor of each of said plurality of first circuit blocks causes a subthreshold current to flow in its source-drain path when the gate-source voltage is substantially 0,

wherein constants of said plurality of first switching elements are set so that the leak current in the off-state of each of said plurality of first switching elements is smaller than the subthreshold current of the MOS transistor of the corresponding one of said plurality of first circuit blocks,

wherein the current dissipation of each of said plurality of first circuit blocks is limited to a leak current value of a corresponding one of said plurality of first switching elements by turning off said plurality of first switching elements, and

wherein a constant of said second switching element is set so that the leak current of said second switching element in its off-state is smaller than the sum of the leak currents of said plurality of first switching elements, and thus the sum of dissipation currents in said plurality of first circuit blocks is limited to said leak current value of said second switching element.

22. A semiconductor integrated circuit chip according to claim 21, further comprising:

a plurality of second circuit blocks;

a plurality of third switching elements;

a third operation potential line coupled common to said plurality of third switching elements;

a fourth switching element coupled between said third operation potential line and said second switching elements;

a fourth operation potential line coupled common to said second switching elements and said fourth switching element; and

a fifth switching element coupled between said fourth operation potential line and said first operation potential point,

wherein each of a plurality of third nodes of said plurality of second circuit blocks is coupled to said third operation potential line through a corresponding one of said plurality of third switching elements,

wherein a plurality of four nodes of said plurality of second circuit blocks are coupled to said second operation potential line,

wherein each of said plurality of second circuit blocks includes a MOS transistor having its source connected to a corresponding one of said third nodes and its gate connected to the input terminal, and a load having its one end connected to the drain of said MOS transistor and the other end connected to a corresponding one of said fourth nodes,

wherein the MOS transistor of each of said plurality of second circuit blocks causes a subthreshold current to flow in the source-drain path when the gate-source voltage is substantially 0,

wherein constants of said plurality of third switching elements are set so that the leak current of each of said plurality of third switching elements in its off-state is smaller than the subthreshold current of the MOS transistor of a corresponding one of said plurality of second circuit blocks,

wherein the current dissipation in each of said plurality of second circuit blocks is limited to a leak current value of a corresponding one of said plurality of third switching elements by turning off said plurality of third switching elements,

wherein the constant of said fourth switching element is set so that the leak current of the fourth switching element in its off-state is smaller than the sum of the leak currents of said plurality of third switching elements, with the result that the sum of the dissipation currents of said plurality of second circuit blocks is limited to said leak current value of said fourth switching element, and

wherein the constant of said fifth switching element is set so that the sum of the dissipation currents of said plurality of first circuit blocks and the dissipation currents of said plurality of second circuit blocks is limited to a leak current value of said fifth switching element by turning off said fifth switching element.

23. A semiconductor integrated circuit chip according to claim 21,

wherein the MOS transistor of each of said plurality of first circuit blocks is a p-channel MOS transistor, and

wherein the load of each of said plurality of first circuit blocks is an n-channel MOS transistor.

24. A semiconductor integrated circuit chip according to claim 22,

wherein the MOS transistor of each of said plurality of first circuit blocks is a p-channel MOS transistor,

wherein the load of each of said plurality of first circuit blocks is an n-channel MOS transistor,

wherein the MOS transistor of each of said plurality of first circuit blocks of said second circuit block is a p-channel MOS transistor, and

wherein the load of each of said plurality of first circuit blocks of said second circuit block is an n-channel MOS transistor.

25. A semiconductor integrated circuit chip according to claim 24,

wherein each of said plurality of first switching elements is a MOS transistor, and

wherein said second switching elements are MOS transistors, and the absolute value of the constant current threshold voltage is larger than that of the MOS transistor of each of said plurality of first switching elements.

26. A semiconductor integrated circuit chip according to claim 21,

wherein each of said plurality of first switching elements is a MOS transistor, and the source-drain path makes a current path between a corresponding one of said first nodes and said first operation potential point.

27. A semiconductor integrated circuit chip according to claim 21, further comprising:

potential setting means for setting the first node of each of said plurality of first circuit blocks at a predetermined potential.

28. A semiconductor integrated circuit chip according to claim 23, further comprising:

a memory array which is formed of a large number of memory cells,

wherein said plurality of first circuit blocks are word drivers for driving word lines which are used to select a desired one of said many memory cells.

29. A semiconductor integrated circuit chip according to claim 23, further comprising:

a memory array which is formed of a large number of memory cells,

wherein said plurality of first circuit blocks are decoders for decoding an address signal which is used to select a desired one of said many memory cells.

30. A semiconductor integrated circuit chip according to claim 23, further comprising:

a memory array which is formed of a large number of memory cells; and

a sense amplifier for detecting a read signal to a desired one of said many memory cells,

wherein said plurality of first circuit blocks are sense amplifier driving circuits which drive said sense amplifier.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is relevant to U.S. patent application Ser. No. 07/972,545 filed on Nov. 6, 1992 in the names of T. Kawahara et al., and U.S. patent application Ser. No. 08/045,792 filed on Apr. 14, 1993 in the names of M. Horiguchi et al., the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION AND SUMMARY OF THE INVENTION

The present invention relates to semiconductor integrated circuits suitable for high-speed and low-power operation, and particularly to a semiconductor integrated circuit formed of small-geometry MOS transistors.

The semiconductor integrated circuits have so far been developed toward the scaling down of MOS transistors. However, since the minute structure of MOS transistors reduces their breakdown voltage the more as the degree of the minuteness becomes greater, the operating voltage of the small-geometry MOS transistors must be lowered, as described in International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, pp. 188-192 (May 1989). The operating voltages of the semiconductors used in the battery-operated portable electronic apparatus must be further reduced for their low power consumption.

In order to maintain their high-speed operation under reduced operating voltages, it is also necessary to decrease the threshold voltage (V.sub.T) of the MOS transistors. The reason for this is that the operating speed is governed by the effective gate voltage of the MOS transistors, or the remainder of the subtraction of V.sub.T from the operating voltage, or that it increased with the increase of this effective gate voltage. For example, in a 16-gigabit DRAM which is expected to have 0.15 .mu.m or below in effective channel length, about 4 nm in gate oxide film thickness, 1 V in standard operating voltage within chip and about 1.75 V in boosted word line voltage, the constant current threshold voltage of transistors is calculated to be -0.04 V. The term, constant current threshold voltage of transistors is the gate-source voltage under the conditions of a ratio, 30 of effective channel width to effective channel length and a drain current of 10 nA. In this case, the substrate-source voltage is 0, the junction temperature is 25.degree. and a typical condition is assumed. For simplicity, the threshold voltage of p-channel MOS transistors is shown with the opposite sign.

When V.sub.T is reduced, however, the drain current cannot be completely cut off due to the drain current characteristic of the subthreshold region of MOS transistors. This problem will be described with reference to FIG. 22A which shows a conventional CMOS inverter. When the input signal IN to the CMOS inverter has a low level (=V.sub.ss), the n-channel MOS transistor M.sub.N is turned off. When the input signal IN has a high level (=V.sub.cc), the p-channel MOS transistor M.sub.P is turned off. Therefore, in either case, from the ideal point of view, no current flows from the high source voltage V.sub.cc through the CMOS inverter to the low source voltage V.sub.ss, or ground potential.

When the threshold voltage V.sub.T of the MOS transistors is reduced, however, the subthreshold characteristic cannot be neglected. As shown in FIG. 22B, the drain current I.sub.DS in the subthreshold region is proportional to the exponential function of the gate-source voltage V.sub.GS, and expressed by the following equation (1). ##EQU1## where W is the channel width of the MOS transistors, I.sub.0 and W.sub.0 are the current value and channel width used when V.sub.T is defined, and S is the subthreshold swing (the reciprocal of the gradient of the V.sub.GS -log I.sub.DS characteristic). Thus, the drain current in the subthreshold region (, or the subthreshold current) flows even under V.sub.GS =0. The subthreshold current can be expressed by the following equation (2). ##EQU2##

When the input signal to the CMOS inverter shown in FIG. 22A is not changed, or when it is not operated, the off-state transistor of the CMOS inverter is at V.sub.GS =0. Therefore, the current flowing from the high source voltage V.sub.cc through the CMOS inverter to the low source voltage V.sub.ss, or ground potential is the current I.sub.L which flows in the off-state transistor of the CMOS inverter.

This subthreshold current, as shown in FIG. 22B, is exponentially increased from I.sub.L to I.sub.L ' when the threshold voltage is decreased from V.sub.T to V.sub.T '.

Although the increase of V.sub.T or the reduction of S reduce the subthreshold current as will be seen from the equation (2), the increase of V.sub.T, incurs the reduction of the speed due to the decrease of the effective gate voltage, while the reduction of S will be difficult for the following reason.

The subthreshold swing S can be expressed by using the capacitance C.sub.OX of the gate dielectric and the capacitance C.sub.D of the depletion region under the gate as in the following equation (3). ##EQU3## where k is the Boltzmann constant, T is the absolute temperature and q is the elementary charge. As will be seen from the equation (3), the condition of S.gtoreq.kTl.sub.n 10/q is limited for any values of C.sub.OX and C.sub.D. Thus, it is difficult for S to be reduced to 60 mV or below at room temperature (about 300 k).

Thus, in the semiconductor integrated circuit including MOS transistors with a low value of V.sub.T the amount of DC current consumption of non-operating circuits is remarkably increased because of the phenomenon mentioned above when the operating voltage becomes low (for example, 2 V or 2.5 V). Particularly, upon high-temperature operation, S becomes large, making this problem further serious. In the downsizing age of future computers and so on, when reduction of power is important, the increase of the subthreshold current becomes a substantial problem.

This problem will be further considered taking a memory, which is a typical semiconductor integrated circuit, as an example. The memory generally includes, as shown in FIG. 23, a memory array MA, an X decoder (XDEC) and word driver (WD) for selecting and driving a row line (word line W) for the selection of a memory cell MC within the memory array MA, a sense amplifier (SA) for amplifying the signal on a column line (data line D), a sense amplifier driving circuit (SAD) for driving the sense amplifier, a Y decoder (YDEC) for selecting a column line, and a peripheral circuit (PR) for controlling these circuits. The main parts of these circuits are designed based on the CMOS inverter logic circuit mentioned above.

When the threshold voltage V.sub.T of transistors (hereinafter, for simplicity the absolute values of the threshold voltages of the p-channel and n-channel MOS transistors are assumed to be equal to V.sub.T) is low, a subthreshold current, that is a current flowing in the source-drain path of the MOS transistors of which the V.sub.GS, is substantially 0.

Therefore, the sum of the subthreshold currents becomes particularly great in the circuits having a large number of MOS transistors, such as decoders, drivers or the peripheral circuit section.

For example, in the decoders or drivers, a small number of particular circuits are selected from a large number of circuits of the same type by the address signal, and driven. FIG. 24 shows an example of the conventional word driver for DRAM.

If the threshold value V.sub.T of the MOS transistors of all CMOS drivers #1-#r is large enough, the subthreshold current, that is a current flowing in the source-drain paths of the MOS transistors of substantially zero V.sub.GS, is substantially zero in each of a large number of nonselected circuits. In general, the number of the decoder and driver is increased with the increase of the storage capacity of the memory. However, even though the storage capacity is increased, the total current is not increased unless the subthreshold current flows in the circuits that are not selected in the decoders or drivers.

If the threshold voltage V.sub.T is decreased as mentioned above, however, the subthreshold current increases in proportion to the number of nonselected circuits.

In the prior art, when the chip is in the standby mode (nonselected state), almost all the circuits within the chip are turned off so that the power dissipation can be reduced as much as possible. However, it is not possible any more to reduce the power current dissipation even in the standby mode because the subthreshold current flows when the MOS transistors are highly scalled down.

When V.sub.T is small, the subthreshold current that is a current flowing in the source-drain paths of the MOS transistors with V.sub.GS being substantially zero, causes a trouble not only in the standby mode but also in the operating mode. Generally the current I.sub.ACT flowing when the chip is in the active mode and the current I.sub.STB flowing when the chip is in the standby mode are respectively expressed by

I.sub.ACT .apprxeq.I.sub.OP +I.sub.DC,

and

I.sub.STB .apprxeq.I.sub.DC,

where I.sub.OP is the charging and discharging current to and from the load capacitance of the circuits within the chip, and given by

I.sub.OP =C.sub.TOT .multidot.V.sub.cc .multidot.f

in which V.sub.cc is the operating voltage of the chip, C.sub.TOT is the total load capacitance of the circuits within the chip, and f is the operating frequency. In addition, I.sub.DC is the subthreshold current given above. The subthreshold current is exponentially increased with the decrease of V.sub.T as indicated by the equation (2).

So far, since V.sub.cc is large and V.sub.T is also large enough, the condition of

I.sub.OP >I.sub.DC

can be satisfied. Therefore, the following equations can be given:

I.sub.ACT .apprxeq.I.sub.OP,

I.sub.STB .apprxeq.I.sub.DC

In this case, I.sub.DC is substantially zero. Thus, for I.sub.ACT, only the increase of I.sub.OP has been considered to cause a problem.

However, since I.sub.DC is increased with the decrease of V.sub.cc and V.sub.T, finally the following condition is satisfied:

I.sub.OP .ltoreq.I.sub.DC

In addition, it is found that if V.sub.cc and V.sub.T are decreased, the following condition is given:

I.sub.OP <I.sub.DC

In this case, the expressions of

I.sub.ACT .apprxeq.I.sub.DC,

I.sub.STB .apprxeq.I.sub.DC

can be given. Therefore, the increase of the subthreshold current I.sub.DC also becomes a problem to the current I.sub.ACT which flows when the chip is operating.

FIG. 25 shows an example of the results predicted for the current dissipation in the DRAM. This prediction is made at a junction temperature of 75.degree. C. with typical conditions. From FIG. 25, it will be seen that the I.sub.DC of the 4-G bit DRAM exceeds I.sub.OP when its operating voltage is assumed to be 1.2 V.

If we considers the worst conditions, the subthreshold current I.sub.DC causes a problem even when the effective channel length, gate oxide film thickness and operating voltage are respectively about 0.25 .mu.m, 6 nm and 2.5 V. Here, the values corresponding to a 256-M bit DRAM are used. In the prior art, when the operating voltage is 3.3 V, the constant current threshold voltage defined as the gate-source voltage of the transistor of which the ratio of the effective channel width to effective channel length is 30 and in which the drain current is 10 nA is one tenth of the operating voltage, or 0.33 V at a substrate-source voltage of 0 volt and a junction temperature of 25.degree. C. with typical conditions. At this time, the extrapolated threshold voltage defined as the gate-source voltage when the drain current characteristic of a saturated region is extrapolated for zero current is about 0.2 V higher than the constant current threshold voltage, or about 0.53 V. When the operating voltage is reduced to 2.5 V, the extrapolated threshold voltage is reduced to about 0.4 V in proportion to the operating voltage in order to assure the effective gate voltage. Since the difference between the extrapolated threshold voltage and the constant current threshold voltage is substantially constant, the constant current threshold voltage is about 0.2 V. In addition, the temperature dependency of the threshold voltage must be considered. In general, when the operation of the chip at room temperature is assured, it must be guaranteed at a normal ambient temperature T.sub.a of 0.degree. C. through 70.degree. C. Moreover, the junction temperature T.sub.j within the chip can be found from the equation of

T.sub.j =T.sub.a +.theta..sub.ja .multidot.P.sub.d

where P.sub.d is the dissipation power, and .theta..sub.ja is the thermal conductivity of the chip, and thus a higher temperature must be considered. If the source voltage and the active current I.sub.ACT are 2.5 V and 50 mA, respectively, and if T.sub.a is 75.degree. C. including a margin when .theta..sub.ja is 200.degree. C./W, the junction temperature T.sub.j is 100.degree. C. The constant current threshold voltage at this value of T.sub.j is about 0.1 V when the temperature dependency of the threshold voltage is assumed to be -1.6 mV/.degree. C. In addition, if we consider the threshold voltage variation due to the process dispersion as 0.1 V, the constant current threshold voltage with 10 nA at the worst condition is about 0.0 V. In this case, if the effective gate length is 0.25 .mu.m, the gate width which is used when defining the constant current threshold voltage is about 7.5 .mu.m. If the total value of gate widths of the MOS transistors within the chip which contributes to I.sub.DC is about 4 m, the subthreshold current I.sub.DC is found to be 5 mA from the equation (2) when the subthreshold swing S is 100 mV/dec. This value of 5 mA corresponds to one tenth of I.sub.ACT as assumed above, and is thus too large to be neglected. Therefore, when the operating voltage is about 2.5 V or below, the subthreshold current in the CMOS logic circuit causes a problem.

We now consider the dissipation power of a CMOS LSI which is demanded for its application. The dissipation power in the LSI used in portable apparatus should be treated as the average dissipation power in the period of time in which it is energized and thus it includes both the standby current and the active current. Particularly in the battery-operated apparatus, both the currents are important because the idle time is determined by the average dissipation power. There are a number of LSIs which keep operating almost within the period of time in which they are energized, such as IC processors, memories and ASICs for high-speed operation. In these LSIs, only the active current is important