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| United States Patent | 5408190 |
| Link to this page | http://www.wikipatents.com/5408190.html |
| Inventor(s) | Wood; Alan G. (Boise, ID);
Farnworth; Warren M. (Nampa, ID);
Hembree; David R. (Boise, ID) |
| Abstract | A reusable burn-in/test fixture for discrete die consists of two halves.
The first half of the test fixture contains cavity in which die is
inserted. Electrical contact with bondpads or bumps on the die is
established through an intermediate substrate. When the two halves are
assembled, electrical contact with the die is established. The fixture
establishes the electrical contact and with a burn-in oven and with a
discrete die tester. The test fixture need not be opened until the burn-in
and electrical tests are completed. The fixture permits the die to be
characterized prior to assembly, so that the die may then be transferred
in an unpackaged form. The intermediate substrate may be formed of
semiconductor material or of a ceramic insulator. A Z-axis anisotropic
conductive interconnect material may be interposed between the
intermediate substrate and the die. |
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Title Information  |
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Drawing from US Patent 5408190 |
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Testing apparatus having substrate interconnect for discrete die burn-in
for nonpackaged die |
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| Publication Date |
April 18, 1995 |
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| Parent Case |
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation-in-part to U.S. patent application Ser. No.
7/709,858, filed Jun. 4, 1991, (abandoned), U.S. patent application Ser.
No. 7/788,065, filed Nov. 5, 1991, and U.S. patent application Ser. No.
7/981,956, filed Nov. 24, 1992. |
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Title Information  |
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References  |
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| *references marked with an asterisk below are user-added references |
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U.S. References |
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| | Reference | Relevancy | Comments | Reference | Relevancy | Comments | 5302891 Wood 324/765 Apr,1994 |      Your vote accepted [0 after 0 votes] | | 5177439 Liu 324/754 Jan,1993 |      Your vote accepted [0 after 0 votes] | | 5140405 King 257/727 Aug,1992 |      Your vote accepted [0 after 0 votes] | | 5123850 Elder 439/67 Jun,1992 |      Your vote accepted [0 after 0 votes] | | 5109320 Bourdelaise 361/785 Apr,1992 |      Your vote accepted [0 after 0 votes] | | 5073117 Malhi
Dec,1991 |      Your vote accepted [0 after 0 votes] | | 4996476 Balyasny 324/754 Feb,1991 |      Your vote accepted [0 after 0 votes] | | 4987365 Shreeve 324/758 Jan,1991 |      Your vote accepted [0 after 0 votes] | | 4970460 Jensen 324/754 Nov,1990 |      Your vote accepted [0 after 0 votes] | | 4956605 Bickford 324/760 Sep,1990 |      Your vote accepted [0 after 0 votes] | | 4954878 Fox 257/675 Sep,1990 |      Your vote accepted [0 after 0 votes] | | 4899107 Corbett 324/765 Feb,1990 |      Your vote accepted [0 after 0 votes] | | 4855672 Shreeve 324/760 Aug,1989 |      Your vote accepted [0 after 0 votes] | | 4843313 Walton 324/763 Jun,1989 |      Your vote accepted [0 after 0 votes] | | 4766371 Moriya 324/763 Aug,1988 |      Your vote accepted [0 after 0 votes] | | 4760335 Lindberg 324/758 Jul,1988 |      Your vote accepted [0 after 0 votes] | | 4739257 Jenson 324/763 Apr,1988 |      Your vote accepted [0 after 0 votes] | | 4725918 Bakker 361/220 Feb,1988 |      Your vote accepted [0 after 0 votes] | | 4686468 Lee 324/757 Aug,1987 |      Your vote accepted [0 after 0 votes] | | 4683423 Morton 324/755 Jul,1987 |      Your vote accepted [0 after 0 votes] | | 4675599 Jensen 324/758 Jun,1987 |      Your vote accepted [0 after 0 votes] | | 4597617 Enochs 439/66 Jul,1986 |      Your vote accepted [0 after 0 votes] | | 4583425 Mann 475/83 Apr,1986 |      Your vote accepted [0 after 0 votes] | | 4560216 Egawa 439/41 Dec,1985 |      Your vote accepted [0 after 0 votes] | | 4554505 Zachry 324/755 Nov,1985 |      Your vote accepted [0 after 0 votes] | | 4437718 Selinko 439/591 Mar,1984 |      Your vote accepted [0 after 0 votes] | | 4340860 Teeple, Jr. 324/758 Jul,1982 |      Your vote accepted [0 after 0 votes] | | 4324040 Gottlieb 29/829 Apr,1982 |      Your vote accepted [0 after 0 votes] | | 4288841 Gogal 361/792 Sep,1981 |      Your vote accepted [0 after 0 votes] | | 4069453 Veenendaal 324/537 Jan,1978 |      Your vote accepted [0 after 0 votes] | | |
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| Market Size |
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| Reasonable Royalty |
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Public's "Guesstimation" of Royalty Value
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Market Review  |
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Technical Review  |
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Claims  |
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What is claimed is:
1. A discrete testing apparatus for testing a semiconductor integrated
circuit device in die form, comprising:
a) a first plate;
b) a die-receiving cavity in the first plate;
c) a second plate associated with the first plate;
d) one of the first and second plates having a plurality of connector leads
thereon;
e) an intermediate substrate located within the die receiving cavity, the
intermediate substrate having a plurality of die contacting conductors
extending therefrom, the die contacting conductors extending to die
contacts to establish electrical communication with contact locations on
the die;
f) the die contacts being positioned so that, when the die is positioned in
the die-receiving cavity, the die contacts are in alignment with contact
locations on the die and extending to the contact locations to establish
electrical communication with said contact locations; and
g) the connector leads in electrical communication with the die contacts,
the connector leads being mounted to the one of the said plates.
2. A discrete testing apparatus as described in claim 1, and wherein;
the intermediate substrate is formed of semiconductor material, and the die
contacting conductors are formed on the semiconductor material by
semiconductor circuit fabrication techniques.
3. A discrete testing apparatus as described in claim 2, and wherein;
the intermediate substrate is of a thickness sufficient to be substantially
rigid.
4. A discrete testing apparatus as described in claim 2, and wherein:
the intermediate substrate is sufficiently thin to be partially flexible.
5. A discrete testing apparatus as described in claim 1, and wherein:
the intermediate substrate is formed of a structure which includes silicon
material, and the die contacting conductors are formed on the silicon
material by semiconductor fabrication techniques.
6. A discrete testing apparatus as described in claim 5, and wherein;
the intermediate substrate is formed with a thickness sufficient to be
substantially rigid.
7. A discrete testing apparatus as described in claim 5, and wherein:
the intermediate substrate is sufficiently thin to be partially flexible.
8. A discrete testing apparatus as described in claim 1 and wherein:
a) the intermediate substrate is formed of a ceramic insulator, and the die
contacting conductors are formed on a surface of the substrate; and
b) the intermediate substrate having a plurality of circuit traces formed
thereon extending from the die contacting conductors to connection points
in electrical communication with substrate bond pads wire bonded to
contact pads on said one of the first and second plates having a plurality
of connector leads thereon.
9. A discrete testing apparatus as described in claim 1 and wherein:
the intermediate substrate is positioned in the die receiving cavity so
that the die contacts on the intermediate substrate face away from the
first plate, wherein the die is positioned above the intermediate
substrate with the contact locations on the die facing the die receiving
cavity.
10. A discrete testing apparatus as described in claim 1, and wherein:
the intermediate substrate is positioned in the die receiving cavity so
that the die contacts on the intermediate substrate are in a face up
position with respect to the die receiving cavity and the die is
positioned above the intermediate substrate with the contact locations in
a face down position on the die facing the die receiving cavity.
11. A discrete testing apparatus as described in claim 1, and wherein:
the die is positioned in the die receiving cavity so that the contact
locations on the die are in a face up position with respect to the die
contacts on the intermediate substrate and the intermediate substrate is
positioned above the die with the die contacts in a face down position on
the intermediate substrate.
12. A discrete testing apparatus as described in claim 1, further
comprising:
a pad which is electrically conductive in a Z-axis, normal to a plane of
the pad, and which provides electrical isolation across the plane of the
pad, the pad being positioned between the die and the die contacts on the
intermediate substrate.
13. A discrete testing apparatus as described in claim 1, further
comprising:
a resilient pad to bias die received in the die receiving cavity with the
intermediate substrate after the first and second plates have been mated,
to apply sufficient pressure to maintain ohmic contact between said die
contacts on the intermediate substrate and said contact locations on the
die.
14. A discrete testing apparatus as described in claim 13, and wherein:
the die contacts on the intermediate substrate are formed as raised contact
members which are in alignment with the die receiving cavity after the
first and second plates have been mated, said contact members cooperating
with said pad to apply sufficient pressure between said pad and said
contact locations on the die to establish ohmic contact between said pad
and said contact locations on the die.
15. A discrete testing apparatus as described in claim 1, further
comprising:
the die receiving cavity having a biased platform therein, the biased
platform exerting a biasing force against the die to establish an
electrical connection between the contact locations on the die and the die
contacts.
16. A discrete testing apparatus as described in claim 1, further
comprising:
an elastomeric backing strip mounted within the die receiving cavity to
secure the substrate in a position within the die receiving cavity by
means of electrostatic attraction and frictional forces.
17. A discrete testing apparatus as described in claim 1, further
comprising:
an elastomeric backing strip mounted within the die receiving cavity to
secure the die in a position within the die receiving cavity by means of
electrostatic attraction and frictional forces.
18. A discrete testing apparatus as described in claim 1, further
comprising:
a clamp adapted to contact the second plate to bias the die towards the
intermediate substrate.
19. A discrete testing apparatus for testing a semiconductor device in die
form, comprising:
a) a first plate;
b) a die-receiving cavity in the first plate;
c) a second plate;
d) means to secure the first and second plates together;
e) an intermediate substrate having a plurality of conductors thereon and
dimensioned to fit within the testing apparatus adjacent to the die when
the die is in the die receiving cavity;
f) a pad which is electrically conductive in a Z-axis, normal to a plane of
the pad, and which provides electrical isolation across the plane of the
pad, the pad being positioned over the die between the die and the
plurality of conductors; and
g) a plurality of die contacts formed on the plurality of conductors, the
die contacts being positioned so that, when the first plate and the second
plate are aligned and the die and the intermediate substrate are
positioned in the die-receiving cavity, the die contacts are in alignment
with contact locations on the die;
h) connector leads in an electrical communication with the plurality of die
contacts; and
i) a support to hold the die, the pad, and the intermediate substrate
together when the first plate and the second plate are secured together,
thereby causing the die contacts to be maintained in electrical
communication with said contact locations.
20. A discrete testing apparatus as described in claim 19, and wherein:
the intermediate substrate is formed as a structure which includes silicon
material, and the die contacting conductors are formed on the silicon
material by semiconductor fabrication techniques.
21. A discrete testing apparatus as described in claim 20, and wherein:
the intermediate substrate is of a thickness sufficient to be substantially
rigid.
22. A discrete testing apparatus as described in claim 20, and wherein;
the intermediate substrate is sufficiently thin to be partially flexible.
23. A discrete testing apparatus as described in claim 19, and wherein:
a) the intermediate substrate is formed of a ceramic insulator, and the die
contacting conductors are formed on a surface of the intermediate
substrate; and
b) the intermediate substrate includes a plurality of circuit traces formed
thereon extending from the die contacting conductors to connection points
in electrical communication with substrate bond pads wire bonded to
contact pads on said one of the first and second plates having a plurality
of connector leads thereon.
24. A discrete testing apparatus as described in claim 19, and wherein:
the intermediate substrate extending beyond the confines of a fixture
formed by the first and second plates and terminating in an external
connector, the external connector including said connector leads.
25. A discrete testing apparatus as described in claim 19, and wherein:
said pad is elastically resilient, thereby biasing against the die received
in the die receiving cavity with the intermediate substrate after the
first and second plates have been mated.
26. A discrete testing apparatus as described in claim 19, further
comprising:
means, separate from said pad, to bias the die received in the die
receiving cavity with the intermediate substrate after the first and
second plates have been mated, the means to bias cooperating with said pad
to apply sufficient pressure between said pad and said contact locations
on the die to establish ohmic contact between said pad and said contact
locations on the die.
27. A discrete testing apparatus as described in claim 19, further
comprising:
the die receiving cavity having a biased platform therein, the biased
platform exerting a biasing force against the die, the biasing force
cooperating with said pad in order to establish an electrical connection,
through said pad, between the contact locations on the die and said
plurality of die contacts.
28. A discrete testing apparatus as described in claim 27, and wherein:
the biased platform comprises an elastomeric polymer.
29. A discrete testing apparatus as described in claim 19, and wherein:
the intermediate substrate includes raised contact members which are in
alignment with the die receiving cavity after the first and second plates
have been mated, said contact members cooperating with said pad to apply
sufficient pressure between said pad and said contact locations on the die
to establish ohmic contact between said pad and said contact locations on
the die.
30. A discrete testing apparatus as described in claim 21, further
comprising:
a) an elastomeric strip, separate from said pad, cooperating with said pad
to bias die received in the die receiving cavity with the intermediate
substrate after the first and second plates have been mated, and to apply
sufficient pressure between said pad and said contact locations on the die
to establish ohmic contact between said pad and said contact locations on
the die; and
b) the elastomeric strip further securing the die in a position within the
die receiving cavity by means of electrostatic attraction and frictional
forces, thereby permitting the die to be maintained in a positional
alignment with respect to the die receiving cavity after being placed into
the die receiving cavity and prior to mating the second plate with the
first plate.
31. A discrete testing apparatus for testing a semiconductor integrated
circuit device in die form, comprising:
a) a first plate;
b) means for holding a die in the testing apparatus;
c) a second plate mating with the first plate;
d) one of the first and second plates having a plurality of connector leads
thereon;
e) a substrate located between the first and second plates having a
plurality of die contacting conductors extending therefrom, the die
contacting conductors extending to die contacts to establish electrical
communication with contact locations on the die, held within the testing
apparatus;
f) the die contacts being positioned so that, when the die is positioned
between the first and second plates, the die contacts are in alignment
with contact locations on the die;
g) means for biasing the die and substrate together; and
h) means for establishing electrical communication between the die contacts
on the substrate and the connector leads on the one of the first and
second plates.
32. A discrete testing apparatus as described in claim 31, and wherein:
the means for establishing electrical communication is bond wires attached
to the intermediate substrate and to the first plate.
33. A discrete testing apparatus as described in claim 31, and wherein:
the means for biasing is a clamp attached to the first plate. |
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Claims  |
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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrical test equipment for semiconductor
devices. More specifically, the invention relates to an apparatus and
method, which utilize conductive polymers, and which are used to perform
dynamic burn-in and full electrical/performance/speed testing on discrete
nonpackaged or semi-packaged dies.
2. Background of the Invention
Semiconductor devices are subjected to a series of test procedures in order
to assure quality and reliability. This testing procedure conventionally
includes "probe testing", in which individual dies, while still on a
wafer, are initially tested to determine functionality and speed. Probe
cards are used to electrically test die at that level. The electrical
connection interfaces with only a single die at a time in wafer; not
discrete die.
If the wafer has a yield of functional dies which indicates that quality of
the functional dies is likely to be good, each individual die is assembled
in a package to form a semiconductor device. Conventionally, the packaging
includes a lead frame and a plastic or ceramic housing.
The packaged devices are then subjected to another series of tests, which
include burn-in and discrete testing. Discrete testing permits the devices
to be tested for speed and for errors which may occur after assembly and
after burn-in. Burn-in accelerates failure mechanisms by electrically
exercising the devices (DUT) at elevated temperatures, thus eliminating
potential failures which would not otherwise be apparent at nominal test
conditions.
Variations on these procedures permit devices assembled onto circuit
arrangements, such as memory boards, to be burned-in, along with the
memory board in order to assure reliability of the circuit, as populated
with devices. This closed assembly testing assumes that the devices are
discretely packaged in order that it can then be performed more readily.
If the wafer has a yield of grossly functional die, it indicates that a
good quantity of die from the wafer are likely to be fully operative. The
die are separated with a die saw, and the nonfunctional die are scrapped,
while the rest are individually encapsulated in plastic packages or
mounted in ceramic packages with one die in each package. After the die
are packaged they are rigorously electrically tested. Components which
turn out to be nonfunctional, or which operate at questionable
specifications, are scrapped or devoted to special uses.
Packaging unusable die, only to scrap them after testing, is a waste of
time and materials, and is therefore costly. Given the relatively low
profit margins of commodity semiconductor components such as dynamic
random access memories (DRAMs) and static random access memories (SRAMs),
this practice is uneconomical. However, no thorough and cost effective
method of testing an unpackaged die is available which would prevent this
unnecessary packaging of nonfunctional and marginally functional die.
Secondly, the packaging may have other limitations which are aggravated by
burn-in stress conditions, so that the packaging becomes a limitation for
burn-in testing.
It is proposed that multiple integrated circuit devices be packaged as a
single unit, known as a multi chip module (MCM). This can be accomplished
with or without conventional lead frames. This creates two problems when
using conventional test methods. Firstly, discrete testing is more
difficult because a conventional lead frame package is not used.
Furthermore, when multiple devices are assembled into a single package,
the performance of the package is reduced to that of the die with the
lowest performance. Therefore, such dies are tested on an individual basis
at probe, using ambient and "hot chuck" test techniques, while still in
wafer form. In other words, the ability to presort the individual dice is
limited to that obtained through probe testing.
In addition, there is an increased interest in providing parts which are
fully characterized prior to packaging. This is desired not only because
of the cost of the package, but also because there is demand for
multi-chip modules (MCMs), in which multiple parts in die form are tested
and assembled into a single unit. While there are various techniques
proposed for testing, burning in and characterizing a singulated die, it
would be advantageous to be able to "wafer map" the die prior to assembly
with as many performance characteristics as possible. Ideally, one would
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