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Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die    
United States Patent5408190   
Link to this pagehttp://www.wikipatents.com/5408190.html
Inventor(s)Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID); Hembree; David R. (Boise, ID)
AbstractA reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. Electrical contact with bondpads or bumps on the die is established through an intermediate substrate. When the two halves are assembled, electrical contact with the die is established. The fixture establishes the electrical contact and with a burn-in oven and with a discrete die tester. The test fixture need not be opened until the burn-in and electrical tests are completed. The fixture permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. The intermediate substrate may be formed of semiconductor material or of a ceramic insulator. A Z-axis anisotropic conductive interconnect material may be interposed between the intermediate substrate and the die.
   














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Drawing from US Patent 5408190
Testing apparatus having substrate interconnect for discrete die burn-in

     for nonpackaged die - US Patent 5408190 Drawing
Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die
Inventor     Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID); Hembree; David R. (Boise, ID)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
All assignments
Publication Date     April 18, 1995
Application Number     08/073,005
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     June 7, 1993
US Classification     324/765 257/E21.512 257/E21.525 257/E23.004 257/E23.069 257/E23.07 324/755
Int'l Classification     G01R 031/02
Examiner     Nguyen; Vinh
Assistant Examiner    
Attorney/Law Firm     Protigal; Stanley N. Gratton; Stephen A. ,
Address
Parent Case     CROSS-REFERENCE TO RELATED APPLICATION This is a continuation-in-part to U.S. patent application Ser. No. 7/709,858, filed Jun. 4, 1991, (abandoned), U.S. patent application Ser. No. 7/788,065, filed Nov. 5, 1991, and U.S. patent application Ser. No. 7/981,956, filed Nov. 24, 1992.
Priority Data    
USPTO Field of Search     324/158 F 324/158 P 324/72.5 324/158.1 324/750 324/754 324/731 324/765 324/755 361/411 439/61 439/91 437/8 257/40 257/48 174/52.4
Patent Tags     testing substrate interconnect discrete die burn-in nonpackaged die
   
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5302891
Wood
324/765
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 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. A discrete testing apparatus for testing a semiconductor integrated circuit device in die form, comprising:

a) a first plate;

b) a die-receiving cavity in the first plate;

c) a second plate associated with the first plate;

d) one of the first and second plates having a plurality of connector leads thereon;

e) an intermediate substrate located within the die receiving cavity, the intermediate substrate having a plurality of die contacting conductors extending therefrom, the die contacting conductors extending to die contacts to establish electrical communication with contact locations on the die;

f) the die contacts being positioned so that, when the die is positioned in the die-receiving cavity, the die contacts are in alignment with contact locations on the die and extending to the contact locations to establish electrical communication with said contact locations; and

g) the connector leads in electrical communication with the die contacts, the connector leads being mounted to the one of the said plates.

2. A discrete testing apparatus as described in claim 1, and wherein;

the intermediate substrate is formed of semiconductor material, and the die contacting conductors are formed on the semiconductor material by semiconductor circuit fabrication techniques.

3. A discrete testing apparatus as described in claim 2, and wherein;

the intermediate substrate is of a thickness sufficient to be substantially rigid.

4. A discrete testing apparatus as described in claim 2, and wherein:

the intermediate substrate is sufficiently thin to be partially flexible.

5. A discrete testing apparatus as described in claim 1, and wherein:

the intermediate substrate is formed of a structure which includes silicon material, and the die contacting conductors are formed on the silicon material by semiconductor fabrication techniques.

6. A discrete testing apparatus as described in claim 5, and wherein;

the intermediate substrate is formed with a thickness sufficient to be substantially rigid.

7. A discrete testing apparatus as described in claim 5, and wherein:

the intermediate substrate is sufficiently thin to be partially flexible.

8. A discrete testing apparatus as described in claim 1 and wherein:

a) the intermediate substrate is formed of a ceramic insulator, and the die contacting conductors are formed on a surface of the substrate; and

b) the intermediate substrate having a plurality of circuit traces formed thereon extending from the die contacting conductors to connection points in electrical communication with substrate bond pads wire bonded to contact pads on said one of the first and second plates having a plurality of connector leads thereon.

9. A discrete testing apparatus as described in claim 1 and wherein:

the intermediate substrate is positioned in the die receiving cavity so that the die contacts on the intermediate substrate face away from the first plate, wherein the die is positioned above the intermediate substrate with the contact locations on the die facing the die receiving cavity.

10. A discrete testing apparatus as described in claim 1, and wherein:

the intermediate substrate is positioned in the die receiving cavity so that the die contacts on the intermediate substrate are in a face up position with respect to the die receiving cavity and the die is positioned above the intermediate substrate with the contact locations in a face down position on the die facing the die receiving cavity.

11. A discrete testing apparatus as described in claim 1, and wherein:

the die is positioned in the die receiving cavity so that the contact locations on the die are in a face up position with respect to the die contacts on the intermediate substrate and the intermediate substrate is positioned above the die with the die contacts in a face down position on the intermediate substrate.

12. A discrete testing apparatus as described in claim 1, further comprising:

a pad which is electrically conductive in a Z-axis, normal to a plane of the pad, and which provides electrical isolation across the plane of the pad, the pad being positioned between the die and the die contacts on the intermediate substrate.

13. A discrete testing apparatus as described in claim 1, further comprising:

a resilient pad to bias die received in the die receiving cavity with the intermediate substrate after the first and second plates have been mated, to apply sufficient pressure to maintain ohmic contact between said die contacts on the intermediate substrate and said contact locations on the die.

14. A discrete testing apparatus as described in claim 13, and wherein:

the die contacts on the intermediate substrate are formed as raised contact members which are in alignment with the die receiving cavity after the first and second plates have been mated, said contact members cooperating with said pad to apply sufficient pressure between said pad and said contact locations on the die to establish ohmic contact between said pad and said contact locations on the die.

15. A discrete testing apparatus as described in claim 1, further comprising:

the die receiving cavity having a biased platform therein, the biased platform exerting a biasing force against the die to establish an electrical connection between the contact locations on the die and the die contacts.

16. A discrete testing apparatus as described in claim 1, further comprising:

an elastomeric backing strip mounted within the die receiving cavity to secure the substrate in a position within the die receiving cavity by means of electrostatic attraction and frictional forces.

17. A discrete testing apparatus as described in claim 1, further comprising:

an elastomeric backing strip mounted within the die receiving cavity to secure the die in a position within the die receiving cavity by means of electrostatic attraction and frictional forces.

18. A discrete testing apparatus as described in claim 1, further comprising:

a clamp adapted to contact the second plate to bias the die towards the intermediate substrate.

19. A discrete testing apparatus for testing a semiconductor device in die form, comprising:

a) a first plate;

b) a die-receiving cavity in the first plate;

c) a second plate;

d) means to secure the first and second plates together;

e) an intermediate substrate having a plurality of conductors thereon and dimensioned to fit within the testing apparatus adjacent to the die when the die is in the die receiving cavity;

f) a pad which is electrically conductive in a Z-axis, normal to a plane of the pad, and which provides electrical isolation across the plane of the pad, the pad being positioned over the die between the die and the plurality of conductors; and

g) a plurality of die contacts formed on the plurality of conductors, the die contacts being positioned so that, when the first plate and the second plate are aligned and the die and the intermediate substrate are positioned in the die-receiving cavity, the die contacts are in alignment with contact locations on the die;

h) connector leads in an electrical communication with the plurality of die contacts; and

i) a support to hold the die, the pad, and the intermediate substrate together when the first plate and the second plate are secured together, thereby causing the die contacts to be maintained in electrical communication with said contact locations.

20. A discrete testing apparatus as described in claim 19, and wherein:

the intermediate substrate is formed as a structure which includes silicon material, and the die contacting conductors are formed on the silicon material by semiconductor fabrication techniques.

21. A discrete testing apparatus as described in claim 20, and wherein:

the intermediate substrate is of a thickness sufficient to be substantially rigid.

22. A discrete testing apparatus as described in claim 20, and wherein;

the intermediate substrate is sufficiently thin to be partially flexible.

23. A discrete testing apparatus as described in claim 19, and wherein:

a) the intermediate substrate is formed of a ceramic insulator, and the die contacting conductors are formed on a surface of the intermediate substrate; and

b) the intermediate substrate includes a plurality of circuit traces formed thereon extending from the die contacting conductors to connection points in electrical communication with substrate bond pads wire bonded to contact pads on said one of the first and second plates having a plurality of connector leads thereon.

24. A discrete testing apparatus as described in claim 19, and wherein:

the intermediate substrate extending beyond the confines of a fixture formed by the first and second plates and terminating in an external connector, the external connector including said connector leads.

25. A discrete testing apparatus as described in claim 19, and wherein:

said pad is elastically resilient, thereby biasing against the die received in the die receiving cavity with the intermediate substrate after the first and second plates have been mated.

26. A discrete testing apparatus as described in claim 19, further comprising:

means, separate from said pad, to bias the die received in the die receiving cavity with the intermediate substrate after the first and second plates have been mated, the means to bias cooperating with said pad to apply sufficient pressure between said pad and said contact locations on the die to establish ohmic contact between said pad and said contact locations on the die.

27. A discrete testing apparatus as described in claim 19, further comprising:

the die receiving cavity having a biased platform therein, the biased platform exerting a biasing force against the die, the biasing force cooperating with said pad in order to establish an electrical connection, through said pad, between the contact locations on the die and said plurality of die contacts.

28. A discrete testing apparatus as described in claim 27, and wherein:

the biased platform comprises an elastomeric polymer.

29. A discrete testing apparatus as described in claim 19, and wherein:

the intermediate substrate includes raised contact members which are in alignment with the die receiving cavity after the first and second plates have been mated, said contact members cooperating with said pad to apply sufficient pressure between said pad and said contact locations on the die to establish ohmic contact between said pad and said contact locations on the die.

30. A discrete testing apparatus as described in claim 21, further comprising:

a) an elastomeric strip, separate from said pad, cooperating with said pad to bias die received in the die receiving cavity with the intermediate substrate after the first and second plates have been mated, and to apply sufficient pressure between said pad and said contact locations on the die to establish ohmic contact between said pad and said contact locations on the die; and

b) the elastomeric strip further securing the die in a position within the die receiving cavity by means of electrostatic attraction and frictional forces, thereby permitting the die to be maintained in a positional alignment with respect to the die receiving cavity after being placed into the die receiving cavity and prior to mating the second plate with the first plate.

31. A discrete testing apparatus for testing a semiconductor integrated circuit device in die form, comprising:

a) a first plate;

b) means for holding a die in the testing apparatus;

c) a second plate mating with the first plate;

d) one of the first and second plates having a plurality of connector leads thereon;

e) a substrate located between the first and second plates having a plurality of die contacting conductors extending therefrom, the die contacting conductors extending to die contacts to establish electrical communication with contact locations on the die, held within the testing apparatus;

f) the die contacts being positioned so that, when the die is positioned between the first and second plates, the die contacts are in alignment with contact locations on the die;

g) means for biasing the die and substrate together; and

h) means for establishing electrical communication between the die contacts on the substrate and the connector leads on the one of the first and second plates.

32. A discrete testing apparatus as described in claim 31, and wherein:

the means for establishing electrical communication is bond wires attached to the intermediate substrate and to the first plate.

33. A discrete testing apparatus as described in claim 31, and wherein:

the means for biasing is a clamp attached to the first plate.
 Description Submit all comments and votes
 


BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electrical test equipment for semiconductor devices. More specifically, the invention relates to an apparatus and method, which utilize conductive polymers, and which are used to perform dynamic burn-in and full electrical/performance/speed testing on discrete nonpackaged or semi-packaged dies.

2. Background of the Invention

Semiconductor devices are subjected to a series of test procedures in order to assure quality and reliability. This testing procedure conventionally includes "probe testing", in which individual dies, while still on a wafer, are initially tested to determine functionality and speed. Probe cards are used to electrically test die at that level. The electrical connection interfaces with only a single die at a time in wafer; not discrete die.

If the wafer has a yield of functional dies which indicates that quality of the functional dies is likely to be good, each individual die is assembled in a package to form a semiconductor device. Conventionally, the packaging includes a lead frame and a plastic or ceramic housing.

The packaged devices are then subjected to another series of tests, which include burn-in and discrete testing. Discrete testing permits the devices to be tested for speed and for errors which may occur after assembly and after burn-in. Burn-in accelerates failure mechanisms by electrically exercising the devices (DUT) at elevated temperatures, thus eliminating potential failures which would not otherwise be apparent at nominal test conditions.

Variations on these procedures permit devices assembled onto circuit arrangements, such as memory boards, to be burned-in, along with the memory board in order to assure reliability of the circuit, as populated with devices. This closed assembly testing assumes that the devices are discretely packaged in order that it can then be performed more readily.

If the wafer has a yield of grossly functional die, it indicates that a good quantity of die from the wafer are likely to be fully operative. The die are separated with a die saw, and the nonfunctional die are scrapped, while the rest are individually encapsulated in plastic packages or mounted in ceramic packages with one die in each package. After the die are packaged they are rigorously electrically tested. Components which turn out to be nonfunctional, or which operate at questionable specifications, are scrapped or devoted to special uses.

Packaging unusable die, only to scrap them after testing, is a waste of time and materials, and is therefore costly. Given the relatively low profit margins of commodity semiconductor components such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), this practice is uneconomical. However, no thorough and cost effective method of testing an unpackaged die is available which would prevent this unnecessary packaging of nonfunctional and marginally functional die. Secondly, the packaging may have other limitations which are aggravated by burn-in stress conditions, so that the packaging becomes a limitation for burn-in testing.

It is proposed that multiple integrated circuit devices be packaged as a single unit, known as a multi chip module (MCM). This can be accomplished with or without conventional lead frames. This creates two problems when using conventional test methods. Firstly, discrete testing is more difficult because a conventional lead frame package is not used. Furthermore, when multiple devices are assembled into a single package, the performance of the package is reduced to that of the die with the lowest performance. Therefore, such dies are tested on an individual basis at probe, using ambient and "hot chuck" test techniques, while still in wafer form. In other words, the ability to presort the individual dice is limited to that obtained through probe testing.

In addition, there is an increased interest in providing parts which are fully characterized prior to packaging. This is desired not only because of the cost of the package, but also because there is demand for multi-chip modules (MCMs), in which multiple parts in die form are tested and assembled into a single unit. While there are various techniques proposed for testing, burning in and characterizing a singulated die, it would be advantageous to be able to "wafer map" the die prior to assembly with as many performance characteristics as possible. Ideally, one would