A video replay store controller wherein appropriate ones of a plurality of field stores are selected for storing replayed video data in a digital video tape recorder (DVTR). The controller comprises a transition detector associated with each of a plurality of video replay heads, for detecting changes in field identifiers associated with consecutively replayed video data blocks received from that video replay head, thereby detecting a field transition in the data replayed by that video replay head.
Displaying video images includes determining which of at least two video field polarities a video display is in a state to display and choosing a stored video field for display based on the determined state.
An image reproducing device comprises an edit information storing unit for storing edit information, an image information storing unit for storing image information which can be accessed randomly, an image reproducing unit for reading image information from the image information storing unit and reproducing it, a reading controlling unit for controlling a faulty area storing unit which stores faulty area information according to edit information from the edit information storing unit, an image displaying unit for displaying image information from the image reproducing unit, a faulty field calculating unit for calculating a faulty field according to faulty area information from the faulty area storing unit, a copy range calculating unit for calculating a copy range according to faulty field information from the faulty field calculating unit, and a copy implementing unit for copying image information to the image storing unit according to copy range information from the copy range calculating unit, and registering edit information about copied image into the edit information storing unit.
A read/write control circuit for a memory uses a read/write judging circuit which receives read and write request signals and a directional signal indicating whether a sequence of sound data inputted into the memory is in forward (normal) sequence or reversed sequence. The read/write judging circuit refers to the directional signal when both the read and write request signals simultaneously become active such that the read/write judge circuit gives priorty to a write operation in the memory when the sequence is normal by asserting a write enable signal and gives priorty to a read operation in the memory when the sequence is reversed by asserting a read enable signal.