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Description  |
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BACKGROUND OF THE INVENTION
This invention relates generally to DC-to-DC. converters and more
particularly to a pulse-width modulated switching converter.
DC-to-DC power converters utilizing a switching device in a combination of
inductors and capacitors to derive power from one source of DC voltage and
then deliver that power to a load at the same or a different DC voltage
are well known. Many different types of topologies exist for implementing
such power converters. The number of different possible combinations using
but a relatively few components has resulted in several standard topology
types which include, among others, the buck, boost, buck-boost, forward,
flyback, and CUK converters. With what initially appears to be only a
simple change or a modification in the particular converter
implementation, an extremely significant performance variation can result.
While many different topologies could be described, each with its own
advantages and disadvantages, the configurations shown in FIGS. 1-3 best
represent prior art topologies which exhibit the closest similarity to
that of the subject invention to be hereinafter described.
FIG. 1, for example, discloses what might be termed a forward converter
topology and comprises an isolated or transformer version of a buck
converter which, without an input filter, is typically characterized by a
converter which displays discontinuous input current while providing a
continuous output current. Such an arrangement offers an efficient power
conversion technique; however, it almost always requires the use of a
reset winding on the power transformer in order to reset the transformer
core by returning its stored energy to the primary side. This requirement,
while not being difficult to implement, creates some additional design
considerations associated with the reset circuitry.
With respect to the circuitry shown in FIG. 2, it exemplifies what is
termed flyback converter topology and comprise what might be referred to
as an isolated or transformer version of a boost converter which, without
an input filter, is characterized by discontinuous input current while
also providing discontinuous output current and where the required
inductor is incorporated into the transformer which comprises a flyback
transformer. It typically offers the smallest number of components for
DC-to-DC power conversion.
The third configuration comprises topology which is illustrative of an
isolated or transformer version of the CUK converter. An isolated CUK
converter utilizes a transformer which is capacitively coupled both on the
primary and secondary sides.
While each of the above-referenced power converters as well as other known
converter topologies have known utility, inherent limitations and certain
disadvantages nevertheless exist.
SUMMARY
Accordingly, it becomes a primary object of this invention to provide an
improvement in DC-to-DC power converters.
It is another object of the invention to provide an improvement in
pulse-width modulated DC-to-DC power converters.
It is still another object of the invention to provide a pulse-width
modulated DC-to-DC power converter having current mode control.
And it is yet another object of the invention to provide a DC-to-DC
converter which provides both volt-second balance of the power transformer
and ampere-second balance of the current sensing transformer
simultaneously.
Briefly, the foregoing and other objects of the invention are achieved by a
current-mode controlled pulse-width modulated DC-to-DC power converter
including both isolated and non-isolated implementations comprised of a
first inductor, i.e. a transformer or an equivalent fixed inductor equal
to the inductance of the secondary winding of the transformer, coupled
across a source of DC input voltage via a controlled switch device, e.g. a
transistor, and which is rendered alternately conductive (ON) and
non-conductive (OFF) in accordance with a signal from a feedback control
circuit which continuously controls the duty cycle of the transistor
switch in relation to a complete cycle of operation. A first capacitor
capacitively couples one side of the first inductor to an output filter
circuit including a second inductor coupled to a second capacitor which in
turn is coupled to the other side of the first inductor, with the circuit
load being coupled across the second capacitor. A semiconductor diode is
additionally coupled from a common circuit connection between the first
capacitor and the second inductor to the other side of the first inductor.
A current sense transformer generating a current feedback signal for the
switch control circuit is directly coupled in series with the other side
of the first inductor so that the first capacitor, the second inductor and
the current sense transformer are connected in series through the first
inductor. This enables the current of the first and second inductors to be
alternately sensed during both portions of an operational cycle. The
inductance values of the first and second inductors, moreover, are made
identical. The location of the current sense transformer and the use of
equal valued first and second inductors result in a relatively simple
DC-to-DC converter topology wherein volt-second balance in the first
inductor and ampere-second balance in the current sense transformer are
achieved simultaneously while at the same time reducing undesired stresses
on the switching transistor.
BRIEF DESCRIPTION OF THE DRAWING
The following detailed description of the invention will be more readily
understood when considered together with the accompanying drawings
wherein:
FIG. 1 is an electrical schematic diagram illustrative of a known prior art
forward type of converter topology;
FIG. 2 is an electric schematic diagram illustrative of a flyback type
converter topology;
FIG. 3 is an electrical schematic diagram illustrative of an isolated
version of a known prior art CUK type converter topology;
FIG. 4 is an electrical schematic diagram illustrative of an isolated or
transformer version of the preferred embodiment of the invention;
FIG. 5 is an electrical schematic diagram illustrative of a non-isolated
version of the preferred embodiment of the invention shown in FIG. 4;
FIG. 6 is an electrical schematic diagram illustrative of the topology
shown in FIG. 5 during a first portion of a circuit operating time period;
FIG. 7 is an electrical circuit diagram illustrative of the circuit shown
in FIG. 5 during a second portion of the operational time period;
FIG. 8 is a set of time related waveforms illustrative of the current and
voltage relationships provided by the non-isolated embodiment shown in
FIG. 5; and
FIG. 9 is a waveform diagram illustrative of the current flow through the
current sensing transformer shown in FIG. 5 during both portions and of
the operational time period.
DETAILED DESCRIPTION OF THE INVENTION PRIOR ART
Before considering the details of the invention, reference will first be
made back to the prior art converter topologies referred to above and
illustrated in FIGS. 1-3.
As shown in FIG. 1, the isolated forward topology depicted thereat includes
a DC voltage input source 10 which applies energy to the primary winding
12 of a power transformer 14 under the control of a transistor switch 16,
rendered alternately conductive (ON) and non-conductive (OFF) during each
cycle T.sub.s of operation by a feedback control circuit 18 coupled to the
primary winding 12 and which controls the ON and OFF time dT.sub.s and
dT.sub.s, respectively, of the transistor 16, where d designates the duty
cycle, and accordingly that of the converter itself. The secondary winding
20 couples energy to an inductor-capacitor output filter including an
inductor 22 and capacitor 24, with the load comprising a resistance
element shown by reference numeral 26 coupled across or shunting capacitor
24.
Furthermore, a diode 28 is connected in series from one (.) polarity end of
the secondary winding 20 to the inductor 22, while a second diode 30
shunts both the inductor 22 and the capacitor 24 while being coupled to
the other or opposite end of the secondary winding 20 along with the one
side of the capacitor 24 and load 26 The primary side of the transformer
14 also includes a reset circuit including a reset winding 32 having its
(.) polarity end connected to ground. However, it also requires an
additional diode 34 and a capacitor 36 which forms part of an input filter
including an inductor 38 connected in series with voltage source 10. The
input filter acts to filter out voltage and current noise on the input
voltage V.sub.in, and primarily to filter converter induced current pulses
from the DC power source 10.
The forward converter topology illustrated in FIG. 1 offers an efficient
power conversion technique; however, it typically requires the use of a
reset winding such as the winding 32 to reset the transformer core of the
power transformer 14 by returning its stored energy to the primary side.
This requirement, although not difficult to implement, causes certain
design problems for some applications, such as requiring the additional
diode 34 and a relatively large capacitance value for the capacitor 36.
With respect to the flyback topology as depicted in FIG. 2, it
intentionally stores energy in the inductance of the power transformer 14
during the on-time interval dT.sub.s of the transistor power switch 16 and
then releases the energy to the secondary side of the transformer 14
during its off-time dT.sub.s and where for continuous mode operation
dT.sub.s +dT.sub.s =T.sub.s, the time period for one operational cycle.
The energy delivered to the load side of the transformer 14 is out of
phase with the reenergizing process of the inductance which is
incorporated into the transformer 14. If operated in the continuous
inductor current mode, this characteristic produces inherent problems in
the stability in the duty cycle control circuit 18 which generally results
in compromised dynamic performance and when operated in the discontinuous
inductor current mode, the switching transistor 16 and the diode 28 can be
subjected to undesirable relatively high peak current stresses.
As to the CUK topology illustrated in FIG. 3, in addition to capacitively
coupling the primary and secondary windings 12 and 20 of the power
transformer 14 to their respective input and output circuit components,
the grounded capacitor 36 of the forward and flyback topologies (FIGS. 1
and 2) forming part of the input filter is deleted and the control switch
device 16 is no longer directly connected to the primary winding 12, but
is now connected to a circuit node 39 common to both the inductor 38 and
the coupling capacitor 40. Additionally, damping circuits comprised of
respective series circuits including capacitor 44, resistor 46 and
capacitor 48, resistor 50 must be utilized and shunt the coupling
capacitors 40 and 42.
The coupling capacitor arrangement of the CUK topology operates to
continuously maintain volt-second balance on the core of the transformer
14 in addition to developing a push-pull driving voltage for improved flux
utilization. In so doing, the front end inductor 38 now operates as a
current source which drives energy into the transformer 14 and the
coupling capacitors 40 and 42. One major disadvantage of the CUK topology,
however, is that this current source typically produces voltage spikes
across the switching transistor 16, which are often times extremely
difficult to reduce. Furthermore, both the switching device 16 and the
output diode 30 must carry significantly higher currents than typically
encountered in other topologies. The potential voltage and current
stresses imposed on both the switching device 16 and the diode 30 force
the circuit designer to select components rated for relatively high power
levels.
In addition to the potential switching component stresses and other
additionally required protection circuitry, not shown, the biggest
inherent disadvantage of the CUK topology is the necessary presence of
relatively large damping components across both the primary and secondary
coupling capacitors 40 and 42 which are shown comprising capacitor 44,
resistor 46, and capacitor 48, resistor 50. The damping components are
required to shape the AC behavior of the control circuitry 18 being
generally large in bulk make size and weight an important and undesirable
concern for many applications.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Considering now the preferred embodiments of the subject invention which
are shown in FIGS. 4 and 5, this invention overcomes the inherent
deficiencies of the prior art converter topologies shown in FIGS. 1-3 by
combining the characteristics of both the forward and flyback topologies
shown in FIGS. 1 and 2, while resembling the topology of the CUK topology
of FIG. 3. However, subtle differences are now present in the subject
invention which at first may not appear apparent but nevertheless are
present and necessary for achieving an improved operation.
The subject invention does not utilize a capacitively coupled primary
winding of the power transformer 14, but instead now employs a driving
arrangement similar to that of a forward topology wherein energy is
delivered to the output filter and transformer inductance or an equivalent
inductor 21 (FIG. 5) thereof during the on-time (dT.sub.s) of the
switching transistor 16. The inductor 21 in effect comprises the
transformer primary winding 12 reflected to the secondary side by the
transformer turns ratio N.sub.1 :N.sub.2.
The energy which is stored in the inductance L.sub.1 of the transformer 14
or the inductor 21, however, is not dumped back to the input side, but
instead is released to the secondary coupling capacitor (C.sub.1) 42
during the off-time (dT.sub.s) of the transistor 16 and which is similar
to the operation of a flyback topology. The topology of the subject
invention is therefore termed a "forback" topology converter since it
exhibits behavior of both the forward and flyback topologies alternately
with dT.sub.s and dT.sub.s of the transistor switching period T.sub.s.
A current sensing transformer 52 is connected in the secondary circuit as
shown in FIGS. 4 and 5 to sense the current I.sub.s flowing in the
secondary circuit for controlling the duty cycle (d) of the switching
transistor 16 in conjunction with the output voltage V.sub.o across the
load 26. The current sensing transformer 52 includes a primary winding 54
directly connected to the end of secondary winding 20 or inductor 21
opposite from the end which is directly connected to the capacitor
(C.sub.1) 42 so that the inductor currents flowing in the secondary
circuit during the respective time intervals of dT.sub.s and dT.sub.s can
be detected. The secondary winding 56 of the sensing transformer 52 is
connected to the duty cycle control circuit 18 for providing a feedback
signal voltage V.sub.s proportional to the secondary current I.sub.s. The
feedback control circuit 18 controls the duty cycle d of the transistor
switch 16.
In addition to the specific location of the current sensing transformer 52,
the methodology employed in the circuit design and hereinafter described,
results in the inductance values of L.sub.1 and L.sub.2 being
substantially equal.
These two last mentioned features result in a converter topology wherein a
volt-second balance of the power transformer 14 and an amp-second balance
of the current transformer 52 are achieved simultaneously. This will be
more readily appreciated as the following detailed description of
operation is considered.
DESCRIPTION OF OPERATION
Referring now FIGS. 6-9, for the sake of simplicity FIG. 6 is illustrative
of the equivalent circuit for the non-isolated converter topology shown in
FIG. 5 during the on-time interval dT.sub.s where the transistor switch 16
is conductive. FIG. 7, on the other hand, is the equivalent circuit for
FIG. 5 during the off-time interval dT.sub.s where the switch 16 is
non-conductive.
The following operational conditions exist:
##EQU1##
It can be seen with reference to FIG. 6 that during the on-time interval
dT.sub.s, wherein the semiconductor switch 16 is closed, the diode
(D.sub.1) 40, becomes reverse biased and is therefore considered an open
circuit resulting in the equivalent circuit as shown. During this time,
energy flows from V.sub.g i.e. source 10' to inductor (L.sub.1) 21,
inductor (L.sub.2) 22, and capacitor (C.sub.2) 24 and from capacitor
(C.sub.1) 42 to load resistor (R.sub.L) 26.
Two currents flow during the dT.sub.s interval, namely, I.sub.L1 and
I.sub.L2. The energy (E.sub.L1) stored in the inductance (L.sub.1) 21
increases from a minimum value to a maximum value according to the
expressions:
E.sub.L1 (min)=1/2L.sub.1 .times.I.sub.L1.sup.2 (min) (7)
and,
E.sub.L1 (max)=1/2L.sub.1 .times.I.sub.L1.sup.2 (max) (8)
whereupon an increase in energy, .DELTA.E.sub.1, stored in inductor
(L.sub.1) 21 which can be expressed as:
.uparw..DELTA.E.sub.1 =1/2L.sub.1 .times.[I.sub.L1.sup.2
(max)-I.sub.L1.sup.2 (min)] (9)
Accordingly, the current in inductor (L.sub.1) 21 increases linearly from a
minimum value to a maximum value as shown in FIG. 8(a) by reference
numeral 58.
The voltage applied to inductor (L.sub.2) 22 is equal to V.sub.g +V.sub.C1
-V.sub.C2 or simply V.sub.g whereupon the stored energy increases from a
minimum value to a maximum value according to the expressions:
E.sub.L2 (min)=1/2L.sub.2 .times.I.sub.L2.sup.2 (min) (10)
and
E.sub.L2 (max)=1/2L.sub.2 .times.I.sub.L2.sup.2 (max) (11)
causing an increase in energy, .DELTA.E.sub.2, which can be expressed as:
.uparw.E.sub.2 =1/2L.sub.2 .times.[I.sub.L2.sup.2 (max)-I.sub.L2.sup.2
(min)] (12)
As a consequence, the current I.sub.L2 in the inductor 22 increases
linearly from a minimum value to a maximum value as shown by reference
numeral 60 in FIG. 8(b).
With respect to the capacitor currents flowing during dT.sub.s, the current
out of capacitor (C.sub.1) 42 is equal to I.sub.L2 and decreases from a
maximum value to a minimum value as shown by reference numeral 62 of FIG.
8(c) and is 180.degree. out of phase with I.sub.L2 of FIG. 8(b). The
energy stored in capacitor (C.sub.1) 42 also decreases from a maximum
value to a minimum value according to the expressions:
E.sub.C1 (max)=1/2C.sub.1 .times.V.sub.C1.sup.2 (max) (13)
and
E.sub.C1 (min)=1/2C.sub.1 .times.V.sub.C1.sup.2 (min) (14)
whereupon the energy change, .DELTA.E.sub.3, stored in capacitor (C.sub.1)
42 can be expressed as:
.uparw.E.sub.3 =1/2C.sub.1 .times.[V.sub.C1.sup.2 (max)-V.sub.C1.sup.2
(min)] (15)
The current entering the + terminal of capacitor (C.sub.2) 24 is I.sub.L2
-I.sub.o. An energy change, .DELTA.E.sub.4, which can be expressed as:
.uparw.E.sub.4 =1/2C.sub.2 [V.sub.C2.sup.2 (max)-V.sub.C2.sup.2 (min)](16)
V.sub.C2 appears as the sinusoidal curve portion 64 shown in FIG. 8(d) and
changes from a minimum value to a maximum value as shown but is out of
phase with I.sub.L1 and I.sub.L2 by an angle .phi. which is determined by
the relative values of L.sub.2, C.sub.2 and R.sub.L.
As a result of these interrelationships, the current I.sub.s flowing
through the primary winding 54 of the current sense transformer 52, is
equal to I.sub.L2 and appears identical to the linear curve portion 60 of
FIG. 8(b) as shown in FIG. 9 by reference numeral 66.
Turning attention now to the off-time interval dT.sub.s, when the
transistor switch 16 is non-conductive, the diode (D.sub.1) 30 in FIG. 5
becomes forward biased and can be considered a short circuit, resulting in
an equivalent circuit as shown in FIG. 7. While two loops are shown, it is
done for purposes of illustration only, since the two conductors 68.sub.a
and 68.sub.b shown thereat are in actuality a single current conducting
path.
During the dT.sub.s interval, energy flows from the inductor (L.sub.1) 21
to the capacitor (C.sub.1) 42. Simultaneously, energy is delivered to the
load resistance (R.sub.L) 26 from the inductor (L.sub.2) 22 and the
capacitor (C.sub.2) 24. The current I.sub.L1 in the inductor (L.sub.1) 21
decreases linearly from a maximum value to a minimum value as shown by
reference numeral 70 in FIG. 8(a). This results in a decrease in energy,
.DELTA.E.sub.1, stored in inductor 21 (L.sub.1) which can be expressed as:
##EQU2##
In a like manner, the current I.sub.L2 in the inductor (L.sub.2) 22
decreases linearly from a maximum value to a minimum value as shown by
reference numeral 72 of FIG. 8(b). A decrease in energy, .DELTA.E.sub.2,
stored in inductor 22 (L.sub.2) occurs which can be expressed as:
##EQU3##
The current flow into capacitor (C.sub.1) 42 increases non-linearly as
shown by waveform 74 of FIG. 8(c) with an increase in energy storage,
.DELTA.E.sub.3, which can be expressed as:
##EQU4##
The current flow out of capacitor (C.sub.2) 24 is equal to I.sub.o
-I.sub.L2 which produces the corresponding voltage waveform as shown in
FIG. 8(d). The voltage V.sub.C2 lags the current, I.sub.o -I.sub.L2, by
the phase angle .phi. as shown by reference numeral 76 of FIG. 8(d). The
corresponding change in energy storage may be expressed as:
##EQU5##
With respect to the current I.sub.s in the primary winding 54 of the
current sensing transformer 52, it comprises a current -I.sub.L1 as
indicated by reference numeral 78 of FIG. 9.
Design Methodology
Regarding a physical implementation of the subject invention, the following
method of circuit design would be followed so that among other things, but
most importantly, L.sub.1 =L.sub.2. Typically, a circuit designer would
establish or would be provided with a set of initial or desired
operational parameters, namely: output voltage V.sub.o, switching
frequency f.sub.s, minimal input voltage V.sub.in(min), nominal input
voltage V.sub.in(nom), maximum input voltage V.sub.in(max), minimum output
load R.sub.L(min), nominal output load R.sub.L(nom) and maximum output
load R.sub.L(max). For purposes of explanation, it should be noted that
R.sub.L(min), for example, stands for minimum resistance in ohms, whereas
R.sub.L(max) stands for maximum resistance in ohms.
One would then proceed to determine the turns ratio N.sub.1 :N.sub.2 of
power transformer 20, including the value of the inductance L.sub.1, the
inductance L.sub.2, the capacitance C.sub.1 and the capacitance C.sub.2.
This would then be followed by the design of the power transformer if
necessary.
The first step involved is determining an acceptable duty cycle d, given
the output voltage V.sub.o, the range of the three input voltages V.sub.in
mentioned above, and by selecting the appropriate turns ratio N.sub.1
:N.sub.2 for the transformer. The turns ratio N.sub.1 :N.sub.2 should be
selected such that the maximum duty cycle d.sub.max should not exceed a
specified upper limit, typically 50% i.e. 0.5 T.sub.s and should typically
be in the range between 20% and 40% and from which the duty cycle d can be
determined from aforementioned equation (2) as:
d=N.sub.1 V.sub.o /(N.sub.2 V.sub.in +N.sub.1 .times.V.sub.o)(21)
From this, the average current I.sub.L2(avg) in the output inductor 22, and
in the transformer secondary I.sub.L1(avg), as shown in equations (3) and
(5), can be calculated from the initial parameters established and
equation (21) for minimum, nominal and maximum conditions.
Noting that one of the inventive features comprises a DC-to-DC converter
where the values of L.sub.1 and L.sub.2 are equal, the value for L.sub.2,
i.e. the inductance value of the inductor 22, is determined first. This is
based on three considerations: (1) the filter requirements of the output
filter consisting of inductance (L.sub.2) 22 and capacitor (C.sub.2) 24;
(2) the desirability of maintaining a continuous current conduction mode
in L.sub.2 ; and (3) the allowable current variation .DELTA.i of I.sub.L2
in the inductance (L.sub.2) 22.
As to the output filter requirements, the voltage input to the LC filter
comprised of inductor 22 and capacitor 24 is basically a square wave with
a magnitude of:
V.sub.filt =(N.sub.2 /N.sub.1).times.V.sub.in +V.sub.C1 (22)
The worst case scenario exists when the largest peak-to-peak output ripple
voltage across the load resistance (R.sub.L) 26 occurs at V.sub.in(max),
d.sub.(min), and R.sub.L(max). Thus,
V.sub.filt =(N.sub.2 /N.sub.1).times.V.sub.in(max) +V.sub.o(23)
Accordingly, the attenuation in dB necessary to meet the ripple requirement
is equal to:
20.times.log [V.sub.o(ripple) /V.sub.filt ] (24)
The LC filter in this invention will have a --40 dB/dec slope. Knowing this
and the required attenuation at the switching frequency f.sub.s, the
filter corner frequency f.sub.c is determined from the expression:
##EQU6##
Rearranging equation (24) yields:
L.sub.2 =1/[(2.pi.f.sub.c).sup.2 .times.C.sub.2 ] (26)
Selection of a few trial values for C.sub.2 is now made to allow one to
determine one or more candidate values for L.sub.2 which will satisfy the
output filter requirements of equation (25). However, the actual value of
L.sub.2 will also depend on the other two considerations of maintaining
continuous conduction mode and the allowable .DELTA.i percentage referred
to above.
Since it is desirable to maintain a continuous conduction mode, then a
critical minimum value of L.sub.2 can be determined for which continuous
conduction is maintained under the conditions of lightest load
R.sub.L(min) and maximum input voltage V.sub.in(max). It can be shown
that the minimum value of L.sub.2 necessary to maintain continuous
conduction mode under the lightest load and maximum input voltage
condition exists where:
L.sub.2(min) =[d.sub.max .times.T.sub.s .times.R.sub.L(min) ].div.2(27)
The value of the inductor (L.sub.2) 22 dictates the slope of the current
ramp as shown by the waveform segments 60 and 72 of FIG. 8(b). As a
general rule, under a nominal input voltage V.sub.in(nom) and nominal
output load R.sub.L(nom), .DELTA.i should remain no more than 25% of
I.sub.L2 (Avg).
In solving for L.sub.2, it can be shown that the voltage across inductor 22
L.sub.2 can be expressed as:
V.sub.L2 =L.sub.2 .times..DELTA.i/.DELTA.t (28)
where .DELTA.t=d.sub.nom .times.T.sub.s. Rearranging equation (28) results
in L.sub.2 being expressed as:
L.sub.2 =(V.sub.L2 .times..DELTA.t)/.DELTA.i (29)
or
L.sub.2 =(N.sub.2 .times.V.sub.in(nom ) .times.d.sub.nom
.times.T.sub.s)/(N.sub.1 .times.0.25.times.I.sub.L2) (30)
Accordingly, L.sub.2 is selected on the basis of equations (26), equation
(27) and equation (30). Having selected a value of L.sub.2, the value of
L.sub.1 is now also determined. The appropriate value of capacitor 24
(C.sub.2) is next determined from equation (26). The only component left
to be selected is the value for the capacitor 42 (C.sub.1).
In the determination of the capacitance value for capacitor 42 (C.sub.1),
the value of C.sub.1 is not as critical as the value of the other
components. Preferably, capacitor 24 should be a polycarbonate or
polystyrene low ESR capacitor. A 1 .mu.F polycarbonate capacitor, for
example, is adequate for 100 kHz designs where load currents are less than
one ampere(amp).
As a general rule under nominal input voltage V.sub.in(nom) and load
conditions R.sub.L(nom), the change of voltage .DELTA.v across C.sub.1
should remain no more than 25% of V.sub.o. During the on-time dT.sub.s of
the transistor switch 16 where .DELTA.v is selected to be 25% of V.sub.o,
C.sub.1 can be calculated from the expression:
C.sub.1 =(I.sub.L2(avg) .times.d.sub.nom
.times.T.sub.s)/(0.25.tim | | |
