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Description  |
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FIELD OF THE INVENTION
The invention relates to integrated circuit chip testing. Typically,
integrated circuit chips are attached to a chip carrier, thermally
conductive module chip carrier, circuit card or board, e.g., by solder
bonding, brazing, controlled collapse chip connect, wire lead bonding,
metal bump bonding, tape automated bonding, or the like. For the first
time since the wafer was diced, the chip is tested, e.g., electrically
tested and logically tested. Some of the tests are subtle, for example
tests for active and passive pattern faults and "stuck at 1" or "stuck at
0" faults. When a fault is found, the chip is removed from the card or
board. This is not a simple "desoldering" step, especially in the case of
high I/O density integrated circuit chips, bonded with encapsulation chip
connect technologies, and usually present in multi-chip modules. This is
because when a chip is found to be defective, it must be removed, the chip
site redressed, and a new chip installed for testing. In the case of a
polymeric substrate, redressing the chip site might include milling.
The chip tester of the present invention substantially reduces the need for
expensive rework. According to the method of the invention, there is
provided a method of testing semi-conductor chips. The individual
semiconductor chips have I/O, power, and ground contacts. In the method of
the invention a test fixture system is provided. The test fixture system
includes a dedicated fixture just for testing chips, a chip insertion
tool, a chip positioning tool, and a chip removal tool. The functions of
the individual tools, that is, the chip insertion tool, the chip
positioning tool, and the chip removal tool, may be combined into a
smaller set of tools. This chip test fixture system has contacts
corresponding to the contacts on the semiconductor chip. The carrier
contacts are low electrical contact resistance contacts adapted for
holding the integrated circuit chip in place during testing, with low
impedance, while allowing easy removal of the chips after testing.
According to the invention the test fixture contacts have dendritic
surfaces. By dendrites are meant essentially vertical members extending
outwardly from a generally planar area of electrically conductive
material. The dendrites, produced by a columnar growth process, generally
have an aspect ratio, of vertical to horizontal dimensions, of at least
about 1.0, a height above the planar area of electrically conductive
material of about 10 to 100 micrometers.
The chip contacts are brought into electrically conductive contact with the
dendrite bearing conductor pads on the chip test fixture system.
Electrically conductive contact requires a low impedance, low contact
resistance contact, with the integrated circuit chips being secured from
lateral movement with respect to the substrate or fixture. Test signal
input vectors are applied to the inputs of the semiconductor chip, and
output signal vectors are recovered from the semiconductor chip. In
preferred embodiment of the invention chip testing may be accelerated by
heating the integrated circuit semiconductor chip or chips under test.
The chips are removed from the fixture and either discarded or attached to
a suitable substrate.
BACKGROUND OF THE INVENTION
In the population of integrated circuit chip carriers, including thermal
conductive modules, ceramic substrates, and polymeric substrates, it is
necessary to minimize the shipment of modules with defective integrated
circuit chips, while minimizing the cost of testing and replacement.
Integrated circuit are subjected to various wafer level tests during
various stages of fabrication prior to dicing. However, after dicing it is
particularly difficult and expensive to test integrated circuit chips. One
reason is that an integrated circuit chip must be tested through its pins
and pads before populating of the carrier, card, board, or the like.
In populating a card, board or other packages integrated circuit chips are
attached to a circuit card or board, e.g., by solder bonding, controlled
collapse chip connect, wire lead bonding, or the like. The chip is then
tested as part of an assembly, e.g., electrically tested and logically
tested. Some of the tests are subtle, for example tests for active and
passive pattern faults and "stuck at 1" or "stuck at 0" faults. When a
fault is found, the chip is removed from the card or board. This is not a
simple "desoldering" step, especially in the case of high I/O density
chips, encapsulation chip connect technologies, and multi-chip modules,
where the chip must be removed, the chip site redressed, and a new chip
installed for testing. In the case of a polymeric substrate, redressing
the chip site might include milling.
DENDRITIC CHIP TESTERS
"High Performance Test System", IBM Technical Disclosure Bulletin, Volume
33, No. 1A (June 1990), pp 124-125 describes a test system for ULSI
integrated circuit memory and logic chips. In the described method, a
first silicon wafer "test board" has metallization complementary to the
metallization of the second silicon wafer to be tested. The second silicon
wafer has C4 (controlled collapse chip connection) Pb/Sn solder balls on
the contacts. The first and second silicon wafers have substantially flat
and substantially parallel surfaces, and are said to require a minimum of
compressive force for testing.
Anonymous, "New Products Test Interposer" Research Disclosure, January
1990, Number 309 (Kenneth Mason Publications Ltd., England) describes a
method for fabricating an interposer-type test head to perform electrical
testing of printed circuit cards and boards prior to component assembly.
The test interposer is built as a mirror image circuit of the circuit to
be tested. However, only the points to be tested, as lands and-pads, are
present. Circuit lines are not present. The test interposer pads are
coated with a dendritic material to make electrical contact to the
corresponding points on the printed circuit component to be tested. The
circuit board or card and the tester are then brought into contact for
testing.
TESTERS
Compressive type testers are described generally in U.S. Pat. No. 4,716,124
to Yerman et al. for TAPE AUTOMATED MANUFACTURE OF POWER SEMICONDUCTOR
DEVICES, U.S. Pat. No. 4,820,976 to Brown for TEST FIXTURE CAPABLE OF
ELECTRICALLY TESTING AN INTEGRATED CIRCUIT DIE HAVING A PLANAR ARRAY OF
CONTACTS, and U.S. Pat. No. 4,189,825 to Robillard et al. for INTEGRATED
TEST AND ASSEMBLY DEVICE.
U.S. Pat. No. 4,189,825 to Robillard et al. for INTEGRATED TEST AND
ASSEMBLY DEVICE describes a chip of the beam lead type with sharp points
on the substrate leads and etched, conical holes in the semiconductor. The
semiconductor and conical holes are metallized with a thin, conformal
metal film, leaving conical openings in the metallization. These apertures
correspond to the sharp points on the substrate leads. According to
Robillard et al, the chips may be assembled and tested, with faulty chips
removed and replaced before bonding. Bonding is by ultrasonic welding.
DENDRITIC CONNECTIONS
Dendritic connections are described in commonly assigned U.S. Pat. No.
5,137,461 of Bindra et al for SEPARABLE ELECTRICAL CONNECTION TECHNOLOGY.
Bindra et al describe separable and reconnectable electrical connections
for electrical equipment. Bindra et al's connectors have dendrites
characterized by an elongated, cylindrical morphology. These cylindrical
dendrites are prepared by a high frequency, high voltage, high current
density, pulse plating methodology utilizing a dilute electrolyte. Bindra
et al describe the pulsed electrodeposition of Pd from a 10-150 millimolar
Pd tetramine chloride, 5 molar ammonium chloride solution at 50 to 450
hertz and 200 to 1100 milliamperes per square centimeter in a pulse
plating technique.
Electrodeposition of Pd dendrites is further described in European Patent
0054695 and U.S. Pat. No. 4,328,286 (European Patent 0020020)
U.S. Pat. No. 4,328,286 (European Patent 20020) to Crosby for
ELECTROPLATING A SUBSTRATE WITH TWO LAYERS OF PALLADIUM describes
producing a low porosity Pd coating for electrical contacts. The Pd
coating is prepared by electrodepositing a first layer of Pd from an
aqueous bath containing the cationic complex Pd (NH.sub.3).sub.4.sup.++
and free ammonia with supporting anions (Cl.sup.-, Br.sup.-, NH.sub.2
SO.sub.3 .sup.-, NO.sub.2.sup.- and NO.sub.3.sup.-) and then
electrodepositing a second Pd layer from an aqueous bath containing the
anionic complex Pd(NO.sub.2).sub.2.sup.4- with supporting cations.
Commonly assigned European Patent 54695 (published Jun. 30, 1982, granted
Sep. 11, 1985, U.S. application Ser. No. 219660 filed Dec. 24, 1980)
discloses a method of preparing a Pd electrical contact by
electrodeposition from a relatively dilute solution that is sprayed onto a
cathode which is located completely outside and above the surface of the
solution, which is located in a tank. The solution forms a continuous
curtain falling from the bottom end of the cathode back into the tank. A
higher electric current than usual is used in the deposition process. The
dendrites obtained have a larger cross-section than those obtained in
conventional processes.
CONCLUSION
The art has failed to provide a means for rapid, reproducible, low cost,
high throughput testing of integrated circuit chips.
OBJECTS OF THE INVENTION
It is an object of the invention to provide for rapid, reproducible, low
cost, high throughput testing of integrated circuit chips.
It is a further object of the invention to provide a method and apparatus
for rapid, reproducible, low cost, high throughput testing of integrated
circuit chips.
It is a further object of the invention to provide a method and apparatus
for rapid, reproducible, low cost, high throughput testing of integrated
circuit chips that allows for easy chip positioning and temporary
attachment and easy removal of chips after testing.
SUMMARY OF THE INVENTION
According to the method of the invention, there is provided a method of
testing semi-conductor chips. The integrated circuit chips are placed in a
test fixture by a special tool, tested in the test fixture under carefully
maintained test conditions, and removed to assure no removal damage.
In the method of the invention a chip test fixture system is provided. This
chip test fixture system has contacts corresponding to the contacts on the
semiconductor chip. The carrier contacts have dendritic surfaces.
The chip contacts are brought into compressive contact with the conductor
pads on the chip test fixture system. The chip contacts may be C4 solder
balls, solder bumps, brazing alloy bumps, metal pads or bumps, as gold,
silver, copper, or aluminum bumps or pads, wire lead connection pads, or
tape automated bonding connection pads. The compressive contact between
the dendritic surface and the chip contacts appears to deform the chip
contact surface and provide a highly electrically conductive temporary
bond. Test signal input vectors are applied to the inputs of the
semiconductor chip across these highly electrically conductive bonds, and
output signal vectors are recovered from the semiconductor chip across
these highly conductive bonds.
After testing the temporary bonds are broken without damage to the chip or
chip contacts, and the chip is carefully removed from the test fixture.
As used herein, "dendrites" are high surface area electrically conductive
pads and contacts formed of essentially vertical members extending
outwardly from a generally planar area of electrically conductive
material. The dendrites, produced by a columnar growth process, generally
have an aspect ratio, of vertical to horizontal dimensions, of at least
about 1.0, a height above the planar area of electrically conductive
material of about 10 to 100 micrometers.
The dendritic morphology is obtained by electroplating the underlayer under
conditions that give rise to columnar growth, that is, very low cation
concentration in the electrolyte, with electroplating being carried out at
a high voltage, a high current, and a high current density. Preferably the
electroplating current is a pulsed current.
The resulting dendrites have a peak height of about 10 to 100 microns and a
density (dendrites per unit area) of about 200 to 500 dendrites per square
millimeter.
Dendrites have a chip connect pad to dendritic pad contact resistance of
about 3 to 5 milliohms.
THE FIGURES
The invention may be understood by reference to the FIGURES.
FIG. 1 is a representation of dendritic connectors, shown in cutaway view.
FIG. 2 is a flow chart of the method of the invention.
FIG. 3 is a schematic flow chart of the method of the invention, showing an
overview of both the process and the system of the invention.
FIG. 4 is a partial cutaway view of the burn in board tester of the
invention.
FIG. 5 is a perspective view of a heating assembly useful in the method and
system of the invention.
FIG. 6 is a perspective view of the bottom surface of the heating assembly
shown in FIG. 5.
FIGS. 7A and 7B show one embodiment of a chip insertion and compression
device useful in the system and method of the invention.
FIGS. 8A and 8B show an alternative embodiment of another chip insertion
and compression device also useful in the system and method of the
invention.
FIG. 9 shows a device for sequentially applying vacuum and pressure to
remove an integrated circuit chip from a burn in board tester.
FIG. 10 shows a multiple burn in board tester.
FIG. 11 is a circuit diagram of a RAM and decoder used to illustrate test
vectors.
FIG. 12 is a representation of passive faults in a Random Access Memory
(RAM) cell.
FIG. 13 is a representation of active faults in a Random Access Memory
(RAM) cell.
FIGS. 14A and 14B show the voltage versus time plots for pulsed
electroplating. FIG. 14A is a representation of the voltage versus time
for the "on/off" electroplating method of the prior art. FIG. 14B is a
representation of the voltage versus time plot for the reversal method of
a preferred embodiment of the invention herein.
DETAILED DESCRIPTION OF THE INVENTION
According to the method of the invention, there is provided a method of
testing semiconductor chips. In a preferred embodiment of the invention,
there is provided apparatus for placing semiconductor chips in the tester,
positioning and holding the semi-conductor chips during testing, and
removing the semiconductor chips after testing. The individual
semiconductor chips have I/O, power, and ground contacts. In the method of
the invention a chip test fixture system is provided. The chip test
fixture system includes a burn in board with dendritic chip connectors, a
means for placing the integrated circuit chips on the burn in board
tester, a means for applying heat and compressive force to the integrated
circuit chips under test, and a means for removing the integrated circuit
chips from the burn in board tester after completion of the test.
The burn in board of the integrated circuit chip test fixture and system
has contacts corresponding to the contacts on the semiconductor integrated
circuit chip. The test fixture contacts have surface area electrically
conductive surfaces, as columnar dendritic surfaces or polymer core
conical connector surfaces.
The chip contacts are brought into electrically conductive contact with the
conductor pads on the chip test fixture system. In the case of flip chip
connector chips, the chips are tested in their normal, connector down,
configuration. In the case of chips intended for other mounting
technologies, with their contacts on the top surface, as tape automated
bonding chips or wire lead connector chips, the chips can be mounted for
testing in an inverted configuration, with their contacts facing downward.
Test signal input vectors are applied to the inputs of the semiconductor
chip, and output signal vectors are recovered from the semiconductor chip.
After testing the chip may be removed from the substrate.
According to a preferred exemplification of the invention there is provided
a method and apparatus for testing an integrated circuit semi-conductor
chip. The chip or chips under test may be chips with bottom surface
electrical connection, which are characterized as "flip chip" bondable
chips. Alternatively, the chips may be conventional chips with upward
facing connectors. The chips have a first plurality of I/O, power, and
ground contacts. These contacts are typically chosen from the group
consisting of solder, low melting point alloys having a melting point
below 200 degrees Celsius, solder balls, brazing alloy bumps and balls,
contacts of conductive metals as gold, silver, copper, or aluminum,
controlled collapse chip connector (C4) balls, and pads for wire lead
bonding and tape automated bonding. Generally, the chip connectors are
characterized as being a structure formed of a metallic material in which
electrical contact resistance is reduced by abrasion or penetration by the
test pad material. The chip connectors may be on the bottom surface of the
chip, as in "flip chip" bonding, or on the top surface of the chip, as in
tape automated bonding or wire liead bonding, or the like.
The process of the invention starts by providing an integrated circuit chip
test system having a special and unique burn in board tester. The tester
has a second plurality of contacts corresponding to the first plurality of
contacts. This second plurality of contacts, i.e., the contacts on the
burn in board tester, have high surface area conductor surfaces. Exemplary
are columnar dendrites of porous, columnar Pd atop a smooth Pd film. The
burn in board also has signal lines for supplying test signals to the
second plurality of contacts and then to the contacts on the integrated
circuit chips.
The system includes fixtures for placing the integrated circuit
semiconductor chip on the burn in board tester, applying a compressive
force to the integrated circuit semiconductor chip, and removing the
integrated circuit semiconductor chip from the burn in board at the
conclusion of the test.
The system may, and preferably does, include one or more heating systems.
For example, a resistance heater can be integral to and incorporated into
the burn in board tester, as well as heating elements in the compressive
means. These heating systems heat the semi-conductor chips under test.
Heating the semiconductor integrated circuit chip under test accelerates
incipient failures and also accelerates the testing process.
In conducting the tests the first plurality of contacts of the
semi-conductor chip are brought into electrically conductive contact with
the second plurality of contacts on the chip test fixture system. This is
not a simple touching contact. This is a compressive contact to break
through oxide films on the contacts, and to even temporarily bond or
adhere the contacts.
The compressive force applied to the chip breaks through these oxides and
results in low impedance, adherent contact between the first plurality of
contacts on the integrated circuit semiconductor chip and the second
plurality of contacts on the burn in board tester.
The functional test of the semiconductor integrated circuit chip includes
passing test signal input vectors to the semiconductor chip and receiving
test signal output vectors from the semiconductor chip, as will be
described more fully hereinbelow.
After completion of the test it is necessary to apply a vacuum to the
surface of the integrated circuit semiconductor chip remote from the burn
in board tester and a positive pressure between the burn in board tester
and the integrated circuit semiconductor chip, there being a standoff
between the bottom of the chip and the top surface of the burn in board
tester, to break the adhesion between the first plurality of contacts on
the integrated circuit semiconductor chip and the second plurality of
contacts on the burn in board tester. This makes it possible to remove the
integrated circuit semiconductor chip from the burn in board tester.
After testing the chips that have passed are separated from chips that have
failed. According to a further embodiment of the invention, "fast" chips
can be separated from "slow" chips.
DENDRITES
Dendrites are high surface area connectors. They can be used as "pad on
pad" connectors, and for chip burn in. Dendrites have the structure shown
in FIG. 1, with (a) a electrically conductive pad or substrate, such as a
Cu pad, (b) a "smooth" underlayer, as a smooth Pd underlayer, and (c) a
porous over layer, as porous Pd layer. The substrate underlying the
electrically conductive pad can be a printed circuit board, a metallized
ceramic, or a metal pad on a flexible circuit. The underlayer can be a Pd
thin film, e.g., a Pd layer direct current plated from a relatively
concentrated electroplated bath. The outer layer is a porous, columnar Pd
layer, typically deposited from a dilute electroplating solution, with a
pulsed, high voltage, high current, high current density electroplating
solution. There may, optionally, be a gold layer, or a solder layer, as a
Bi--Sn or Pb--Sn layer, atop the porous Pd layer for bonding.
The dendritic morphology is obtained by electroplating the underlayer under
conditions that give rise to columnar growth, that is, very low cation
concentration in the electrolyte, with electroplating being carried out at
a high voltage, a high current, and a high current density. Preferably the
electroplating current is a pulsed current. In the case of a particularly
preferred embodiment of the invention the plating current is pulsed
positive and negative.
The dendritic surface is prepared by first electroplating a smooth Pd
coating, referred to in the electroplating as a shiny or reflective plate,
onto Cu pads. This smooth Pd layer is deposited from a relatively
concentrated Pd electroplating solution, containing about 100 or more
millimoles of Pd or more, at a low current density of about 50 to 100
milliamperes per square centimeter or lower.
A columnar, porous Pd layer is applied atop the Pd undercoat. This
columnar, porous coat is applied from a relatively dilute Pd
electroplating solution having a Pd concentration of about 10-50
millimoles per liter in Pd (versus about 100 millimoles of Pd per liter
for conventional electroplating). Typical electroplating solutions include
palladium tetra-amine chloride/ ammonium chloride, at a pH of about 9 to
10. Typical pulsed electroplating programs include a ten to twenty percent
duty cycle, and a current density of about 500 to 1000 mA/cm.sup.2.
While satisfactory results are obtained with a single phase pulsed current,
as shown in FIG. 14A, and denominated "Prior Art," we have found that
superior results are obtained with about 2.5 percent to about 25% voltage
reversal with a two phase electroplating cycle, as shown in FIG. 14A. By
"single phase" pulsed electroplating cycle, we mean an electroplating
current that is pulsed to zero and positive values. By a "two phase"
pulsed electroplating cycle we mean an electroplating current that is
pulsed to zero and positive values and to zero and negative values, as
shown in FIG. 14B.
One such pulse pattern that we have found particularly outstanding has the
following characteristics:
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POSITIVE PULSE CONDITIONS
Peak Current Density
200-400 Amperes/ft.sup.2
Pulse Time On 0.5 to 1.0 millisecond
Pulse Time Off 2.0 to 9.0 milliseconds
Duty Cycle 10% to 20%
Positive Direction Time
20 to 40 seconds
REVERSE PULSE CONDITIONS
Peak Current Density
300 to 800 Amperes/ft.sup.2
Pulse Time On 0.5 to 1.0 millisecond
Pulse Time Off 2.0 to 9.0 milliseconds
Duty Cycle 10% to 20%
Reverse Direction Time
1 to 5 seconds
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Gold, solder (as Pb--Sn or Bi--Sn) or even a thin overcoat of Pd may be
applied atop the dendrites formed thereby.
The resulting dendrites have a peak height of about 10 to 100 microns and a
density (dendrites per unit area) of about 200 to 500 dendrites per square
millimeter. Dendrites have a chip connect pad to dendritic pad contact
resistance of about 3 to 5 milliohms.
While the invention has been described with respect to dendrites, it is, of
course, to be understood that conical connectors may also be utilized on
the substrate or fixture. Conical connectors are described in the commonly
assigned U.S. Pat. No. 5,118,299 of Francis C. Burns, John J. Kaufman,
David E. King, and Alan D. Knight, for CONE ELECTRICAL CONTACT, the
disclosure of which is hereby incorporated herein by reference. Conical
connectors are prepared by depositing an imagable polymeric material, as
polyimide, and forming polymeric cones, as by laser ablation. The conical
connectors are then coated, e.g., e.g., with a sputter chromium adhesion
layer approximately 150 Angstroms thick, followed by sputter coating of a
Cu layer approximately 10,000 to 100,000 Angstroms thick. A nickel coating
approximately 0.1 to 1 mil thick is deposited atop the Cu, followed by a
thin Au film.
INTEGRATED CIRCUIT CHIP BURN IN TEST SYSTEM
In a preferred exemplification of the invention the system includes:
1. A burn in board with dendritic pads for connecting to C4 solder balls on
one or more integrated circuit chips to be tested;
2. A heating assembly, preferably a time versus temperature programmable
heating assembly, for heating the one or more integrated circuit chips
being tested; and
3. Sub-systems for placing the integrated circuit chip or chips on the burn
in board, and for removing the integrated circuits from the burn in board
tester at the conclusion of testing.
It is, of course, to be understood that the heating assembly, the subsystem
for inserting the integrated circuit chips, and the subsystem for removing
the integrated circuit chips at the conclusion of testing can be one unit,
fixture, tool, or element.
The burn in board has a plurality of individual pads, lands, or recesses
for temporary electrical connectivity with integrated circuit chips. Each
such pad, land, or recess has dendrites or cones, as described
hereinbelow, to pierce the thin oxide layer on each facing contact of the
integrated circuit chip, as a Pb/Sn solder ball, and provide a low contact
resistance electrical connection between the pad, land, or recess, and the
contact on the integrated circuit chip.
The chips are manually or robotically located and placed on the burn in
board so that each contact of each chip mates with a land, pad, or recess
of the burn in board.
In one embodiment of the invention the heating assembly is aligned over the
array of integrated circuit chips and lowered over the integrated circuit
chips to cover the chips, apply heat to the chips, and apply a compressive
force thereto. This application of pressure increases the heat transfer
between the heating assembly and the chips, and reduces the electrical
contact resistance between the integrated circuit chip contacts and the
burn in board.
In a preferred exemplification the heating assembly has recesses for each
integrated circuit chip. Each such recess has its sidewalls thermally
insulated to prevent loss of heat from an individual chip to adjacent
chips, thereby further increasing the severity of the test.
In a particularly preferred embodiment the burn in board itself can have
integral heating means, whereby to heat the integrated circuit chips from
both the top and bottom surfaces of the integrated circuit chip.
The temperatures may be monitored at each chip location, as well as at
various other locations to control the thermal load on a chip.
FIG. 2 is a flow chart of the method of the invention.
FIG. 3 is a schematic flow chart of the method of the invention, showing an
overview of both the general system and the process. An initially
unpopulated burn in board 11 is populated with integrated circuit chips
31, either normally configured "flip chip" bonding chips, or inverted
chips with contacts on their top surface. A heating assembly 51 is applied
to the integrated circuit chips 31 on the burn in board 11 to provide
electrical contact between the integrated circuit chips 31 and the
contacts 13 on the burn in board 11. The integrated circuit chips 31 are
then tested electrically, logically, and thermally, as described
hereinbelow. After testing the heating element 51 is removed from the
integrated circuit chips 31 and the burn in board 11 and the individual
integrated circuit chips 31 are separated into defective chips and chips
for placement on a printed circuit board, card, or other substrate.
FIG. 4 is a partial cutaway perspective view of the burn in board 11. This
shows individual dendritic contacts 13 on the surface of the burn in
board, with electrical contacts for applying test vectors to individual
contacts of the integrated circuit chip. Also shown is an optional heating
means 15, represented by a resistance heater.
FIG. 5 is a perspective view of the heating assembly 51 showing the
assembly 51 with respect to the populated burn in board 11. In the
embodiment shown in FIG. 5, the heating assembly has a board 53 with a
power cable 55, connected to individual feeder cables 57 which extend
through slots 59 to heating elements (not shown) atop the integrated
circuit chips 31.
FIG. 6 is a perspective view of the bottom surface 61 of the heating
assembly shown in FIG. 5. This view shows individual apertures 59 for the
individual integrated circuit chips 31. A heat frame 63 surrounds each
aperture 59, with a conformal heater 65 wrapped around the walls of the
aperture 57 and a conformal contact pad 67. The conformal contact pad 67
may be formed of a resilient material, optionally with heating means
contained therein.
The testing process requires initial high pressure to break through oxide
films on the connector contact surface and effect a low electrical
resistance contact, as well as sustained high pressure to avoid | | |
