A method for manufacturing a floating gate field effect transistor includes the steps of forming a plurality of first band-like insulating films over a semiconductor substrate in a parallel, spaced-apart relation and a second insulating film between the first insulating films and having a thickness smaller than that of the first insulating film, forming a plurality of first conductive layers selectively over the insulating layer and a plurality of second band-like conductive layers over the first conductive layers in a spaced-apart relation and in a direction perpendicular to the first and second insulating films, the first conductive layer having a width substantially the same as that of the second conductive layer, coating a first resist over a whole surface of a resultant structure and patterning it so as to protect a substantive source region, removing the first insulating film at those areas not covered by the first resist, removing the first resist, forming a third insulating film by a thermal oxidation, and implanting an impurity ion into an element formation area in the semiconductor substrate in a self-aligned relation to the source region of a first conductivity type and forming a first impurity region, the conductivity type of the impurity being opposite to that of the substrate.
The present invention forms a modified DDD junction structure in which a DDD structure is formed on stack gate structure side on which a floating gate and a control gate are laminated and a non-DDD structure is formed on split gate side, by forming a first impurity region through a tilt angle implanting of impurity ions at a high level of energy and then forming a second impurity region through a tilt angle implanting of impurity ions at a low level of of energy using a spacer.
A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.
A method of fabricating a semiconductor device including MOS elements comprising the steps of forming: a gate insulation layer on a semiconductor substrate; forming a gate electrode on the gate insulation layer; and implanting impurity ions into source and drain forming regions, wherein the ion implantation into said source and drain forming regions is performed in separate ion implantation steps. In at least either one of the ion implantation steps for the source forming region or for the drain forming region, a resist layer used for blocking impurities is provided with a wall extending to said gate insulation layer at a location distant from said gate electrode, said wall allowing charges to flow to the substrate. In accordance with the method provided herein, a semiconductor device having excellent data retention characteristics can be provided based on a simple process and without creating additional fabrication steps, while avoiding quality degradation of the tunnel oxide layer or the gate oxide layer resulting from charge-up at the time of ion implantation.
A process for making stacked gate memory cells which does not require the extra thermal cycle as in the conventional SAMOS process. It includes the steps of: (a) forming a silicon nitride layer on a wafer surface; (b) forming a diffusion pattern mask on the silicon nitride layer which includes a source line diffusion mask; (c) removing portions of the silicon nitride layer not covered by the diffusion pattern mask to expose a portion of the silicon substrate; (d) removing the diffusion pattern mask; (e) using the remaining portion of the silicon nitride as a mask to grow a field oxide layer in the silicon substrate; (f) forming a poly-1 layer, an interpoly dielectric layer, and a poly-2 layer on the wafer surface; (f) forming a SAMOS (self-aligned MOS) mask which contains a plurality of SAMOS strips perpendicular to the poly-1 strips, followed by SAMOS etching to form a plurality of stacked gates. The source diffusion mask is formed to have such a predetermined width that the field oxide layer is formed to contain bird beaks which merge with each other to form an interconnected field oxide bird's beak. Further, the interconnected field oxide bird's beak is formed to be thicker than the thickness of the interpoly dielectric layer so as to protect the portion of the silicon substrate not covered by the poly-1 strips from being trenched during the SAMOS etching process.
On a semiconductor substrate, a floating gate electrode composed of a first layer of polysilicon is disposed through a gate dielectric film, and the drain diffusion layer contacts with the floating gate electrode by self-alignment. The source diffusion layer is disposed to have an offset. The control gate electrode is formed through the ON film and second gate dielectric film on the floating gate electrode. The control gate electrode is formed to cover the offset region. The first gate dielectric film is formed entirely of the tunneling dielectric film at least in the region beneath the floating gate electrode. In such constitution, an electrically erasable and programmable semiconductor memory device small in cell area and excellent in matching with other process may be obtained.
