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Description  |
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TECHNICAL FIELD
The present invention relates to an equalizing method in a digital wireless
communication system operating in a plurality of non-contiguous time slots
with each slot commenced by a synchronization signal followed by a data
signal having a digitally encoded marker signal at a predetermined time
period.
BACKGROUND OF THE INVENTION
Wireless communication is well known in the art. Heretofore, one type of
wireless communication is known as a "cellular" communication wherein each
stationary unit receives and transmits signals to mobile units within its
allocated geographical region, called a cell. As mobile units move from
one cell to another, communication is transferred from one stationary unit
in one cell to another stationary unit in another cell.
Heretofore, cellular communication is analog based and has risen in
popularity. However, as a result, the airways have become increasingly
crowded and the capacity of the communication system to take on new
subscribers is becoming increasingly of a problem. Digital cellular
communication offers an opportunity to increase the number of subscribers
to operate within the cellular system. However, to bridge the gap between
the current analog cellular system and the digital cellular system, a
standard has been proposed. The standard proposed by EIA/TIA (Electronic
Industry Association/Telecommunications Industry Association), known as
the IS-54 standard, specifies that communication between a mobile unit and
a base unit should be capable of operating in both the analog and the
digital mode. More particularly, when operating in the digital wireless
communication mode, the IS-54 standard specifies that communication
between a base unit and a mobile unit occur in a Time Division Multiplex
Access (TDMA) mode. In a TDMA mode, the digitally encoded signal is
transmitted in a plurality of non-contiguous time slots. Communication
between a base unit and a mobile unit occurs in an assigned time slot,
within each frame. In each time slot, digitally encoded synchronization
signal must first be transmitted followed by the digitally encoded data
signal. Furthermore, within the digitally encoded data signal, at a
predetermined time period, a digitally encoded marker signal is
transmitted. These are all well known standards in the IS-54
specification.
One of the problems of a digital wireless communication system is the
problem of equalizing the digitally encoded signals. As the digitally
encoded signal is transmitted from one unit to another, through a
multiplicity of data paths, the various signals arriving at the other unit
can cause delay spread between the digitally encoded signals. This is
known as inter-symbol interference. An equalizer is a digital
hardware/software apparatus which corrects inter-symbol interference
between the digitally encoded signals arriving from a plurality of signal
paths.
In the prior art, a number of equalization strategies is disclosed. See,
for example, "BER Performances Of Mobile Radio Equalizer Using RLS
Algorithm In Selective Fading Environment" by Akihiro Higashi, Hiroshi
Suzuki; "Bi-Directional Equalization Technique For TDMA Communication
Systems Over Land Mobile Radio Channels" by Yow-Jong, Liu, page 1458-1462,
Globecom '91; and "Development Of Japanese Adaptive Equalization
Technology Toward High Bit Rate Data Transmission In Land Mobile
Communications" by Seiichi Sampei, page 1512-1521 IEICE Transactions,
Volume E, 74, No. 6, Jun., 1991.
Although the present invention, in the preferred embodiment, discloses a
wireless communication systems using the IS-54 standard capable of
operating in both analog and digital mode, it should be apparent that the
invention, as set forth herein, can be used in any digital, wireless,
communication system.
SUMMARY OF THE INVENTION
A method of equalizing a digitally encoded signals transmitted in a
plurality of non-contiguous time slots has a digitally encoded
synchronization signal commencing in each time slot. This is followed by a
digitally encoded data signal having a digitally encoded marker signal at
a predetermined time period in each slot. The method comprises the step of
storing the digitally encoded synchronization signal of the assigned time
slot ("first synchronization signal"), and the digitally encoded data
signal of the assigned time slot, and the digitally encoded
synchronization signal of the immediately succeeding non-assigned time
slot ("second synchronization signal"). The location of the minimum energy
point of the stored digitally encoded signals is then determined. An
equalization of the stored digitally encoded signal is then started
commencing forward from the first synchronization signal to the minimum
energy point. In addition, an equalization of the stored digitally encoded
signal begins from the end of the second synchronization signal backwards
to the minimum energy point.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block level diagram of a wireless communication unit which is a
remote unit or is a portion of a stationary unit of a digital wireless
communication system.
FIG. 2 is a block level diagram of the signal flow path when the wireless
communication unit shown in FIG. 1 is operating in the analog mode.
FIG. 3 is a block level diagram of the signal flow path when the wireless
communication unit shown in FIG. 1 is operating in a digital mode.
FIG. 4 is a detailed block level diagram of the RF unit portion of the
communication unit shown in FIG. 1.
FIG. 5 is a detailed block level diagram of the AFE portion of the
communication unit shown in FIG. 1.
FIG. 6 is a flow chart showing the operation of the software used in the
Modem DSP of the communication unit shown in FIG. 1, when the Modem DSP is
operating in the receive mode and having two modes of operation: sync
acquisition mode and steady state mode.
FIG. 7 is a functional block diagram of the Modem DSP with its software,
operating in the sync acquisition mode.
FIG. 8 is a functional block diagram of the Modem DSP with its software,
operating in the steady state mode.
FIG. 9 is a detailed functional block diagram of the timing recovery
function during the steady state mode shown in FIG. 8.
FIG. 10 is a detailed functional block diagram of the DQPSK receiver
function during the steady state mode shown in FIG. 8.
FIG. 11 is a timing diagram of the protocol of communication between like
units of FIG. 1, when operating in a digital mode.
FIG. 12 is a diagram showing the difference in energy of a signal received
by a mobile unit when moving.
FIG. 13 is a block level diagram showing the measurement of energy in a
time slot to estimate the speed of a mobile unit.
FIG. 14(a-c) are diagrams showing the methods of training an equalizer.
DETAILED DESCRIPTION OF THE DRAWINGS
Referring to FIG. 1 there is shown a schematic block level diagram of a
communication unit 10. In a wireless communication system between a mobile
unit and a stationary unit, the communication unit 10 is that of the
mobile unit. In addition, the schematic block level diagram shown in FIG.
1 represents a portion of the stationary unit. More particularly, as will
be appreciated by those having ordinary skilled in the art, the stationary
unit would comprise additional units to accomplish function such as hand
off and the ability to process many remote units at the same time.
The communication unit 10 comprises an antenna 12 which receives the RF
(radio frequency) wireless signal. The RF signal is then processed by an
RF processing unit 14. From the RF processing unit 14, the signal is then
passed to a base band processor 20. The base band processor 20 comprises
in AFE (analog front end) 22, which receives the RF signal from the RF
processing unit 14. The signal from the AFE unit 22 is then received by a
Modem DSP 24. The signal from the Modem DSP 24 is received by a VSELP DSP
26. A FPGA (Field Programmable Gate Array) 28 communicates with the Modem
DSP 24 and the VSELP DSP 26. The FPGA 28 also communicates with an audio
codec 30. In addition, the FPGA 28 is connected to a controller 32.
Finally, the audio codec 30 is connected to a conventional speaker and
microphone.
As previously discussed, the communication unit 10 in the preferred
embodiment implements the IS-54 standard. Thus, the communication unit 10
can process both analog wireless signals as well as digital by encoded
wireless signals. In general, the above-identified components operate in
the following manner:
RF processing unit 14 receives the analog or the digitally encoded RF
signal and converts them into an baseband signal for further processing by
the based band processor 20. When operating in the digital mode, the RF
processing unit 14 also demodulates the received IF signal to produce the
analog I,Q signals.
The AFE unit 22 implements analog to digital and digital to analog
conversions with associated filtering functions for the I/Q signals. In
addition, it provides for four (one not used) channel D/A for RF control.
It also has one A/D for RSSI (Receive Signal Strength Indicator)
measurement.
The Modem DSP 24 in the preferred embodiment is a digital signal processor
which is ROM coded (TMS 320c51) which implements analog mode processing,
modem functions in the digital mode, as well as FACCH (Fast Access Control
Channel)/SACCH (Slow Access Control Channel) error control functions.
FACCH/SACCH are defined by the IS-54 standard and is well known in the
art. The modem processor 24 interfaces with the FPGA I/O decoder 28
through its serial port. Through the FPGA 28, the FPGA 28 then
communicates with the controller 32. The Modem DSP 24 also maintains the
time division multiplex (TDM) bus for communication with the VSELP DSP
processor 26 and the audio codec 30 when operating in the analog mode. The
Modem DSP 24 communicates with the RF processor 14 through the AFE 22.
The VSELP DSP 26 is also a ROM coded DSP (TMS 320c51) which implements the
VSELP codec functions, which is a speech compression algorithm. In
addition, it performs error control functions associated with the speech
frame and echo cancellation. Finally, it communicates with the Modem DSP
24 via the TDM port and is powered down during the analog mode operation.
The audio codec 30 implements the speech A to D and D to A conversion and
associated filtering. It interfaces directly to the speaker and to the
microphone (not shown). The speech samples are exchanged with the Modem
DSP 24 through the TDM port and TDM to pulse code modulation (PCM)
conversion circuit in the FPGA I/O decoder 28 during the analog mode
operation. In addition, during the digital mode operation, the audio codec
30 interfaces with the VSELP DSP 26 through the PCM bus.
The FPGA I/O decoder 28 consist of a first FPGA1 28a, a second FPGA2 28d,
and a PAL (Programmable Array Logic--not shown), for I/O address decoding.
The first FPGA1 28a includes timing generation circuitry, wideband data
demodulator, sync control interface, and baseband test interface. The
second FPGA2 28b includes an interface (UPIF) to interface with the
controller 32. In addition, it communicates with the audio codec 30 and
the VSELP DSP 26 through the PCM port and has TDM/PCM conversion
circuitry. Finally, the second FPGA2 28b has a sampling clock (interrupt
control).
Referring to FIG. 2, there is shown the signal flow for the communication
unit 10 when operating in the analog mode. As can be seen, when operating
in the analog mode, the VSELP DSP 26 is completely "turned off". The
analog wireless signal is received by the RF unit 14 and is supplied to
the AFE unit 22. From the AFE unit 22, the signal is supplied to the Modem
DSP 24. The Modem DSP 24 through its TDM port communicates with the second
FPGA2 28b. From the PCM port of the second FPGA2 28b, the second FPGA2 28b
communicates with the codec 30.
Referring to FIG. 3, there is shown a block level diagram of the signal
flow when the communication unit 10 operates in the digital mode. In this
mode, the VSELP DSP 26 is actively involved in the processing of the
received digitally encoded signal.
Referring to FIG. 11, there is shown a timing diagram of a digitally
encoded signal when the communication unit 10 operates in the digital
mode, implementing in particular, the IS-54 standard. The communication
between a base unit and a mobile unit is divided into a plurality of
frames, designated as F1, F2, etc., with each frame lasting 20 msec. In
the digital mode of operation, each 20 msec. frame is further divided into
a plurality of time slots, shown as T1, T2 and T3. Using the capability of
voice compression as performed by VSELP processor 26, at full rate, 8
kbits/sec., for the same frame at the same frequency, in the digital mode,
the base unit can serve to communicate with three different mobile units.
Further, when the VSELP DSP 26 is operating at half rate compression i.e.,
4 kbits per second, communication between the base unit and a plurality of
mobile units can occur using a 40 msec. frame with each frame divided into
six different time slots or serving six users.
Each time slot Tn can accommodate the transmission of 162 symbols or 324
bits. The base unit and the mobile unit communicate over separate
frequency channels thereby accomplishing full duplex transmission. The
protocol of transmission from the base unit to the mobile unit is shown
and designated as f (for forward). The protocol of transmission from the
mobile unit to the base unit is shown and is designated as r (for
reverse). In the forward protocol, the IS-54 standard dictates that the
digitally encoded signal begins with 14 symbols of synchronization signal
followed by 148 symbols of data signal, with 6 symbols of DVCC (a marker
signal) located in the middle of the data field between symbols 85-91.
Thus, within each forward time slot, transmission of 162 symbols include
sync and data.
Referring to FIG. 4, there is shown a detailed block level diagram of the
RF processing unit 14. The RF processing unit 14 receives the signal from
the antenna 12 through a duplexer. The received signal is supplied to an
RF+IF stage 72. The RF+ IF stage 72, as is well known in the art, has an
RF filter, low noise amplifier which serves to filter and amplify the
received signal, and an RF to IF converter to convert the received RF
signal into an intermediate frequency signal. The conversion is based upon
a difference frequency signal generated by an RX frequency synthesizer 74.
The frequency selected by the RX frequency synthesizer 74 is based upon a
signal supplied from a temperature compensated crystal oscillator 70,
passing through an appropriate multiplier 78.
The output of the RF+IF stage 72 is then supplied to an amp and I/Q
demodulator 76 whose gained is selected by an automatic gain control
signal AGC. The outputs of the amp+I/Q demodulator 76 are the analog I and
analog Q signals.
In the transmit mode, the RF processing unit 14 comprises similar
components as the above. The analog I and analog Q signals are supplied to
an I/Q modulator 86, which modulates the analog I,Q signals on an IF
carrier signal. The output of the I/Q modulator 86 is then supplied to an
RF+IF stage 82. The RF+IF stage 82 converts up the output of the I/Q
modulator 86 into an RF signal for transmission by the antenna 12. The
frequency to convert from the intermediate frequency to the RF frequency
is controlled by the TX frequency synthesizer 84. The TX frequency
synthesizer 84 also receives the output of the temperature compensated
crystal oscillator 70 multiplied by an appropriate multiplier 88.
Referring to FIG. 5, there is shown a detailed block level diagram of the
AFE unit 22. The AFE unit 22 comprises a first LPF (low pass filter) 91.
The first LPF 91 receives the received analog I/Q signals from the RF unit
14. The output of the LPF 91 is then supplied to an A-to-D converter 90
from which the digital RxI and the digital RxQ signals are produced. The
A-to-D converter 90 also receives a clock signal from a clock 92. The
clock 92 is adjusted by a sampling phase adjustment signal (which will be
described hereinafter). The AFE unit 22 also comprises a D-to-A converter
118. The D-to-A converter 118 receives the transmit digital I and Q (Tx
I/Q) signals and converts them into analog Tx I/Q signals. The D-to-A
converter 118 also receives the clock signal from the clock 92. The analog
Tx I/Q signals are then supplied to a second LPF 117. The output of the
second LPF 117 is then supplied as the Tx analog I/Q signals and are
provided to the RF unit 14.
The AFE unit 22 also comprises a WBDD (wide band data demodulator) 119.
From the WBDD 119, the signal wide band data is produced. The wide band
data demodulator signal is an analog control channel. It is disclosed
herein only because the IS-54 standard requires that the communication
unit 10 can handle both analog and digital communication. It is not used
during digital communication. The AFE unit 22 also comprises a D-to-A
converter 93 which receives the control signals of Tx.sub.-- Power, AFC,
and AGC. These digital signals are converted into an analog signal and are
supplied to the RF unit 14 to control the RF unit 14. Finally, the AFE
unit 22 receives the RSSI (receive signal strength indicator) signal and
digitizes it by the A-to-D converter 95.
Referring to FIG. 6, there is shown a flowchart of the operation of the
software used in the Modem DSP 24 when the Modem DSP 24 is operating in
the received mode. When operating in the received mode, the Modem DSP 24
has two modes of operation: a sync acquisition mode, and a steady state
mode. In the sync acquisition mode, the operation occurs at the start of
each communication session. Once communication has been established, the
software proceeds into the steady state mode. There, the operation occurs
once every frame or once every 20 millisec. Further, during the steady
state, the Modem DSP 24 initially performs a timing recovery operation 42
which is shown in FIG. 9 and which will be explained in greater detail.
After the timing recovery operation 42, the Modem DSP 24 operates on the
signal shown in block level diagram form in FIG. 10 and will be discussed
in greater detail hereinafter.
Referring to FIG. 7, there is shown a detailed functional block diagram of
the sync acquisition mode of operation for the Modem DSP 24. The digital
I/Q received signals from the AFE unit 22 are supplied to a normalizing
circuit 96. The normalizing circuit 96 serves to normalize the magnitude
or the amplitude of the digitized I,Q signals from the A to D converter
90.
From the normalizing circuit 96, the digitally encoded signal is then
stored in a storage unit 98, which is just a buffer. As will be explained
hereinafter, the storage 98 stores at least 15 symbols (or 30 samples)
which is the length of the synchronization signal portion of the digitized
signal. The stored signals are then supplied to a first bank of match
filters 100. Each of the filters in the first bank 100 is adapted to
receive the digital signal from the storage 98 and to filter this digital
signal through a frequency range different from one another. Thus, the
output of the first bank of match filters 100 is a plurality of filtered
digital signals. The plurality of filtered digital signals are supplied to
a plurality of first magnitude circuits 102. Each of the plurality of
first magnitude circuits 102 determines the magnitude of the filtered
digital signal from the first bank of match filters 100. The output of the
first magnitude circuits 102 is yet another plurality of digital signals
which are supplied to a first maximum and threshold circuit detector 106.
The output of the first maximum and threshold circuit detector 106 serves
to detect the filtered digital signal having the maximum magnitude. In
addition, the first maximum and threshold circuit 106 selects the match
filter from the first bank of matched filters 100 that generated the
signal having the maximum output.
The output of the first maximum and threshold circuit 106 is supplied to a
second bank of match filters 108. Each of the filters in the second bank
of match filters 108 has a fine frequency offset from one another and
having a different filter coefficients from one another. The output of the
second bank of match filters 108 is a plurality of fine filtered digital
signals which are supplied to a second magnitude circuit 110.
The second magnitude circuit 110, similar to the first magnitude circuit
102, comprises a plurality of circuits each of which receives a fine
filtered digital signal and determines the amplitude or the magnitude
thereof. The output of the second magnitude circuit 110 is a plurality of
signals which are supplied to a second maximum and threshold circuit
detector 112. The second maximum and threshold detector 112 selects the
digital signal having the maximum amplitude as the output thereof. In
addition, the second maximum and threshold circuit 112 selects the filter
from the second bank of match filters 102, producing that output. Finally,
the output of the second maximum and threshold circuit 112 is an initial
carrier frequency offset signal to correct the carrier frequency to the
AFC (automatic frequency control), and a time slot position signal. The
time slot position signal is used internally to control the start and stop
of each subsequent frame.
Referring to FIG. 8, there is shown a block level functional diagram of the
operation of the Modem DSP 24 with the software therein when operating in
the steady state mode. In the steady state mode, the Modem DSP 24 performs
SQRC filtering function 42 and 50 (for receive and transmit) and timing
recovery 42 (for receive), DQPSK modulation 44 and 52 (again receive and
transmit respectively) and frame interleaving/De-interleaving 46 and 54
(receive and transmit respectfully), and FACCH decode and encode 48 and 56
(receive and transmit respective). In addition, the VSELP DSP 26 performs
channel decode and encoding 62 and 66 (receive and transmit, respectively)
and speech decode and encode 64 and 68 (receive and transmit
respectively).
Referring to FIG. 9, there is shown a detailed block level functional
diagram of the timing recovery function 42 performed by the Modem DSP 24
when operating in the steady state mode.
The Rx I/Q signals from the second maximum and threshold circuit detector
112 are supplied to a 1:4 interpolator 114. The output of the interpolator
114 is then supplied to a third match filter 116. The match filter 116
also receives the stored sync signal from a storage location 104. The
match filter 116 is a single filter and it matches each input sample
symbol with the stored sync signal from the storage location 104. After
each match, the input signal is shifted by T/8, or by one input sample and
then is matched again with the sync signal from the storage location 104.
Thus, the output of the match filter 116 is a signal operating at the T/8
rate. The outputs of the match filter 116 are then supplied to a peak
detector 118. The peak detector 118 receives the plurality of outputs from
the match filter 116, being supplied thereto at the T/8 rate, and
determines the output having the highest peak value. The output of the
peak detector 118 is the value imax, the use of which will be discussed
hereinafter. The output from the peak detector 118 is then supplied to a
second order phase lock loop 119. The second order phase lock loop 119 has
an internal variable AVG-POS, the use of which will be described
hereinafter in greater detail. The output of the second order phase lock
loop 119 is the sampling phase adjustment signal which is supplied to the
clock 92 of the AFE 22 shown in FIG. 5. The received digital Rx I/Q
signals at the T/2 rate are also supplied to a bank of SQRC filters 117.
The output of the second order PLL 119 is used to select the appropriate
SQRC filter from the bank of SQRC filters 117. The output of the bank of
SQRC filters 117 is then supplied to the DQPSK receiver 44.
The output of the second order PLL 119 is the signal Avg-pos(n+1). It is
supplied to the AFE unit 22 and is adjusted once every frame during the
idle period. the coefficient filter of each of the bank of SQRC filters
117 is tuned to a different sampling phase adjustment. Thus, the output of
the second order PLL 117 selects one of the coefficient filters from the
bank of SQRC filters 117.
Referring to FIG. 10 there is shown a detailed block level diagram of a
portion of the DQPSK receiver 44. The DQPSK receiver 44 receives each
symbol as the output of the timing recovery function 42. The digital Rx
I/Q symbols are supplied to a pre-processing unit 121 which generates the
control signals: speed estimation, energy calculation, and CTRL. The CTRL
signal controls the DQPSK receiver 44 in its two modes of operation. In
one mode, each symbol from the output of the timing recovery 42 is
supplied to a fine all pass filter 120. From the fine all pass filter 120,
each symbol signal is supplied to a differential detector 122. From the
differential detector 122, the symbol signal is then supplied to a phase
slicer 126 and an arc tangent processor 128.
In another mode of operation, each symbol from the timing recovery function
42 is supplied to an equalizer 124. The equalizer 124 operates on all the
symbols received during the assigned time slot. After the equalizer 124
has performed its operation (to be discussed hereinafter), each symbol is
outputted from the equalizer 124, one at a time. Each symbol signal from
the equalizer 124 is also supplied to the phase slicer 126 and at the same
time to the arc tangent processor 128.
Each of the symbol signal from the equalizer 124 or the differential
detector 122 is received simultaneously by the phase slicer 126 and the
arc tangent processor 128. The phase slicer 126 operates upon the symbol
signal by quantizing the input phase into one of a plurality of
pre-determined constellation points (i.e. 45.degree., 135.degree.,
225.degree., 315.degree. ) and generates the phase signal .crclbar.. The
arc tangent processor 128 receives the same symbol signal and serves to
operate on the symbol signal received to determine the arc tangent of its
phase. The output of the arc tangent processor 128 is the phase signal
.crclbar.. The phase signal .crclbar. and the phase signal .crclbar. are
supplied to a first subtractor (or adder with a negative input) 130 which
generates the phase error signal (.crclbar.-.crclbar.). The phase error
signal (.crclbar.-.crclbar.) is then supplied to a first multiplier 132 to
which a constant g.sub.1 is multiplied. Thereafter, the output of the
first multiplier 132 is supplied to a second adder 134 to which the
frequency signal output from a prior operation on a prior symbol was
stored in the storage 136. From the second adder 134, the adjustment to
the frequency to the next symbol or the frequency error signal, is then
generated. Thus, the frequency error signal which is generated is in
accordance with:
.DELTA.f(n+1)=.DELTA.f (n)+g.sub.1 (.crclbar.(n)-.crclbar.(n));
The output of the first adder 130 is also supplied to a second multiplier
138 to which the constant g.sub.2 is supplied. The output of the second
multiplier 138 is then supplied to a third adder 140 to which the
frequency error signal .DELTA.f(n) from a prior symbol is also supplied.
The output of the third adder 140 is supplied to a fourth adder 142 to
which the carrier phase signal from a prior bit has been supplied and
stored in storage 144. The output of the fourth adder 142 is a carrier
phase error signal and is calculated in accordance with:
o(n+1)=o(n)+g.sub.2 (.crclbar.(n)-.crclbar.(n))+.DELTA.f(n)
Operation
I. Initial Determination of Frequency and Time Slot Position
As previously discussed, the digital wireless communication unit 10 is
particular adapted for digital cellular communication wherein errors such
as rayleigh fading, intersymbol interference and carrier frequency offset
present problems. At the commencement of each communication session, the
remote unit and the base unit must necessarily establish initial frequency
and time slot position.
Referring to FIG. 7, after the IQ signals are digitized by the analog to
digital converter 90, they are normalized by the normalizing unit 96 to
retain only the phase information. The digitized I,Q samples are then
stored in a storage unit 98 or a delay line of size of 30 complex. The
size is chosen because the storage unit 98 or the delay line must contain
14 phase changes for the sync word, which is 15 symbols or 30 samples at
T/2 sampling rate.
The output of the storage unit 98 is supplied to a first bank 100 of | | |
