Wide screen television - Patent Review 5442406

What is claimed is:

1. A display system, comprising:

display means having a first format display ratio;

means for mapping an output video signal onto said display means, said output video signal representing a picture which is dimensionally adjustable on said display means by operation of said mapping means;

a plurality of video signals, each of said video signals having one of different format display ratios;

means for processing at least two of said plurality of video signals, as necessary, to be compatible with one another and with said display means;

switching means for coupling first and second ones of said video signals as inputs to said processing means;

means for selecting, as said output video signal, between: one of said first and second ones of said video signals as processed, such that said picture represented by said output video signal is a single picture display; and, a combination of said first and second ones of said video signals as processed, such that said picture represented by said output video signal is a multiple picture display; and,

means for controlling said mapping means, said processing means and said selecting means, to adjust each picture represented in said output video signal in format display ratio and image aspect ratio, during both said single and multiple picture displays.

2. The display system of claim 1, wherein said first format display ratio is a wide format display ratio.

3. The display system of claim 1, wherein one of said plurality of video signals has said first format display ratio of said display means.

4. The display system of claim 3, wherein said first format display ratio is a wide format display ratio.

5. The display system of claim 1, wherein one of said plurality of video signals has a format display ratio different from said first format display ratio of said display means.

6. The display system of claim 5, wherein said first format display ratio is a wide format display ratio.

7. The display system of claim 1, wherein two of said plurality of video signals have a format display ratio different from said first format display ratio of said display means.

8. The display system of claim 7, wherein said first format display ratio is a wide format display ratio.

9. The display system of claim 1, wherein one of said plurality of video signals has said first format display ratio of said display means and another one of said plurality of video signals has a format display ratio different from said first format display ratio of said display means.

10. The display system of claim 9, wherein said first format display ratio is a wide format display ratio.

11. The display system of claim 1, wherein said processing means comprises means for selectively cropping and means for selectively interpolating each of said first and second ones of said plurality of video signals.

12. The display system of claim 1, wherein said mapping means comprises means for generating a raster for a cathode ray tube.

13. The display system of claim 1, wherein said mapping means comprises means for generating an address matrix for a liquid crystal display.

14. The display system of claim 1, wherein said picture represented by said output video signal is independently adjustable in size in mutually perpendicular directions, said mapping means providing picture size adjustment in one of said directions and said processing means providing picture size adjustment in said other one of said directions.

15. The display system of claim 1, wherein said picture represented by said output video signal is independently adjustable in size in horizontal and vertical directions, said mapping means providing picture size adjustment in said vertical direction by controlling vertical deflection height and said processing means providing picture size adjustment in said horizontal direction by interpolation of video data samples.

16. The display system of claim 1, wherein said mapping means and said video display means are adapted for operation with noninterlaced video signals having a horizontal scanning rate of nf.sub.H, where f.sub.H is a conventional horizontal scanning rate and n is an integer, and further comprising means for converting video signals having an interlaced format and a horizontal scanning rate of f.sub.H to video signals having a noninterlaced video format and said horizontal scanning rate of nf.sub.H.

17. The display system of claim 1, further comprising second selecting means for selecting between said output video signal and an another input video signal which is coupled to said mapping means along a signal path which bypasses said processing means.

18. A display system, comprising:

display means having a generally wide format display ratio;

means for mapping an output video signal onto said display means, said output video signal representing a picture which is dimensionally adjustable on said display means by operation of said mapping means;

a plurality of video signals, each of said video signals having either a generally conventional format display ratio or said generally wide format display ratio of said display means;

first and second video processors, each including means for cropping and interpolating video signals, for respectively manipulating at least two of said plurality of video signals, as necessary;

switching means for coupling first and second ones of said video signals as inputs to said video processors;

means for selecting, as said output video signal, between: one of said first and second ones of said video signals as processed, such that said picture represented by said output video signal is a single picture display; and, a combination of said first and second ones of said video signals as processed, such that said picture represented by said output video signal is a multiple picture display; and,

means for controlling said mapping means, said first and second video processors and said selecting means, to adjust each picture represented in said output video signal in format display ratio and image aspect ratio as necessary to selectively implement a plurality of multiple picture display formats on said video display means, some of said plurality of display formats being representative of various ones of said video signals having format display ratios which are different from one another and at least one of which is different from said first format display ratio of said video display means.

19. The display system of claim 18, wherein each picture in each of said plurality of display formats is substantially without image aspect ratio distortion.

20. The display system of claim 18, wherein said plurality of display formats comprises:

a wide format display ratio main picture and an overlaid auxiliary picture having a conventional format display ratio; and,

a conventional format display ratio main picture and an overlaid auxiliary picture having a wide format display ratio.

21. The display system of claim 20, wherein each picture in each of said plurality of display formats is substantially without image aspect ratio distortion.

Description Submit all comments and votes

The invention relates to the field of televisions, for example those televisions having a wide display format ratio screen, which must interpolate video data to implement various display formats. Most televisions today have a format display ratio, horizontal width to vertical height, of 4:3. A wide format display ratio corresponds more closely to the display format ratio of movies, for example 16:9. The invention is applicable to both direct view televisions and projection televisions.

Televisions having a format display ratio of 4.3, often referred to as 4.times.3, are limited in the ways that single and multiple video signal sources can be displayed. Television signal transmissions of commercial broadcasters, except for experimental material, are broadcast with a 4.times.3 format display ratio. Many viewers find the is 4.times.3 display format less pleasing than the wider format display ratio associated with the movies. Televisions with a wide format display ratio provide not only a more pleasing display, but are capable of displaying wide display format signal sources in a corresponding wide display format. Movies "look" like movies, not cropped or distorted versions thereof. The video source need not be cropped, either when converted from film to video, for example with a telecine device, or by processors in the television.

Televisions with a wide display format ratio are also suited to a wide variety of displays for both conventional and wide display format signals, as well as combinations thereof in multiple picture displays. However, the use of a wide display ratio screen entails numerous problems. Changing the display format ratios of multiple signal sources, developing consistent timing signals from asynchronous but simultaneously displayed sources, switching between multiple sources to generate multiple picture displays, and providing high resolution pictures from compressed data signals are general categories of such problems. Such problems are solved in a wide screen television according to this invention. A wide screen television according to various inventive arrangements is capable of providing high resolution, single and multiple picture displays, from single and multiple sources having similar or different format ratios, and with selectable display format ratios.

Televisions with a wide display format ratio can be implemented in television systems displaying video signals both at basic or standard horizontal scanning rates and multiples thereof, as well as by both interlaced and noninterlaced scanning. Standard NTSC video signals, for example, are displayed by interlacing the successive fields of each video frame, each field being generated by a raster scanning operation at a basic or standard horizontal scanning rate of approximately 15,734 Hz. The basic scanning rate for video signals is variously referred to as f.sub.H, 1 f.sub.H, and 1H. The actual frequency of a 1f.sub.H signal will vary according to different video standards. In accordance with efforts to improve the picture quality of television apparatus, systems have been developed for is displaying video signals progressively, in a noninterlaced fashion. Progressive scanning requires that each displayed frame must be scanned in the same time period allotted for scanning one of the two fields of the interlaced format. Flicker free AA-BB displays require that each field be scanned twice, consecutively. In each case, the horizontal scanning frequency must be twice that of the standard horizontal frequency. The scanning rate for such progressively scanned or flicker free displays is variously referred to as 2f.sub.H and 2H. A 2f.sub.H scanning frequency according to standards in the United States, for example, is approximately 31,468 Hz.

A wide screen television according to the inventive arrangements taught herein has all of the capabilities and advantages described above. A video display has a first format display ratio, for example 16.times.9. A mapping circuit maps an adjustable picture display are on the video display. First and second signal processors generate first and second selectively interpolated video signals from input video signals having one of different format display ratios, for example 4.times.3 and 16.times.9. The interpolation of the input video signals can result in expansion or compression of the input video signals. The first and second signal processors can also selectively crop the input video signals. Overall, the input video signals can be selectively cropped, interpolated, both cropped and interpolated and neither cropped nor interpolated. A switching circuit selectively couples video signal sources as the input video signals. A synchronizing circuit synchronizes the first and second signal processors with the mapping circuit. A selecting circuit selects as an output video signal between one of the first and second processed video signals and a combination of the first and second processed video signals. A control circuit controls the mapping circuit, the first and second signal processors and the selecting circuit to adjust in format display ratio and image aspect ratio each picture represented in the output video signal. One of the different format display ratios of the input video signals can be the same as the first format display ratio of the video display. The mapping circuit can comprise a raster generating circuit for a cathode ray tube or an address matrix generator for a liquid crystal display. The display system may further comprise a circuit for converting interlaced video signals to a noninterlaced format, two internal tuners and a plurality of external jacks. In one inventive arrangement, the picture display area is adjustable only vertically and the first and second signal processing circuits interpolate the video signals only horizontally.

FIGS. 1(a)-1(i) are useful for explaining different display formats of a wide screen television.

FIG. 2 is a block diagram of a wide screen television in accordance with aspects of this invention and adapted for operation at 2f.sub.H horizontal scanning.

FIGS. 3 is a block diagram of the wide screen processor shown in FIG. 2.

FIG. 4(a) is a block diagram of a wide screen television in accordance with aspects of this invention and adapted for operation at 1f.sub.H horizontal scanning.

FIG. 4(b) is a block diagram of a wide screen television in accordance with aspects of this invention and adapted for operation with a liquid crystal display system.

FIG. 5 is a block diagram of the wide screen processor shown in FIG. 4.

FIG. 6 is a block diagram showing further details of the wide screen processor common to FIGS. 3 and 5.

FIG. 7 is a block diagram of the picture-in-picture processor shown in FIG. 6.

FIG. 8 is a block diagram of the gate array shown in FIG. 6 and illustrating the main, auxiliary and output signal paths.

FIGS. 9 and 10 are timing diagrams useful for explaining the generation of the display format shown in FIG. 1(d), using fully cropped signals.

FIG. 11(a) is a block diagram showing the main signal path of FIG. 8 in more detail.

FIG. 11(b) illustrates waveforms useful for explaining video compression in the main signal path of FIG. 11(a).

FIG. 11(c) illustrates waveforms useful for explaining video expansion in the main signal path of FIG. 11(a).

FIG. 11(d) illustrates a circuit for generating write and read enable signals.

FIG. 12 is a block diagram showing the auxiliary signal path of FIG. 8 in more detail.

FIG. 13 is a block diagram of an alternative main signal path.

FIG. 14 is a block diagram of the the timing and control section of the picture-in-picture processor of FIG. 7.

FIG. 15, FIG. 16 and FIG. 17 are block diagrams of the decimation section of the timing and control section shown in FIG. 14.

FIG. 18 is a table of values used for controlling the decimation section shown in FIGS. 10-12.

FIGS. 19(a) and 19(b) are block diagrams of fully programmable, general purpose decimation circuits for controlling horizontal and vertical compression ratios respectively.

FIG. 20 is a block diagram of the interlaced to progressive scanning conversion circuit shown in FIG. 2.

FIG. 21 is a block diagram of the noise reduction circuit shown in FIG. 20.

FIG. 22 is a combination block and circuit diagram for the deflection circuit shown in FIG. 2.

FIG. 23 is a timing diagram useful for explaining implementation of vertical panning.

FIGS. 24(a)-24(c) are diagrams of display formats useful for explaining the timing diagram of FIG. 23.

FIG. 25 is a block diagram of the RGB interface shown in FIG. 2.

FIG. 26 is a block diagram of the RGB to Y, U, V converter shown in FIG. 25.

FIG. 27 is a block diagram of a circuit for generating the internal 2f.sub.H signal in the 1f.sub.H to 2f.sub.H conversion.

FIG. 28 is a different block diagram of a portion of the auxiliary signal path shown in FIG. 8.

FIG. 29 is a diagram of a five line FIFO line memory useful for explaining avoidance of read/write pointer collisions.

FIG. 30 is a block diagram of a simplified circuit for implementing an auxiliary path synchronizing circuit for the gate array.

FIG. 31 is a timing diagram illustrating the correspondence of an upper/lower field indicator to the horizontal lines of a video frame.

FIGS. 32-34 are useful for explaining a method for maintaining interlace integrity for simultaneously displayed video signals exhibiting relative precession.

FIGS. 35(a)-35(c) are waveforms useful for explaining the operation of the circuit shown in FIG. 36.

FIG. 36 is a block diagram of a circuit for maintaining interlace integrity as explained in connection with FIGS. 31-35.

FIG. 37 is a diagram useful for explaining memory mapping in the video RAM associated with the picture-in-picture processor.

FIG. 38 is a block diagram of a circuit for controlling output switching between main and auxiliary video signals.

FIGS. 39 and 40 are a block diagrams for 1-bit dithering and dedithering circuits respectively, for implementing the resolution processing circuits of FIG. 6 and FIG. 8.

FIGS. 41 and 42 are a block diagrams for 2-bit dithering and dedithering circuits respectively, for implementing the resolution processing circuits of FIG. 6 and FIG. 8.

FIG. 43 is a table useful for explaining a skewing scheme for enhancing operation of dithering circuits.

FIG. 44 is a table useful for explaining yet another alternative for implementing the resolution processing circuits of FIG. 6 and FIG. 8.

FIGS. 45 and 46 are diagrams useful for explaining operation of an automatic letterbox detector.

FIG. 47 is a block diagram of an automatic letterbox detector as explained in connection with FIGS. 45-46.

FIG. 48 is a block diagram of an alternative circuit for implementing an automatic letterbox detector.

FIG. 49 is a block diagram of a vertical size control circuit including an automatic letterbox detector.

FIGS. 50(a)-50(f) illustrate waveforms useful for explaining the analog to digital conversion of the color components of the main video signal.

FIGS. 51(a)-51(b) illustrate waveforms useful for explaining skewing of luminance and color components in the main signal path of the gate array.

FIGS. 52(a) and 52(b) illustrate portions of the main signal path for the luminance and color components respectively, for implementing video compression.

FIG. 53(a)-53(l) are useful for explaining video compression of the color components in relation to the luminance components.

FIGS. 54(a) and 54(b) illustrate portions of the main signal path for the luminance and color components respectively, for implementing video expansion.

FIGS. 55(a)-55(l) are useful for explaining video expansion of the color components in relation to the luminance components.

FIGS. 56 and 57 are pixel diagrams useful for explaining the operation of two-stage variable interpolation filters, as may be used to implement the interpolators of FIGS. 8, 11(a), and 12.

FIG. 58 is a block diagram of a two stage compensated variable interpolation filter.

FIG. 59 is a block diagram of a two stage compensated variable interpolation filter configured for implementing a zoom feature.

FIG. 60 is a block diagram of a circuit for implementing an eight tap, two stage interpolation filter.

FIG. 61 is a block diagram of a 1/16 or 1/32 resolution interpolator.

FIG. 62 is a table of K and C values for the interpolator shown in FIG. 61.

FIG. 63 is a block diagram of a circuit for determining the values of C from the values of K.

FIG. 64 is a table of values as calculated by the circuit of FIG. 62.

FIG. 65 is a block diagram of an alternative circuit for determining the values of C from the values of K.

FIG. 66 is a block diagram of another alternative circuit for determining the values of C from the values of K.

FIG. 67 is a graph of curves showing the frequency response of a conventional two stage, four point interpolator.

FIG. 68 is a table and FIG. 69 is a graph, together illustrating the frequency response of an eight point interpolator.

FIG. 70 is a block diagram of an eight point interpolator having a frequency response corresponding to FIGS. 68 and 69.

The various parts of FIG. 1 illustrate some, but not all of the various combinations of single and multiple picture display formats which can be implemented according to different inventive arrangements. Those selected for illustration are intended to facilitate the description of particular circuits comprising wide screen televisions according to the inventive arrangements. For purposes of convenience in illustration and discussion herein, a conventional display format ratio of width to height for a video source or signal is generally deemed to be 4.times.3, whereas a wide screen display format ratio of width to height for a video source or signal is generally deemed to be 16.times.9. The inventive arrangements are not limited by these definitions.

FIG. 1(a) illustrates a television, direct view or projection, having a conventional format display ratio of 4.times.3 . When a 16.times.9 format display ratio picture is transmitted, as a 4.times.3 format display ratio signal, black bars appear at the top and at the bottom. This is commonly referred to as letterbox format. In this instance, the viewed picture is rather small with respect to the entire available display area. Alternatively, the 16.times.9 format display ratio source is converted prior to transmission, so that it will fill the vertical extent of a viewing surface of 4.times.3 format display. However, much information will be cropped from the left and/or right sides. As a further alternative, the letterbox picture can be expanded vertically but not horizontally, whereby the resulting picture will evidence distortion by vertical elongation. None of the three alternatives is particularly appealing.

FIG. 1(b) shows a 16.times.9 screen. A 16.times.9 format display ratio video source would be fully displayed, without cropping and without distortion. A 16.times.9 format display ratio letterbox picture, which is itself in a 4.times.3 format display ratio signal, can be progressively scanned by line doubling or line addition, so as to provide a larger display with sufficient vertical resolution. A wide screen television in accordance with this invention can display such a 16.times.9 format display ratio signal whether the main source, the auxiliary source or an external RGB source.

FIG. 1(c) illustrates a 16.times.9 format display ratio main signal in which a 4.times.3 format display ratio inset picture is displayed. If both the main and auxiliary video signals are 16.times.9 format display ratio sources, the inset picture can also have a 16.times.9 format display ratio. The inset picture can be displayed in many different positions.

FIG. 1(d) illustrates a display format, wherein the main and auxiliary video signals are displayed with the same size picture. Each display area has an format display ratio of 8.times.9, which is of course different from both 16.times.9 and 4.times.3 . In order to show a 4.times.3 format display ratio source in such a display area, without horizontal or vertical distortion, the signal must be cropped on the left and/or right sides. More of the picture can be shown, with less cropping, if some aspect ratio distortion by horizontal squeezing of the picture is tolerated. Horizontal squeezing results in vertical elongation of objects in the picture. The wide screen television according to this invention can provide any mix of cropping and aspect ratio distortion from maximum cropping with no aspect ratio distortion to no cropping with maximum aspect ratio distortion.

Data sampling limitations in the auxiliary video signal processing path complicate the generation of a high resolution picture which is as large in size as the display from the main video signal. Various methods can be developed for overcoming these complications.

FIG. 1(e) is a display format wherein a 4.times.3 format display ratio picture is displayed in the center of a 16.times.9 format display ratio screen. Dark bars are evident on the right and left sides.

FIG. 1(f) illustrates a display format wherein one large 4.times.3 format display ratio picture and three smaller 4.times.3 format display ratio pictures are displayed simultaneously. A smaller picture outside the perimeter of the large picture is sometimes referred to as a POP, that is a picture-outside-picture, rather than a PIP, a picture-in-picture. The terms PIP or picture-in-picture are used herein for both display formats. In those circumstances where the wide screen television is provided with two tuners, either both internal or one internal and one external, for example in a video cassette recorder, two of the displayed pictures can display movement in real time in accordance with the source. The remaining pictures can be displayed in freeze frame format. It will be appreciated that the addition of further tuners and additional auxiliary signal processing paths can provide for more than two moving pictures. It will also be appreciated that the large picture on the one hand, and the three small pictures on the other hand, can be switched in position, as shown in FIG. 1(g).

FIG. 1(h) illustrates an alternative wherein the 4.times.3 format display ratio picture is centered, and six smaller 4.times.3 format display ratio pictures are displayed in vertical columns on either side. As in the previously described format, a wide screen television provided with two tuners can provide two moving pictures. The remaining eleven pictures will be in freeze frame format.

FIG. 1(i) shows a display format having a grid of twelve 4.times.3 format display ratio pictures. Such a display format is particularly appropriate for a channel selection guide, wherein each picture is at least a freeze frame from a different channel. As before, the number of moving pictures will depend upon the number of available tuners and signal processing paths.

The various formats shown in FIG. 1 are illustrative, and not limiting, and can be implemented by wide screen televisions shown in the remaining drawings and described in detail below.

An overall block diagram for a wide screen television in accordance with inventive arrangements, and adapted to operate with 2f.sub.H horizontal scanning, is shown in FIG. 2 and generally designated 10. The television 10 generally comprises a video signals input section 20, a chassis or TV microprocessor 216, a wide screen processor 30, a 1f.sub.H to 2f.sub.H converter 40, a deflection circuit 50, an RGB interface 60, a YUV to RGB converter 240, kine drivers 242, direct view or projection tubes 244 and a power supply 70. The grouping of various circuits into different functional blocks is made for purposes of convenience in description, and is not intended as limiting the physical position of such circuits relative to one another.

The video signals input section 20 is adapted for receiving a plurality of composite video signals from different video sources. The video signals may be selectively switched for display as main and auxiliary video signals. An RF switch 204 has two antenna inputs ANT1 and ANT 2. These represent inputs for both off-air antenna reception and cable reception. The RF switch 204 controls which antenna input is supplied to a first tuner 206 and to a second tuner 208. The output of first tuner 206 is an input to a one-chip 202, which performs a number of functions related to tuning, horizontal and vertical deflection and video controls. The particular one-chip shown is industry designated type TA7730. The baseband video signal VIDEO OUT developed in the one-chip and resulting from the signal from first tuner 206 is an input to both video switch 200 and the TV1 input of wide screen processor 30. Other baseband video inputs to video switch 200 are designated AUX1 and AUX 2. These might be used for video cameras, laser disc players, video tape players, video games and the like. The output of the video switch 200, which is controlled by the chassis or TV microprocessor 216 is designated SWITCHED VIDEO. The SWITCHED VIDEO is another input to wide screen processor 30.

With further reference to FIG. 3, a switch SW1 wide screen processor selects between the TV1 and SWITCHED VIDEO signals as a SEL COMP OUT video signal which is an input to a Y/C decoder 210. The Y/C decoder 210 may be implemented as an adaptive line comb filter. Two further video sources S1 and S2 are also inputs to the Y/C decoder 210. Each of S1 and S2 represent different S-VHS sources, and each consists of separate luminance and chrominance signals. A switch, which may be incorporated as part of the Y/C decoder, as in some adaptive line comb filters, or which may be implemented as a separate switch, is responsive to the TV microprocessor 216 for selecting one pair of luminance and chrominance signals as outputs designated Y.sub.-- M and C.sub.-- IN respectively. The selected pair of luminance and chrominance signals is thereafter considered the main signal and is processed along a main signal path. Signal designations including .sub.-- M or .sub.-- MN refer to the main signal path. The chrominance signal C.sub.-- IN is redirected by the wide screen processor back to the one-chip, for developing color difference signals U.sub.-- M and V.sub.-- M. In this regard, U is an equivalent designation for (R-Y) and V is an equivalent designation for (B-Y). The Y.sub.-- M, U.sub.-- M, and V.sub.-- M signals are converted to digital form in the wide screen processor for further signal processing.

The second tuner 208, functionally defined as part of the wide screen processor 30, develops a baseband video signal TV2. A switch SW2 selects between the TV2 and SWITCHED VIDEO signals as an input to a Y/C decoder 220. The Y/C decoder 220 may be implemented as an adaptive line comb filter. Switches SW3 and SW4 select between the luminance and chrominance outputs of Y/C decoder 220 and the luminance and chrominance signals of an external video source, designated Y.sub.-- EXT and C.sub.-- EXT respectively. The Y.sub.-- EXT and C.sub.-- EXT signals correspond to the S-VHS input S1. The Y/C decoder 220 and switches SW3 and SW4 may be combined, as in some adaptive line comb filters. The output of switches SW3 and SW4 is thereafter considered the auxiliary signal and is processed along an auxiliary signal path. The selected luminance output is designated Y.sub.-- A. Signal designations including .sub.-- A, .sub.-- AX and .sub.-- AUX refer to the auxiliary signal path. The selected chrominance is converted to color difference signals U.sub.-- A and V.sub.-- A. The Y.sub.-- A, U.sub.-- A and V.sub.-- A signals are converted to digital form for further signal processing. The arrangement of video signal source switching in the main and auxiliary signal paths maximizes flexibility in managing the source selection for the different parts of the different picture display formats.

A composite synchronizing signal COMP SYNC, corresponding to Y.sub.-- M is provided by the wide screen processor to a sync separator 212. The horizontal and vertical synchronizing components H and V respectively are inputs to a vertical countdown circuit 214. The vertical countdown circuit develops a VERTICAL RESET signal which is directed into the wide screen processor 30. The wide screen processor generates an internal vertical reset output signal INT VERT RST OUT directed to the RGB interface 60. A switch in the RGB interface 60 selects between the internal vertical reset output signal and the vertical synchronizing component of the external RGB source. The output of this switch is a selected vertical synchronizing component SEL.sub.-- VERT.sub.-- SYNC directed to the deflection circuit 50. Horizontal and vertical synchronizing signals of the auxiliary video signal are developed by sync separator 250 in the wide screen processor.

The 1f.sub.H to 2f.sub.H converter 40 is responsible for converting interlaced video signals to progressively scanned noninterlaced signals, for example one wherein each horizontal line is displayed twice, or an additional set of horizontal lines is generated by interpolating adjacent horizontal lines of the same field. In some instances, the use of a previous line or the use of an interpolated line will depend upon the level of movement which is detected between adjacent fields or frames. The generation of 2f.sub.H timing signals is shown more fully in FIG. 27. The converter circuit 40 operates in conjunction with a video RAM 420. The video RAM may be used to store one or more fields of a frame, to enable the progressive display. The converted video data as Y.sub.-- 2f.sub.H U.sub.-- 2f.sub.H and V.sub.-- 2f.sub.H signals is supplied to the RGB interface 60.

The RGB interface 60, shown in more detail in FIG. 25, enables selection of the converted video data or external RGB video data for display by the video signals input section. The external RGB signal is deemed to be a wide format display ratio signal adapted for 2f.sub.H scanning. The vertical synchronizing component of the main signal is supplied to the RGB interface by the wide screen processor as INT VERT RST OUT, enabling a selected vertical sync (f.sub.Vm or f.sub.Vext) to be available to the deflection circuit 50. Operation of the wide screen television enables user selection of an external RGB signal, by generating an internal/external control signal INT/EXT. However, the selection of an external RGB signal input, in the absence of such a signal, can result in vertical collapse of the raster, and damage to the cathode ray tube or projection tubes. Accordingly, the RGB interface circuit detects an external synchronizing signal, in order to override the selection of a non-existent external RGB input. The WSP microprocessor 340 also supplies color and tint controls for the external RGB signal.

The wide screen processor 30 comprises a picture in picture processor 320 for special signal processing of the auxiliary video signal. The term picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. A gate array 300 combines the main and auxiliary video signal data in a wide variety of display formats, as shown by the examples of FIGS. 1(b) through 1(i). The picture-in-picture processor 320 and gate array 300 are under the control of a wide screen microprocessor (WSP .mu.P) 340. Microprocessor 340 is responsive to the TV microprocessor 216 over a serial bus, The serial bus includes four signal lines, for data, clock signals, enable signals and reset signals. The wide screen processor 30 also generates a composite vertical blanking/reset signal, as a three level sandcastle signal. Alternatively, the vertical blanking and reset signals can be generated as separate signals. A composite blanking signal is supplied by the video signal input section to the RGB interface.

The deflection circuit 50, shown in more detail in FIG. 22, receives a vertical reset signal from the wide screen processor, a selected 2f.sub.H horizontal synchronizing signal from the RGB interface 60 and additional control signals from the wide screen processor. These additional control signals relate to horizontal phasing, vertical size adjustment and east-west pin adjustment. The deflection circuit 50 supplies 2f.sub.H flyback pulses to the wide screen processor 30, the 1f.sub.H to 2f.sub.H converter 40 and the YUV to RGB converter 240.

Operating voltages for the entire wide screen television are generated by a power supply 70 which can be energized by an AC mains supply.

The wide screen processor 30 is shown in more detail in FIG. 3. The principal components of the wide screen processor are a gate array 300, a picture-in-picture circuit 301, analog to digital and digital to analog converters, the second tuner 208, a wide screen processor microprocessor 340 and a wide screen output encoder 227. Further details of the wide screen processor, which are in common with both the 1f.sub.H and the 2f.sub.H chassis, for example the PIP circuit, are shown in FIG. 6. A picture-in-picture processor 320, which forms a significant part of the PIP circuit 301, is shown in more detail in FIG. 7. The gate array 300 is shown in more detail in FIG. 8. A number of the components shown in FIG. 3, forming parts of the main and auxiliary signal paths, have already been described in detail.

The second tuner 208 has associated therewith an IF stage 224 and an audio stage 226. The second tuner 208 also operates in conjunction with the WSP .mu.P 340. The WSP .mu.P 340 comprises an input output I/O section 340A and an analog output section 340B. The I/O section 340A provides tint and color control signals, the INT/EXT signal for selecting the external RGB video source and control signals for the switches SW1 through SW6. The I/O section also monitors the EXT SYNC DET signal from the RGB interface to protect the deflection circuit and cathode ray tube(s). The analog output section 340B provides control signals for vertical size, east-west adjust and horizontal phase, through respective interface circuits 254, 256 and 258.

The gate array 300 is responsible for combining video information from the main and auxiliary signal paths to implement a composite wide screen display, for example one of those shown in the different parts of FIG. 1. Clock information for the gate array is provided by phase locked loop 374, which operates in conjunction with low pass filter 376. The main video signal is supplied to the wide screen processor in analog form, and Y U V format, as signals designated Y.sub.-- M, U.sub.-- M and V.sub.-- M. These main signals are converted from analog to digital form by analog to digital converters 342 and 346, shown in more detail in FIG. 4.

The color component si