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Claims  |
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We claim:
1. A programmable refresh circuit integrated with a semiconductor memory
device having a memory array accessed through word lines and bit lines,
said programmable refresh circuit comprising:
a self-timed oscillator that outputs a clocking signal;
programmable pattern generating means for generating a first signal
pattern;
counter means connected to receive the clocking signal output from the
self-timed oscillator and the first signal pattern generated by the
programmable pattern generating means, said counter means having a count
driven by said clocking signal and outputting a signal pulse upon the
count reaching a digital pattern representation corresponding to the first
signal pattern generated by said programmable pattern generating means;
and
refresh control logic connected to said counter means for receiving the
signal pulse output therefrom, said refresh control logic responding
thereto by refreshing a portion of the memory array of the semiconductor
memory device, wherein output of multiple signal pulses from the counter
means defines a refresh rate at which the memory array is refreshed, said
refresh control logic further including means for disabling refreshing of
the memory array for a programmable "wait state interval" subsequent to
said refresh control logic receiving from a control system connected to
the semiconductor memory device a signal initiating self-refresh, and
means for enabling refreshing of the memory array subsequent to said wait
state interval.
2. The programmable refresh circuit of claim 1, wherein the semiconductor
device receives a row address strobe (RAS) signal and a column address
strobe (CAS) signal from the control system connected thereto, and wherein
the signal initiating self-refresh comprises a CAS before RAS transition
of signals received from the control systems.
3. The programmable refresh circuit of claim 1, wherein the programmable
pattern generating means includes means for generating a second signal
pattern, and wherein said refresh control logic is connected to receive
the second signal pattern generated by the programmable pattern generating
means, and wherein the refresh control logic includes comparing means for
comparing a portion of the digital pattern representation of the count of
the counter means with the second signal pattern generated by the
programmable pattern generating means to determine the wait state interval
subsequent to initiation of refresh.
4. The programmable refresh circuit of claim 3, wherein said programmable
pattern generating means comprises a first bank of fuses for generating
the first signal pattern used to program the refresh rate and a second
bank of fuses for generating the second signal pattern used to program the
wait state interval.
5. The programmable refresh circuit of claim 3, wherein the counter means
includes a single counter coupled to the self-timed oscillator, said
single counter containing the count driven by said clocking signal.
6. A memory system comprising:
a memory device including a memory array accessed through word lines and
bit lines; and
a refresh circuit integrated with the memory array, said refresh circuit
including
a self-timed oscillator that outputs a clocking signal,
a programmable non-volatile frequency divider coupled to receive said
clocking signal and output therefrom multiple successive reset pulse
signals based upon a programmed frequency division, and
refresh control logic connected to the programmable non-volatile frequency
divider for receiving the multiple successive reset pulse signals output
therefrom, said refresh control logic responding to each reset pulse
signal by refreshing a portion of the memory array, wherein output of said
multiple successive reset pulse signals from the programmable non-volatile
frequency divider defines a refresh rate at which the memory array is
refreshed as an interval of time between any two successive reset pulse
signals of the multiple successive reset pulse signals, said refresh
control logic further including means for disabling refreshing of the
memory array for a programmable "wait state interval" subsequent to said
refresh control logic receiving from a control system connected to the
semiconductor memory device a signal initiating self-refresh, and means
for enabling refreshing of the memory array subsequent to said wait state
interval.
7. The memory system of claim 6, wherein said memory system comprises a
semiconductor memory chip.
8. A programmable refresh circuit integrated with a semiconductor memory
device having a memory array accessed through word lines and bit lines,
said programmable refresh circuit comprising:
a self-timed oscillator that outputs a clocking signal;
programmable pattern generating means for generating a first signal
pattern;
counter means connected to receive the clocking signal output from the
self-timed oscillator and the first signal pattern generated by the
programmable pattern generating means, said counter means having a count
driven by said clocking signal and outputting a signal pulse upon the
count reaching a digital pattern representation corresponding to the first
signal pattern generated by the programmable pattern generating means,
said counter means including a counter containing the count and a refresh
rate comparing means coupled thereto, said counter receiving the clocking
signal output from the self-timed oscillator, said refresh rate comparing
means comprising means for comparing the count of the counter with the
first signal pattern generated by the programmable pattern generating
means and for outputting the signal pulse when the digital pattern
representation of the count corresponds to the first signal pattern
generated by the programmable pattern generating means; and
refresh control logic connected to said counter means for receiving the
signal pulse output therefrom, said refresh control logic responding
thereto by refreshing a portion of the memory array of the semiconductor
memory device, wherein output of multiple signal pulses from the counter
means defines a refresh rate at which the memory array is refreshed.
9. The programmable refresh circuit of claim 8, further comprising means
for resetting said counter means upon output of the signal pulse to the
refresh control logic.
10. The programmable refresh circuit of claim 8, wherein the self-timed
oscillator outputs two non-overlapping clocking signals to the counter
means, and wherein the count of the counter means is driven by both of
said two non-overlapping clocking signals.
11. The programmable refresh circuit of claim 10, wherein the counter means
includes a divide by N counter connected to receive the two
non-overlapping clock signals output from the self-timed oscillator,
wherein N is an integer.
12. A programmable refresh circuit integrated with a semiconductor memory
device having a memory array accessed through word lines and bit lines,
said semiconductor memory device further including a row address strobe
(RAS) clock generator and a column address strobe (CAS) clock generator,
said RAS clock generator having a RAS buffer coupled to receive a RAS
signal from an external control system connected to the semiconductor
memory device and said CAS clock generator having a CAS buffer connected
to receive a CAS signal from the external control system connected to the
semiconductor memory device, said programmable refresh circuit being
coupled to the RAS buffer and to the CAS buffer, said programmable refresh
circuit comprising:
a self-timed oscillator that outputs a clocking signal;
programmable pattern generating means for generating a first signal
pattern;
counter means connected to receive the clocking signal output from the
self-timed oscillator and the first signal pattern generated by the
programmable pattern generating means, said counter means having a count
driven by said clocking signal and outputting a signal pulse upon the
count reaching a digital pattern representation corresponding to the first
signal pattern generated by said programmable pattern generating means;
and
refresh control logic connected to said counter means for receiving the
signal pulse output therefrom, said refresh control logic responding
thereto by refreshing a portion of the memory array of the semiconductor
memory device, wherein output of multiple signal pulses from the counter
means defines a refresh rate at which the memory array is refreshed, said
refresh control logic further including means for controlling the RAS
buffer and the CAS buffer to ignore a RAS signal and CAS signal input
thereto, respectively, during self-refreshing of a portion of the memory
array of the semiconductor memory device.
13. A memory system comprising:
a memory device including a memory array accessed through word lines and
bit lines; and
a refresh circuit integrated with a memory array, said refresh circuit
including:
a self-timed oscillator that outputs a clocking signal,
programmable pattern generating means for generating a first signal
pattern,
counter means connected to receive the clocking signal output from the
self-timed oscillator and the first signal pattern generated by the
programmable pattern generating means, said counter means having a count
driven by said clocking signal and outputting a signal pulse upon the
count reaching a digital pattern representation corresponding to the first
signal pattern generated by the programmable pattern generating means,
said counter means including a counter containing the count and a refresh
rate comparing means coupled thereto, said counter receiving the clocking
signal output from the self-timed oscillator, said refresh rate comparing
means comprising means for comparing the count of the counter with the
first signal pattern generated by the programmable pattern generating
means and for outputting the signal pulse when the digital pattern
representation of the count corresponds to the first signal pattern
generated by the programmable pattern generating means, and
refresh control logic connected to said counter means for receiving the
signal pulse output therefrom, said refresh control logic responding
thereto by refreshing a portion of the memory array of the memory device,
wherein output of multiple signal pulses from the counter means defines a
refresh rate at which the memory array is refreshed.
14. A memory system comprising:
a memory device including a memory array accessed through word lines and
bit lines, said memory device further including a row address strobe (RAS)
clock generator and a column address strobe (CAS) clock generator, said
RAS clock generator having a RAS buffer coupled to receive a RAS signal
from an external control system connected to the memory device and said
CAS clock generator having a CAS buffer connected to receive a CAS signal
from the external control system connected to the memory device; and
a refresh circuit integrated with the memory device, said refresh circuit
including
a self-timed oscillator that outputs a clocking signal,
programmable pattern generating means for generating a first signal
pattern,
counter means connected to receive the clocking signal output from the
self-timed oscillator and the first signal pattern generated by the
programmable pattern generating means, said counter means having a count
driven by said clocking signal and outputting a signal pulse upon the
count reaching a digital pattern representation corresponding to the first
signal pattern generated by the programmable pattern generating means, and
refresh control logic connected to said counter means for receiving the
signal pulse output therefrom, said refresh control logic responding
thereto by refreshing a portion of the memory array of the semiconductor
memory device, wherein output of multiple signal pulses from the counter
means defines a refresh rate at which the memory array is refreshed, said
refresh control logic further including means for controlling the RAS
buffer and the CAS buffer to ignore a RAS signal and a CAS signal input
thereto, respectively, during self-refreshing of a portion of the memory
array of the memory device. |
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Claims |
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Description |
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TECHNICAL FIELD
The present invention relates in general to semiconductor memory devices
and to testing methods therefore, and in particular, to a programable
self-timed refresh circuit for a memory device, such as a random access
memory (RAM), and to methods for "non-invasively" and deterministically
testing the self-timed refresh circuit; for establishing/verifying a
refresh rate and a wait state interval for the self-timed refreshing of
the memory device.
BACKGROUND ART
Each memory cell in a memory array of a dynamic random access memory (DRAM)
structure includes a charge-storage capacitor element and a MOSFET
controlling input into and output from the capacitor element. Stored
information is represented by the charge across the capacitor element.
This charge decays over time due to MOSFET leakage current and to charge
recombination on the surface of the semiconductor substrate. Therefore, a
process of periodically "refreshing" stored information is required. For
accomplishing refresh processing at high efficiency, a number of refresh
modes have been developed. One common technique is referred to as the "CAS
(Column Address Strobe) Before RAS (Row Address Strobe)" (CBR) refresh
mode in which start of refresh is signalled by switching the timing order
of the system generated RAS and CAS signals from that of a normal
operating mode.
To enhance versatility, a "sleep mode" is designed into many random access
memories. An externally applied CAS before RAS transition thus initiates
sleep mode and thus self-refreshing of the memory array. Self-timed
refreshing of the memory array typically utilizes a Row Address Counter
(RAC), also referred to as a RAC counter, to track refreshing of the
memory array and the mode is maintained as long as the system generated
RAS signal is held constant.
Implementation of an integrated, self-timed refresh circuit within a
semiconductor memory device raises three concerns. First, with any refresh
circuit implementation it is highly desirable to maintain specified
product timing parameters so that performance of the memory device does
not deteriorate. Second, data integrity of the memory device must be
maintained by compensating self-timed refresh intervals with changes in
process and operating conditions. For example, if temperature increases,
the memory cells become leakier and, thus, it is desirable to refresh the
memory array more often. Third, "non-invasive" functional verification of
memory device performance is desired, which also minimizes test time.
Presently, there is no known self-timed refresh circuit and testing method
which adequately address all of these concerns.
Thus, a novel, programmable self-timed refresh circuit for integrating with
a random access memory, which is susceptible to "non-invasive" and
deterministic testing methods for accurate programming and testing of the
refresh rate and wait state interval of the refresh mode, will
significantly advance the state-of-the-art. The present invention provides
such circuitry and programming/testing methods.
DISCLOSURE OF INVENTION
Briefly summarized, this invention comprises in one aspect a programmable
refresh circuit integrated with a semiconductor memory device having a
memory array accessed through word lines and bit lines. The programmable
refresh circuit includes a self-timed oscillator that outputs a clocking
signal and a programmable pattern generating means that generates a first
signal pattern. A counter means is connected to receive the clocking
signal output from the self-timed oscillator and the first signal pattern
generated by the programmable pattern generating means. The counter means
has a count driven by the clocking signal and outputs a signal pulse upon
the count reaching a digital pattern representation corresponding to the
first signal pattern. Refresh control logic is connected to the counter
means for receiving the signal pulse output and responding thereto by
refreshing a portion of the memory array of the semiconductor memory
device such that output of multiple signal pulses from the counter means
to the refresh control logic defines a refresh rate. Various enhancements
are also presented including means for disabling active refreshing of the
memory array for a programmable "wait state" interval subsequent to
receipt of a signal initiating self-refresh.
Also presented are various methods for programming/testing self-refreshing
of a semiconductor memory device by a programmable refresh circuit
integrated therewith. The semiconductor memory device receives a row
address strobe (RAS) signal and a column address strobe (CAS) signal from
an external control system. A first method includes the steps of:
initiating self-refreshing of the memory array upon receipt of a "CAS
Before RAS" transition of signals at the semiconductor memory array;
pulsing the CAS signal at a known time t.sub.x after initiating of
self-refreshing; monitoring an output of the memory array for a data out
transition responsive to the CAS signal pulsing; if a data out transition
is monitored, incrementing time t.sub.x by a constant time increment
t.sub.c and repeating the above-outlined processing steps; if no data out
transition is monitored, determining a time interval from initiating
self-refresh to time t.sub.x at which the CAS signal pulsing fails to
result in monitoring of a data out transition; and using the determined
time interval to program the self-refreshing characteristics of the
semiconductor memory device. Programmable self-refresh characteristics
include the refresh rate and the wait state interval.
In another embodiment, a method for testing self-refreshing of a
semiconductor memory device is presented. The memory device has a memory
array accessed through word lines and bit lines and a programmable refresh
circuit integrated therewith for refreshing the memory array. The device
receives a row address strobe (RAS) signal and a column address strobe
(CAS) signal from an external control system. This testing method
includes: blanket writing the memory array to a first state; writing a
second state to `X` successive sections of the memory array; actively
self-refreshing the memory array for a first known time interval t.sub.1 ;
writing the second state to `Y` successive sections of the memory array;
reading the memory array and counting the number of refresh sections
between the successive sections having the second state written thereto;
repeating the above-outlined steps for a second known time interval
t.sub.2 ; and determining from the number of refresh sections read and
from the first known time interval t.sub.1 and the second known time
interval t.sub.2 a self-refresh characteristic of the programmable refresh
circuit integrated with the semiconductor memory device.
In yet another aspect, a method is presented for testing self-refreshing of
a semiconductor memory device having a memory array and a programmable
refresh circuit integrated therewith for refreshing the memory array when
in refresh mode. The programmable refresh circuit has a single counter and
the semiconductor memory device receives a row address strobe (RAS) signal
and a column address strobe (CAS) signal from an external control system.
Further, the memory device receives a current from a power supply. The
testing method employs a predefined equation relating ac current of the
semiconductor memory device in refresh mode to frequency of the single
counter within the programmable refresh circuit. The method includes:
measuring dc current input to the semiconductor memory device from the
power supply; placing the memory device in self-refresh mode and measuring
self-refresh current input to the semiconductor memory device from the
power supply; eliminating the measured dc current component of the
measured refresh current to obtain a resultant ac current input to the
semiconductor memory device in refresh mode; and employing the predefined
equation to establish counter frequency, wherein the refresh rate and wait
state interval are each proportional to the established counter frequency.
To restate, the present invention provides a programmable self-timed
refresh circuit integrated with a semiconductor memory device which
accurately refreshes the device when in "sleep mode," and has an
accurately programmable refresh rate and wait state interval when in sleep
mode. Further, methods for programming/testing the programmable refresh
circuit are presented. Specifically, methods are provided for programming
the refresh rate and the wait state interval for refreshing the
semiconductor memory device and for non-invasively testing the refresh
rate and wait state interval once programmed. Because the methods are
non-invasive, and deterministic, testing can occur within a fraction of
the time previously required. The programmable refresh circuit will
maintain specified product timing parameters so that performance of the
memory device will not deteriorate. Data integrity of the device is
maintained by the self-timed oscillator compensating for changes in
process and operating conditions.
BRIEF DESCRIPTION OF DRAWINGS
These and other objects, advantages and features of the present invention
will be more readily understood from the following detailed description of
certain preferred embodiments of the present invention, when considered in
conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram circuit of a semiconductor memory device
incorporating a self-timed refresh (S.T.R.) circuit in accordance with the
principles of the present invention;
FIG. 2 is a block diagram circuit of one embodiment in accordance with the
present invention of the self-timed refresh (S.T.R.) circuit of FIG. 1;
FIG. 3 is a block diagram circuit of one embodiment of the programmable
counter and associated first fuse bank of FIG. 2;
FIG. 4 is a timing diagram of a JEDEC proposed "CAS Before RAS" (CBR)
self-refresh of a semiconductor memory device, followed by exit to a
normal operating mode;
FIG. 5 is a timing diagram of self-timed refresh processing in accordance
with the present invention;
FIG. 6 is a flowchart of a programming/testing process embodiment in
accordance with the present invention for establishing/verifying a desired
wait time and refresh rate for the programmable refresh circuit of FIG. 2;
FIG. 7 is a flowchart of another programming/testing process embodiment in
accordance with the present invention for establishing/verifying a desired
wait time and refresh rate within the programmable refresh circuit of FIG.
2;
FIG. 8 is a graph of power supply current (I.sub.cc) versus counter
frequency for a semiconductor memory device in refresh mode;
FIG. 9 is a flowchart of a further programming/testing process embodiment
in accordance with the present invention for establishing/verifying a
desired wait time and refresh rate for the programmable refresh circuit of
FIG. 2; and
FIG. 10 is a block diagram of a data processing system having a
semiconductor memory device implemented in accordance with the principles
of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
Refer now to the drawings wherein the same reference numbers are used
throughout multiple figures to designate the same or similar components.
FIG. 1 presents an overview of a semiconductor memory device, generally
denoted 10, having an integrated self-timed refresh circuit 12.
Semiconductor memory device 10 includes a memory array 14 consisting of a
plurality of memory cells arranged in a conventional grid configuration
accessed by word lines and bit lines (not shown). In one embodiment, each
memory cell comprises a one-transistor/one-capacitor memory cell
consisting of an n-channel transistor and a capacitor element. A row
decoder 16 decodes an address received at inputs A0, A1, A2, . . . , A11,
and temporarily held in a row address buffer 18. Using the decoded
address, row decoder 16 selects one word line of memory array 14. A RAS
clock generator 20 clocks row decoder 16. When in normal operation, RAS
clock generator 20 responds to a "Row Enable Not" (RE) master signal.
Further, a CAS clock generator 22 responds to a received "Column Enable
Not" (CE) signal.
CAS clock generator 22 generates the clock that drives a column decoder and
I/O gate 24. Column decoder and I/O gate 24 is coupled through sense
amplifiers 26 to the bit lines (not shown) of memory array 14. Sense
amplifiers 26 amplify read data signals to a voltage signal level employed
by the semiconductor memory device. After a row address has been asserted
and the row has been selected in the array, at a point in time later, a
column address is asserted that identifies which node in the array, i.e.,
which piece of data, is selected. The selected data is then brought out
through a data out buffer 28. Data out buffer 28 drives off-chip loads
(not shown) through the input/output connections, for example, I/O0, I/O1,
I/O2, and I/O3. Buffer 28 is itself driven by an "Output Enable Not" (OE)
signal.
Data is written into memory array 14 from the input/output connections
through a data in buffer 32 and column decoder and I/O gate 24. An AND
circuit 34 receives as input a "Write Enable Not" (WE) and the "Column
Enable Not" (CE) signals. This circuit outputs a signal to both data out
buffer 28 and data in buffer 32. This signal designates whether the
desired function comprises a read operation or a write operation.
The balance of this disclosure focuses on the self-refreshing of
semiconductor memory device 10 and includes programming/testing methods
for establishing/verifying refresh characteristics such as the refresh
rate and wait state interval of the programmable refresh circuit in
accordance with the present invention.
The most effective integration of a self-refresh function into a random
access memory, such as shown in FIG. 1 is accomplished so that previously
specified random access memory performance and functional parameters are
maintained. Towards this end, it is desirable that the self-refresh
control logic be self-contained and designed such that it control the
semiconductor memory device at the RAS and CAS clock generators when in
"sleep mode". This then maintains specified performance in that delays of
the control logic remain constant in self-refresh for normal device
operating mode.
A refresh counter 36 (e.g., a RAC counter) contains multiple latches which
identify a next section (e.g., row) of memory array 14 to be refreshed.
Counter 36 is incremented in refresh mode with initiation of each new
(CBR) refresh cycle. Row address buffer 18 obtains a next row address by
reading the state of refresh counter 36 subsequent to initiation of the
refresh mode. Upon start of an active refresh cycle, buffer 18 ignores
signals on address bus 21 of semiconductor memory device 10 and instead
receives the state of refresh counter 36, which identifies a next section
of memory array 14 to be refreshed.
Refresh mode is initially detected by a conventional refresh controller 38
upon receipt of a "CAS Before RAS" (CBR) transition of signals. In
particular, refresh mode is detected by refresh controller 38 whenever the
"Column Enable Not" (CE) signal goes "active" before the "Row Enable Not"
(RE) signal goes "active", i.e., upon selection of the semiconductor
memory device. As used herein, "active" is assumed to comprise a low
signal.
Simultaneous with commencing refresh mode, the S.T.R. circuit 12 is enabled
to monitor whether the RE and CE inputs remain low for a given interval of
time, referred to herein as the "wait state". Assuming that these inputs
are maintained through the "wait state", then a flag is tripped in the
S.T.R. circuit to indicate that the semiconductor memory device is in
self-refresh mode and refreshing of the memory array will occur, for
example, row-by-row at a substantially fixed refresh rate. After wait
state conditions have been satisfied, the CAS buffer is disabled and
becomes a "don't care" during self-refresh mode. However, signal RE is
continually monitored by S.T.R. 12 for an external exit request.
Once entering self-refresh mode, control signals will be output on lines 40
and 42 to the CAS clock generator 22 and the RAS clock generator 20,
respectively, to disable the generators from responding to external
signals presented to the CE and RE inputs during a refresh cycle. In
effect, the generators are deactivated from external system control when
the memory device is undergoing active refreshing of the memory array.
This guarantees that the refresh cycle will be completed before control of
the generators can be returned to the external system. Otherwise, the
external controller might start to restore the array before all refresh
data is back into the corresponding storage cells, with a resultant loss
of data. Thus, control protocol is such that an active refresh cycle takes
precedence over the external system trying to take control of the
semiconductor memory device, i.e., until the current refresh cycle has
been completed and the memory device has returned to "sleep mode."
An S.T.R. circuit 12 in accordance with the invention receives four input
signals. First, a "CAS Before RAS Not" (CBRN) signal is received from
refresh controller 38 whenever the controller detects that the column
address strobe (CAS) goes low before the row address strobe (RAS). Also
received at circuit 12 are three handshaking signals, namely, a power up
enable (ENPL) signal, a data line interlock left (DLINT) signal, and a RAS
clock generator off (STROFFP) signal. The ENPL signal ensures that the
self-time refresh control logic cannot assert itself when the
semiconductor memory device is in power-up mode. The DLINT signal,
produced from the memory array, signals completion of a current refresh
cycle of operation, and the STROFFP signal confirms to the S.T.R. circuit
that it has control of the RAS clock generator.
One embodiment of a programmable self-timed refresh control circuit 12 in
accordance with the invention is depicted in FIG. 2. In this embodiment,
circuit 12 includes a self-timed oscillator (STOSC) 50 which outputs two
non-overlapping clock signals, e.g., signal MN and signal SP as shown.
Oscillator 50 is enabled by a self-refresh enable pulse (SREP) generated
by a self-timed refresh control logic 52. Logic 52 generates this
oscillator enable signal SREP when the logic is itself enabled by power up
enable signal ENPL and, a "CAS Before RAS Not" (CBRN) signal is received.
Also enabled by the self-refresh enable pulse output from logic 52 is a
programmable counter circuit 54. The ability to program the output of
counter 54 is significant since oscillator 50 frequency is traditionally
variable with process biases. For enhanced granularity of control, counter
circuit 54 preferably is a divide-by-N synchronous count-down counter,
wherein N is an integer.
Data integrity of the memory device must be maintained by compensating
self-timed refresh intervals with operating conditions. For example, as
applied voltage increases, the resultant higher electric fields aggravate
parasitic leakage in the memory cells. Thus, it is desirable that the
oscillator frequency increase with voltage. Similarly, parasitic leakage
mechanisms can also be aggravated by increased temperature. Thus, it is
desirable that the oscillator respond appropriately. Process parametric
variations can also affect chip-to-chip and wafer-to-wafer oscillator
frequency. This source of variation is controlled by the fuse programmable
counter, which provides a consistent self-timed refresh frequency
notwithstanding various oscillator input frequencies, i.e., through
programming of the fuses.
As shown, counter circuit 54 is connected to a "first bank of fuses" 56
which, as explained below, allows a system designer to set the refresh
rate, i.e., the interval of time between RP pulse signals output from the
counter circuit. First bank of fuses 56 can comprise any appropriate
signal generating means having a programmable output pattern, such as a
parallel circuit of laser fuses which can be "programmed" by open
circuiting or burning selected fuses. Open circuiting of selected fuses
and passing the signals through a comparator allows the count of counter
circuit 54 at which pulse signal RP will be outputted to be programmed.
Specifically, when the instantaneous count has a digital pattern
representation corresponding to the pattern of signals from the associated
first bank of fuses, then the comparator outputs an RP pulse signal to the
self-timed refresh control logic 52. Resetting the counter and repeating
the process establishes an RP rate of output, or refresh rate. The desired
refresh rate is programmed based on the characteristics of the particular
semiconductor memory device to which circuit 12 is integrated. Fuses 56
can comprise poly-silicon stripes on the integrated circuit chip, which
when exposed to a conventional laser fuse tool are open circuited (or
enabled), since counter circuit 54 is preferably implemented as a count
down counter.
Upon completion of the "wait state," STR control logic 52 outputs a "RAS
Disable Not" (RASDISN) signal to a RAS buffer 58 disp | | |
