A power supply for achieving high output power levels at a high efficiency from a compact profile. The power supply includes a current regulator which receives a source voltage and outputs a signal having a constant current. The signal output from the regulator is provided to a center tap of a primary winding of a transformer. The ends of the primary winding of the transformer are connected to switches which are controlled by a switch driver. The transformer, switches and switch driver form a resonant oscillator. The switch driver is connected to a zero voltage level detector which detects when the voltage of the signal output from the current regulator reaches a zero level. When such a detection is made, the zero voltage level detector provides an enable signal to the switch driver to operate the switches in a push-pull mode. By operating the switches in a push-pull mode, the energy balance and resonance of the transformer can be maintained. This energy balance allows additional transformers to be connected directly in parallel to increase the output power capability.

In an inverting system, a reference V.sub.REF is coupled to an input of a predictor. The predictor has an output V.sub.P and a transfer function T.sub.P. An inverter of the inverting system has a pulse width modulator, a filter, and a transfer function T.sub.I. The transfer function T.sub.P is substantially equal to 1/T.sub.I. The inverter has an output V.sub.C, and the inverter is coupled to the output V.sub.P so that V.sub.C =V.sub.REF T.sub.P T.sub.I =V.sub.REF. In this manner, the output of the inverter tracks the reference without phase error.

A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

Temperature compensation is achieved by adjusting a divide ratio of a multi-modulus divider circuit in a feedback path of a phase-locked loop based on the detected temperature. The divide ratio is adjusted based on stored adjustment values stored in non-volatile memory. Interpolation may be used to interpolate between the stored adjustment values.

A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.