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Claims  |
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What is claimed is:
1. A test access port (TAP) included in an integrated circuit (IC) device
for testing circuits within said device, said TAP having a standard
interface which consists of a number of lines including a test data output
(TDO) and a test data input (TDI) for use in testing and a controller for
generating control and clocking signals for carrying out said testing,
said TAP further comprising a plurality of standard registers connected to
said controller and a multiplexer having a number of inputs and an output
connected to said TDO line of said IC device, each register having at
least a serial input and a serial output, said serial input of each
register being connected to said TDI of said standard interface and said
serial output of each register being connected to a different one of said
multiplexer inputs, said TAP further including:
an additional number of register like transfer circuits, each register like
transfer circuit having an input and an output, said input of each of said
number of register like transfer circuits being connected to said TDI line
and said output of each transfer circuit being connected to a different
predetermined one of said inputs of said multiplexer; and,
an instruction register for storing information pertaining to any one of a
number of instructions coded for generating signals defining a number of
operational modes, said instruction register being coupled to said
multiplexer and to said controller, said instruction register in response
to a first one of said number of instructions being applied by said TDI
line causing said multiplexer to select and during said testing, maintain
selected as a path between said TDI and TDO lines of said IC device, a
first one of said number of said register like transfer circuits to
effectively provide a minimum length shift path for minimizing the number
of bits required to be shifted through a string of IC devices for carrying
out said testing.
2. The TAP of claim 1 wherein said first one of said number of said
transfer circuits corresponds to a wire conductor for providing a zero
length bit shift path for minimizing shifting of said number of bits
including data and instruction bits through said string of IC devices.
3. The TAP of claim 1 wherein said controller generates a selection signal
for selecting said instruction register and wherein said instruction
register includes means conditioned by said first one of said instructions
for preventing said selection signal from changing path selection for
maintaining selection of said first one of said number of said register
like transfer circuits.
4. The TAP of claim 1 wherein a second one of said transfer circuits
corresponds to a single bit register stage, said single bit register stage
being connected to be clocked by signals from said controller, said single
bit register stage in response to a second one of said number of
instructions being applied by said TDI line causing said multiplexer to
select and to maintain as selected as a path, said single bit register
stage to provide a single bit length shift path for transferring bits
clocked at a rate defined by said signals thereby minimizing shifting of
data and instruction bits through said string of IC devices.
5. The TAP of claim 1 wherein said instruction register includes decode
circuits for decoding said number of instructions, said decode circuits in
response to each of said number of instructions, generating signals for
selecting one of said number of register like transfer circuits, for
defining said number of modes of operation and for maintaining selection
of said one of said number of register like transfer circuits
notwithstanding receipt of a select signal from said controller specifying
a change in register selection.
6. The TAP of claim 1 wherein said instruction register includes predecode
circuits for predecoding said number of instructions, said predecode
circuits in response to each of said number of instructions, generating
signals which are loaded into said register for selecting one of said
number of transfer circuits, for defining said number of modes of
operation and for maintaining selection of said one of said number of
register like transfer circuits notwithstanding receipt of a select signal
from said controller specifying a change in register selection.
7. The TAP of claim 5 wherein said instruction register includes reset
circuit means connected to said controller, said controller in response to
a test mode reset signal causing said instruction register to be reset to
a predetermined value.
8. The TAP of claim 5 wherein one of said number of instructions is a
CTRANS instruction coded to specify selection of a predetermined one of
said number of register like transfer circuits for providing a clocked
single bit length shift path between said TDI and TDO lines of said IC
device and for generating mode signals for causing said IC device to
operate in a system mode of operation wherein said device operates as if
said TAP were not incorporated into said device.
9. The TAP of claim 5 wherein one of said number of instructions is a
CTRANT instruction coded to specify said selection of said predetermined
one of said number of register like transfer circuits for providing said
clocked single bit shift path between said TDI and TDO lines of said IC
device and for generating mode signals for causing said IC device to
operate in a test mode of operation wherein said device performs said
testing.
10. The TAP of claim 5 wherein one of said number of instructions is a
DTRANS instruction coded to specify selection of a predetermined one of
said number of register like transfer circuits for providing a zero length
shift path between said TDI and TDO lines of said IC device and for
generating mode signals for causing said IC device to operate in a system
mode of operation wherein said device operates as if said TAP were not
incorporated into said device.
11. The TAP of claim 5 wherein one of said number of instructions is a
DTRANT instruction coded to specify said selection of said predetermined
one of said number of register like transfer circuits for providing said
zero length bit shift path between said TDI and TDO lines of said IC
device and for generating mode signals for causing said IC device to
operate in a number of test modes of operation wherein said device
performs said testing.
12. The TAP of claim 5 wherein one of said number of instructions is a
DTRANC instruction coded to specify selection of a predetermined one of
said number of register like transfer circuits for providing a zero length
shift path between said TDI and TDO lines of said IC device and for
generating mode signals for causing said IC device to operate in a current
mode of operation corresponding to either a system mode or test mode of
operation.
13. The TAP of claim 5 wherein one of said number of instructions is a
CTRANC instruction coded to specify said selection of said predetermined
one of said number of register like transfer circuits for providing said
clocked single bit shift path between said TDI and TDO lines of said IC
device and for generating mode signals for causing said IC device to
operate in a current mode of operation corresponding to either a system
mode or test mode of operation.
14. A method of providing a number of additional modes of operation in a
standard test access port (TAP) for minimizing shifting of instruction and
data bits through a number of series connected integrated circuit (IC)
devices, said standard TAP being included in each integrated device for
testing circuits within said device, said TAP having a standard interface
which consists of a number of lines including a test data output (TDO)
line and a test data input (TDI) line for use in testing and a controller
for generating control and clocking signals for carrying out said testing,
said TAP further comprising a plurality of standard registers connected to
said controller and a multiplexer having a number of inputs and an output
connected to said TDO line of said IC device, each register having at
least a serial input and a serial output, said serial input of each
standard register being connected to said TDI line of said standard
interface and said serial output of each register being connected to a
different one of said multiplexer inputs, said method comprising the steps
of:
a. incorporating an additional number of register like transfer circuits
into each IC device, each register like transfer circuit having an input
and an output;
b. connecting said input of each register like transfer circuit to said TDI
line and connecting said output of each register like transfer circuit to
a different predetermined input of said multiplexer;
c. including an instruction register for storing information pertaining to
any one of a number of instructions coded for generating signals defining
said number of additional modes;
d. connecting said instruction register to said TDI line, to said
multiplexer and to said controller;
e. selecting in response to a first one of said number of instructions
being loaded into said register through said TDI line, one of said
additional number of register like transfer circuits designated by said
instruction as a path between said TDI and TDO lines of said IC device;
and,
f. maintaining the selection of said one register like transfer circuits
during testing so as to provide a minimum length shift path for minimizing
said shifting of said data and instruction bits.
15. The method of claim 14 wherein said method further includes the step
of:
g. resetting said instruction register to a predetermined value by said
controller when a test mode reset signal is applied to said controller.
16. The method of claim 14 wherein step e further includes selecting one of
said additional number of register like transfer circuits which provides a
zero length shift path between said TDI and TDO lines of said device.
17. The method of claim 16 wherein said method further includes the steps
of:
h. connecting a tester to each of said number of series connected IC
devices;
i. loading said first one of said instructions coded to specify said zero
length shift path into said instruction register of each IC device;
j. connecting a generator to said TDI line of a first one of said series
connected IC devices;
k. connecting a verification circuit to said TDO line of a last one of said
series connected IC devices; and,
l. verifying that signals applied by said generator to said TDI line are
propagated through said series connected IC devices within a predetermined
minimum time period for indicating that there has been no change in state
of said TAP of any one of said IC devices.
18. The method of claim 14 wherein said method further includes the steps
of:
h. connecting a tester to each of said number of series connected IC
devices;
i. loading into said instruction registers of a number of said IC devices
except IC devices to be tested, said first one of said instructions coded
to specify said zero length shift path;
j. performing a series of boundary scan tests by said tester on said IC
devices to be tested; and,
k. evaluating results obtained in step j to determine if any of said number
of IC devices which were loaded with said first one of said instructions
had responded incorrectly to signals associated with a previous series of
boundary scan tests.
19. The method of claim 14 wherein step e further includes selecting one of
said register like transfer circuits which includes a logic gate having a
first input connected to said TDI line, a second input connected to a
reference logic signal and an output connected to a predetermined input of
said multiplexer for providing a shift path between said TDI and TDO lines
of said device and said method further includes the step of changing the
state of said reference logic signal for indicating the occurrence of a
predetermined event within an IC device.
20. The method of claim 19 wherein said method further includes the steps
of:
h. connecting a tester to each of said number of series connected IC
devices;
i. loading said first one of said instructions coded to specify said logic
gate length shift path into said instruction register of each IC device;
j. connecting a generator to said TDI line of a first one of said series
connected IC devices;
k. connecting a verification circuit to said TDO line of a last one of said
series connected IC devices; and,
l. verifying that signals applied by said generator to said TDI line are
propagated through said series connected IC devices within a predetermined
minimum time period for indicating that there has been no change in state
of said TAP and in said reference logic signal of any one of said IC
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of Use
The present invention relates to electronic integrated circuits (ICs) and,
more particularly, to circuits which employ a standard boundary scan test
access port.
2. Prior Art
A standard boundary scan test architecture was approved by the American
National Standards Institute and the Institute of Electrical and
Electronics Engineers in 1990. This architecture provides a means by which
ICs may be designed in a standard fashion such that they or their external
connections, or both, may be tested using a four or five wire interface.
The device test logic which connects to this interface is known as a test
access port, or TAP. Device outputs normally controlled by the functional
system logic of an IC chip may be controlled via the TAP. Also, device
inputs to the functional system logic may be monitored via the TAP. All
TAP control and data bits are passed in serial fashion on two lines: a
test data input (TDI), and the test data output (TDO). Integral to each
TAP is a TAP controller having a state machine which determines the
function of the device test logic. A test clock (TCK) line and a test mode
select (TMS) line determine the currently active state of each state
machine. The state machine has been designed such that a logic one present
at the TMS input for five consecutive clocks of TCK always results in
placing the state machine in a state called test logic reset. In this
state, the device test logic has no effect on the IC device functional
logic circuits and the device operates essentially as if the test logic
were not present. An optional test reset state (TRST*) line may be
included in devices where there is a need to enter the test logic reset
state without waiting for five TCK clock cycles. For example, such need
may arise when there are possible output driver conflicts with other
devices immediately after power up.
For compliance, the standard mandates the use of several specific operating
modes for all devices while others are optional. For example, one mandated
mode is known as EXTEST. This mode allows interconnections between devices
to be checked by setting various outputs to known states and checking the
receipt of these known states at various inputs to verify continuity.
Additionally, through the use of potentially conflicting output states,
the receipt of proper input states can verify the absence of shorts.
Optional modes include modes which, if present, must conform to the
standard, and modes which are not defined by the standard. An example of
the former is known as INTEST. This mode allows device functional logic
inputs to be controlled via the TAP and device functional outputs to be
monitored via the TAP. The INTEST mode allows the device functional logic
circuits to be checked by applying test vectors and monitoring device
response via the TAP. Modes not defined by the standard are known as
private modes. An example of such a mode is a mode in which the TAP
controls data shifting through an internal scan chain.
A register known as the instruction register is used to select the various
operating modes of the TAP controlled test logic. Input bits destined for
the TAP instruction register enter the device via the same interface line
used for test data bits. The value of the data or instruction bits is
determined by the current state of the TAP state machine. The length of
the scan chain through the device (i.e., from the TDI line to the TDO
line) is, therefore, determined by the length of the currently selected
register.
The standard mandates the use of a number of registers. These registers,
connected in parallel between a common serial input (TDI) and common
serial output (TDO), include a bypass register, a boundary scan register
and a number of optional test data registers. The length of the bypass
register is defined as one bit. The instruction register has a minimum
length of two bits and may be expanded as a user sees fit. For example, a
16-bit or longer instruction register may be appropriate for some
applications.
During normal operation, all devices of a boundary scan chain are in the
same TAP state machine state at any given time. Hence, it can be seen that
the overall length of the boundary scan chain can vary widely depending
upon the TAP selection of instruction versus data registers. While the
length of the boundary scan chain may be minimized during the shifting of
data bits by selecting the bypass register in some devices, it cannot be
prevented from being expanded to the cumulative length of all device
instruction registers during the shifting of instruction bits.
Furthermore, since all instruction registers of the boundary scan chain
must be updated together, an appropriate value must be determined for and
shifted into all such instruction registers, not just the one or more
instruction registers of immediate interest.
The inability to select particular devices of a boundary scan chain to
receive instruction register updates, therefore, results in considerable
overhead. To alter the contents of only one instruction register, the
present state of all other instruction registers of the chain have to be
determined and the appropriate bits made to proceed and follow the bits
scanned into the instruction register of interest. For example, consider a
boundary scan chain of a thousand serially connected devices, each having
an instruction register 16 bits in length. To alter the 16-bit instruction
register of one device, 16,000 bits would have to be shifted into the
boundary scan chain once instruction register shifting was established.
The shifting of 15,984 bits is viewed as overhead, since such shifting
merely serves to restore the current contents of the other instruction
registers not being altered. The overhead exists both in terms of time
needed to shift in the bits and in the means needed in their
determination.
It will be appreciated that the case where overhead would be somewhat
minimized by specific instruction bit configurations and relative
locations on the boundary scan chain has not been considered in the above
example because of the greater importance of considering a general case.
Considerable overhead can also exist in the shifting of data bits. For
example, again consider the case of a thousand devices in a single
boundary scan chain. Assume, by virtue of previous instruction register
entries, 999 devices have selected the bypass register and one device has
selected an optional data register of 100 bits, for a total scan chain
length of 1099 bits. Further, assume that it is desired to examine the
contents of the optional data register each time new contents are shifted
into the devices. In this case, up to 1099 shifts would be required for
each change of the optional 100-bit data register, resulting in an
overhead of 999 bits. Since the standard mandates loading the bypass
register with a logic zero at the same time the optional data register is
loaded, as determined by the state machine, the shifted data cannot be
retained in the bypass registers to alleviate the overhead condition.
Overhead in boundary scan operations is significant in that it decreases
the number of tests that may be conducted within a reasonable amount of
time and increases the amount of external hardware and associated software
needed to apply those tests.
Despite the powerful capability of the architecture defined by the
standard, implementation at the level of a large board or at the system
level can present problems in terms of selecting boundary scan paths of
manageable length during design.
Other problems also exist in determining boundary scan paths. One such
problem is the case where electrical faults or shortcomings of the test
interface, as with the clock line (TCK) cause erratic test operation. In
this case, diagnosing and locating the fault within the test interface and
its associated logic becomes more difficult as the length of the boundary
scan chain increases.
Experts in the field have attempted to increase boundary scan chain
manageability by creating multiple chains which are merged into a single
interface grouping by means of added controller devices which have
attributes similar to TAPs. One such device is the "Backplane Test Bus
Link" described by D. Bhavsar in the published proceedings of the 1991
IEEE International Test Conference." Another such device is the
"Addressable Shadow Port" described by L. Whetsel in the published
proceedings of the 1992 IEEE International Test Conference.
These and similar such devices represent an overhead of a different kind.
They have hardware overhead beyond that which is already contained in
devices having TAP controllers that conform to the above mentioned
standard. In certain cases, such devices and methods could be implemented
as additions to devices already defined to be incorporated as part of a
given design. However, whether or not such methods are implemented as
dedicated devices or incorporated as part of an integrated circuit during
design, they still represent an undesirable hardware overhead in the
general case.
Accordingly, it is a primary object of the present invention to provide a
method and means of minimizing the bit overhead of the boundary scan
serial string test operations without incurring the overhead typically
found in attempts to implement boundary scan in a multiplicity of strings
at a board or system level.
It is a further object of the present invention to provide such method and
means of minimizing bit overhead in a manner which does not conflict with
present standards to the extent that devices incorporating the present
invention could be used with devices previously manufactured to conform to
the standard.
It is a still further object of the present invention to provide a method
and apparatus for performing verification and diagnostic operations
relating to the device test logic.
SUMMARY OF THE INVENTION
The above objects and advantages of the present invention are achieved in a
preferred embodiment of a test access port (TAP) included in an IC device
which provides electronic access to the circuits within the IC device.
According to the present invention, the TAP incorporates additional logic
circuits for establishing predetermined operating modes defined by a
number of new boundary scan instructions. Each such instruction prevents
affected IC devices from changing in either their current operating mode
or scan path length between the TDI input and TDO output as a consequence
of boundary scan chain instruction register or data register shifting
operations. The modes remain effective until the TAP state machine enters
a test logic reset state in a conventional manner which effectively
disconnects the TAP from each IC device. That is, in the preferred
embodiment, the mode is effective until such state is entered either
through asserting an optional test reset (TRST*) line or by the repeated
clocking of a test clock (TCK) line when in a test mode (i.e., a test mode
select line at a logic one) wherein the number of times depends on the
state machine condition at the outset.
The instructions of the present invention allow selection of either a
single bit register or a direct connection to be placed in the path
between a device's TDI input and TDO output. The single bit register in
contrast to the above described bypass register, retains its current value
at the point during data shifting that the bypass register is required to
be set to zero. The single bit register of the preferred embodiment in
contrast to the bypass register, remains active in the TDI to TDO path
during instruction scan operations as well as data scan operations. The
direct connection minimizes the overall boundary scan chain bit length and
also reduces dependency on device clocking for shift operations.
The instructions further allow test logic present at device functional
(i.e., non-test) pins to either retain or release control of those pins,
making them useable during both test-only operations and background TAP
operations running in conjunction with normal system functions.
The above objects and advantages of the present invention will be better
understood from the following description when taken in conjunction with
the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a and 1b show the test logic circuits of a test access port which
incorporates logic circuits of the present invention.
FIG. 2 shows a typical instruction register cell which incorporates logic
circuits of the present invention.
FIG. 3 shows a typical mode control cell which incorporates logic circuits
of the present invention.
FIG. 4 shows an example system used in describing the operation of the
present invention.
FIG. 5 shows an on-line monitoring configuration system of the present
invention for continuously verifying test logic inactivity.
FIG. 6 is a diagram illustrating a scan operation carried out by the
preferred embodiment of the present invention and the prior art.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a standard test access port (TAP) which incorporates the
circuits of the present invention. As shown, the test access port includes
a plurality of data registers 100, 102 and 104 and a multiplexer 118,
arranged as shown. The data registers correspond to a boundary scan
register 100, a bypass register 102 and internal scan register 104 which
connect to multiplexer 118. The TAP further includes a typical instruction
register 106, an instruction decoder 108 and a controller state machine
110. The value loaded into the instruction register 106 which is then
decoded by decoder 108 determines the TDI (test data in) to TDO (test data
out) path selection during data shift operations. That is, the multiplexer
118, the output of which drives TDO driver 120, is controlled via lines
117 from decoder 108 in accordance with the value defined by the
previously loaded instruction in conjunction with signals from TAP
controller 110.
The TAP controller 110 includes a state machine and clock circuits which
generate the required-control and clocking signals applied to the
different registers of FIG. 1a. Additionally, TAP controller 110 provides
as outputs, select and enable signals which are applied as inputs to the
instruction decoder 108 and an output driver circuit 120 respectively. The
controller 110 receives as inputs, an optional test reset state (TRST*)
line, a test mode select (TMS) line and a test clock (TCK) line. The TCK
and TMS lines determine the currently active state of the controller state
machine of each IC device. The TRST* line, if present, overrides both to
force a reset.
The controller state machine is designed such that a logic ONE present on
the TMS line for five consecutive clocks of line TCK always results in
placing the state machine in a test logic reset state. In this state, the
IC device test logic has no effect on the IC device functional logic
circuits and device operates as if such test logic were not present. The
TRST* line may be included in IC devices where there is a need to enter
the test logic reset state immediately (i.e., without having to wait up to
five TCK clock cycles).
The TAP controller 110 generates the select signal on a select line during
state machine states defining when the instruction register 106 is the
register selected by multiplexer 118 as the path between input TDI and
output TDO. The select signal causes instruction decoder 108 to apply an
appropriate select code value on line 117 designating instruction register
106 as the register to be selected. The TAP controller 110 generates the
enable signal during machine states defining instruction register and data
register shifting operations.
For further details regarding TAP controller 110, in addition to the TAP
and boundary scan operations, reference may be made to the publication
entitled, "IEEE Standard Test Access Port and Boundary-Scan Architecture,"
published by the Institute of Electrical and Electronics Engineers, Inc.,
Copyright 1990.
In the preferred embodiment, boundary scan register 100 includes a shift
register section and hold/storage register section. This allows register
shift and update operations to be performed independently. The instruction
register 106 is similarly constructed. The boundary scan register 100
normally included as part of the IC device consists of cells logically
positioned for monitoring IC inputs (i.e., signals originating from
without the IC device) or pins for driving inputs to the functional logic
of the IC device (i.e., to have the effect of signals originating from
without the IC device) and for driving external lines which connect to
outputs or bidirectional connections of the IC device. By serially
scanning binary values into the boundary scan register 100 via input TDI,
test vectors can be applied to an IC device to which the test system is
unable to make contact, except via the TAP.
Bypass register 102 is a single bit shift register which is reset at the
start of data shift operations. Generally, its purpose is to minimize the
path between TDI input and TDO output. This register is selected by
default each time the TAP is reset unless the device includes an optional
identification register. In such case, the latter register is selected at
TAP reset. The optional identification register (not shown) contains 32
bits, the one nearest to the TDO output being placed in a logic one state.
Thus, the resetting of bypass register 102 allows a test system to examine
the TDI to TDO path of numerous serially connected IC devices and
distinguish between the two types of IC devices (i.e., those with and
without identification registers).
The internal scan register (SI) 104 includes a plurality of storage
cells/elements of the functional logic of its respective IC device that
are interconnected to form a serial string internal to the device during
test so as to facilitate testing. This type of arrangement is described in
U.S. Pat. No. 3,582,902 to Allen C. Hirtle, et al.
In accordance with the present invention, two transfer registers have been
incorporated into the TAP structure of FIG. 1a. These are a single bit
register 140 and a zero length register 150 implemented by directly
connecting the TDI input via a "zero length register" line 110 as an input
to multiplexer 118. The direct connection, when selected by means of an
appropriate instruction, provides logical continuity of the TDI to TDO
path without necessitating clocking by the TAP. The single bit register
140 in contrast to the bypass register does not get reset at the beginning
of each shift operation. The register 140 is referred to herein as the C
register. The zero length register 150 is referred to herein as the D
register. Referring to the direct connection as a zero length register is
done only for ease of explanation in describing the present invention in
light of the prior art.
The C register 140 is shown in greater detail in FIG. 1b. As seen from FIG.
1b, C register 140 includes an input section and a storage section. The
input section includes NAND gates 142 through 145 which receive the
different clock and control signals SHIFTIR through RESET* from TAP
controller 110. The storage section includes a clocked D-type flip-flop
141 whose D input terminal connects to the TDI line and whose Q output
terminal connects to one of the data selection inputs (i.e., input 4) of
multiplexer 118. The clock input terminal (CLK) and reset input terminal
(R) connect to the outputs of NAND gates 144 and 145 respectively.
FIG. 2 illustrates a typical instruction register cell which makes up the
six-bit instruction register of FIG. 1 constructed according to the
present invention. The shift registe | | |
