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| United States Patent | 5450023 |
| Link to this page | http://www.wikipatents.com/5450023.html |
| Inventor(s) | Yang; Weikang (Tokyo, JP);
Shou; Guoliang (Tokyo, JP);
Takatori; Sunao (Tokyo, JP);
Yamamoto; Makoto (Tokyo, JP) |
| Abstract | An interface circuit for reducing the number of data pins in an LSI
circuit. The interface circuit, converts a multivalue input signal of a
predetermined level into a binary value or converts a binary output signal
into a multivalue of signal a predetermined level and is used as an
interface for transferring data in LSI applications. |
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Title Information  |
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Drawing from US Patent 5450023 |
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Interface circuit using a limited number of pins in LSI applications |
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| Publication Date |
September 12, 1995 |
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| Filing Date |
April 18, 1994 |
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Title Information |
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Claims |
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What is claimed is:
1. An integrated circuit including an interface circuit disposed therein,
said interface circuit comprising:
first converting means, disposed within said integrated circuit, for
converting an input signal to said integrated circuit having a voltage
within one of at least four ranges into a binary signal, and
second converting means, disposed within said integrated circuit, for
converting a binary output signal from said integrated circuit into a
signal having a voltage within one of at least four ranges.
2. An interface circuit comprising:
i) means for receiving a plurality of binary input signals;
ii) a decoder for generating a signal corresponding to a value represented
by said binary input signals; and
iii) a plurality of voltage sources; and
iv) a plurality of transistors, each having a first terminal connected to
one of said voltage sources, respectively, a second terminal connected to
a common output terminal and a control terminal responsive to said signal
generated by said decoder.
3. An interface circuit comprising:
i) means for receiving a multivalue input signal;
ii) a first plurality of capacitances each having one terminal connected to
said receiving means and another terminal connected to a corresponding one
of a plurality of switch nodes;
iii) a resistor network connected to a power source having a plurality of
nodes at different voltages;
iv) a second plurality of capacitances, each having one terminal connected
to one of said nodes, respectively, and a second terminal connected to a
corresponding one of said plurality of switch nodes, respectively;
iv) a plurality of switches, each controlled by a voltage level at one of
said plurality of switch nodes, for selectively supplying a corresponding
signal level; and
v) an encoder for receiving said signal levels and generating a plurality
of corresponding binary signals.
4. An integrated circuit including an interface circuit disposed therein,
said interface circuit comprising:
means for receiving a plurality of binary input signals;
a decoder for generating a decoder output corresponding to a value
represented by said binary input signals;
means for generating a voltage signal having a voltage level corresponding
to said decoder output;
means for receiving a multivalue voltage signal;
means for selectively supplying a source voltage to one or more of a
plurality of encoder lines in accordance with said multivalue voltage
signal; and
an encoder for receiving said encoder lines and generating a plurality of
binary signals.
5. The integrated circuit of claim 4, wherein said means for generating a
voltage signal includes:
a plurality of transistors, each connected between one of a corresponding
plurality of voltage sources and an output terminal such that said decoder
output causes one of said plurality of transistors to conduct.
6. The integrated circuit of claim 4, wherein said means for selectively
supplying a source voltage includes:
a first plurality of capacitances connected between said receiving means
and a corresponding plurality of switch nodes;
a second plurality of capacitances, each having a first terminal connected
to one of a corresponding plurality of voltage sources and a second
terminal connected to a corresponding one of said switch nodes; and
a plurality of switches for selectively connecting a source voltage to one
or more of said plurality of encoder lines in response to a voltage level
at each of said plurality of switch nodes. |
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Claims |
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Description |
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FIELD OF THE INVENTION
The present invention relates to an interface circuit for transferring data
across a limited number of pins in LSI applications.
BACKGROUND OF THE INVENTION
A higher scale of integration in an LSI circuit results in a circuitry per
chip. Therefore, the number of input and output signals increases
substantially, and it is impossible an avoid to increase in the number of
pins. However, an increased number of pins can not be accommodated because
of the size limitations of the LSI package.
SUMMARY OF THE INVENTION
The present invention solves the conventional problems and provides an
interface circuit for transferring data across a limited number of pins in
LSI applications.
An interface circuit according to the present invention reduces the number
of pins for transferring data in LSI applications by converting a
binarized signal into a binarized multivalue signal or a multivalue
binarized signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit between LSI circuits using the present invention.
FIG. 2 is a block diagram of a first embodiment of a multivalue binarized
value converting circuit.
FIG. 3 is a diagram explaining signal levels.
FIG. 4 is a block diagram of a second embodiment of a multivalue binarized
value converting circuit.
FIG. 5 is a diagram explaining signal levels.
FIG. 6 is a diagram explaining a circuit with switch characteristics.
PREFERRED EMBODIMENT OF THE PRESENT INVENTION
Hereinafter, an embodiment of the present invention is described with
reference to the attached drawings.
FIG. 2 is a block diagram of a binarized multivalue converting circuit.
T.sub.A, T.sub.B, T.sub.C and T.sub.D are transistors connected in
parallel, and R4, R3, R2, R1 and R0 are resistances. The source of T.sub.D
is connected with a power source V.sub.CC through R.sub.4, the source of
T.sub.C is connected with power source V.sub.CC through R4 and R3, the
source of T.sub.B is connected with power source V.sub.CC through R4, R3
and R2 and one of T.sub.A is connected with a source V.sub.CC power
through R4, R3, R2 and the R1. Here, R4 and R0 have same resistance value,
and resistance value of R3, R2 and R1 are twice that of R4 or R0.
Signals x and y are binarized logical input signals. When signals x and y
are at a low level (shown by "0" in FIG. 3), a decoder outputs signal A as
a high level (shown by "1" in FIG. 3) and render only T.sub.A conductive.
In this case, the voltage at node 0 is output as V.sub.OUT in a source
follower circuit composed of T.sub.A, T(0) and R(0).
In the case when x is "1" and y is "0", signal B is output as a high level
and only T.sub.B is rendered conductive. The voltage at node 1 is output
as V.sub.OUT.
In the case when x is "0" and y is "1", signal C is output as a high level,
and only T.sub.C is rendered conductive. The voltage at node 2 is output
as V.sub.OUT.
In the case when x and y are "1", signal D is output as a high level, and
only T.sub.O is rendered conductive. The voltage at node 3 is output as
V.sub.OUT.
In this circuit, when one of signals A, B, C or D is "1", voltage V.sub.OUT
is as follows.
Signal A: 0.ltoreq.V.sub.OUT <1/4 V.sub.CC
Signal B: 1/4 V.sub.CC .ltoreq.V.sub.OUT <2/4 V.sub.CC
Signal C: 2/4 V.sub.CC .ltoreq.V.sub.OUT <3/4 V.sub.CC
Signal D: 3/4 V.sub.CC .ltoreq.V.sub.OUT <V.sub.CC
Then, 2 bits of data on 2 lines can be expressed by 4 values, each value
corresponding to a voltage level.
In the circuit of FIG. 6, V.sub.1 and V.sub.2 are input voltages, C.sub.1
and C.sub.2 are capacitors. T.sub.1 is NMOS transistor and T.sub.2 is a
PMOS transistor. If C.sub.1 is equal to C.sub.2, then voltage V.sub.3 is
shown by
##EQU1##
If a threshold voltage of transistors T.sub.1 and T.sub.2 is defined as
V.sub.T, then a signal x' is "1" if V.sub.3 is smaller than V.sub.T and is
"0" if V.sub.3 is more than V.sub.T. Thus, the circuit of FIG. 6 has the
characteristics of a switch.
The circuit shown in FIG. 4 includes a plurality of circuits having the
same composition as in FIG. 6 connected in parallel.
Here, if a threshold voltage of each transistor is defined as 1/2 V.sub.CC,
based on formula 1, voltages V.sub.A, V.sub.B and V.sub.C are defined as
formulas 2, 3 and 4.
##EQU2##
When input voltage V.sub.IN is smaller than 1/4 V.sub.CC, then all signals
A', B' and C' are "1". When V.sub.IN is more than 1/4 V.sub.CC, but less
than 44 V.sub.CC, then only signal A' is "0". When V.sub.IN is more than
2/4 V.sub.CC, but less than 3/4 V.sub.CC then signals A' and B' are "0".
When V.sub.IN is more than 3/4 V.sub.CC, then all signals A', B' and C'
are "0".
When all signals A', B' and C' are "1", then the encoder sets the signal
levels of y' and z' as "0". When only signal A' is "0", then y' is "1" and
z' is "0". When signals A' and B' are "0", then y' is "0" and z' is "1".
If all signals A', B' and C' are "0", then y' and z' are "1".
Thus, it is possible to convert the representation of 2 bits of data from 4
valves on one line into two binary data lines.
FIG. 5 shows the relationship between signals A', B' and C' and signals y'
and z'.
FIG. 1 shows a group of LSI circuit interconnected on a circuit board, each
have interface circuits for translating data signals from binary to
multivalue and multivalue to binary. By using the interface circuits, it
is possible to reduce the number of pins needed.
In FIG. 1, I/F.sub.2A is a binary to multivalue interface circuit for an
address signal. I/F.sub.MA is a multivalue to binary interface circuit for
an address signal. I/F.sub.MD is a multivalue to binary interface circuit
for a data signal. Insides of the CPU chip and each memory chip are binary
logic circuits. A binary address signal used by the CPU is converted into
a multivalue signal through I/F.sub.2A . An output signal is converted
into a binary signal through I/F.sub.MA of memory 1 and stored in
memory.sup.1.
A binary data signal used in the CPU is converted into a multivalue signal
through I/F.sub.2A.
Output multivalue data is converted into binary data through converter
I/F.sub.MA and it is stored in memory 1.
When binary data stored at memory.sub.1 is processed by the CPU, binary to
multivalue converting is performed by I/F2D of memory.sub.1 and the signal
is processed by the CPU after multivalue to binary converting by
I/F.sub.MD.
Therefore it is possible to reduce the number of lines between a CPU and
memory.
As mentioned above, an interface circuit according to the present invention
makes it possible to reduce the number of input/output pins for LSI
circuits and to thereby limit package size.
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Description |
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