Semiconductor device and its fabrication method

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices and fabrication methods thereof. In particular, the invention relates to semiconductor devices formed on an SOI (Silicon on Insulator) substrate and fabrication methods thereof. Also, the invention relates to bipolar transistors having a control electrode formed via an insulating film on a base region.

2. Related Background Art

In the development of an advanced information society, there has been a great contribution of improved technology for semiconductor devices such as transistors. Among such devices is included a vertical bipolar transistor such as a planar bipolar transistor. The vertical bipolar transistor operates at high speed as a single element, and can act effectively for current amplification and switching. However, when incorporated as an element to an integrated circuit, the vertical bipolar transistor is difficult to combine with a condenser (capacitor) or other transistor resulting from the problem of the process times. One method of constituting an integrated circuit by the combination of a bipolar transistor with other elements is to laterally arrange the bipolar transistor to enhance coordination with the process times. There is a Bi-CMOS structure in which a MOS transistor is chose as another element to combine with the bipolar transistor. Bi-CMOS allows for the design of logic with high speed and low consumption power, because the bipolar transistor operating at high speed and the MOS transistor operating at high speed and the MOS transistor operating at low consumption power can be incorporated into one IC.

The process of incorporating the bipolar transistor as one element in an IC of a Bi-CMOS fabricated on a silicon wafer is referred to as a silicon wafer bulk process. Conventionally, the vertical bipolar transistor and the lateral bipolar transistor has been formed through the silicon wafer bulk process, as shown in FIGS. 67 and 68.

In FIG. 67, and NPN-type vertical bipolar transistor 301 is electrically separated from other elements by an element separation region 302. Herein, 303 is a P-type silicon substrate, 304 is an N.sup.+ -type region which is a collector region for the vertical bipolar transistor 301, 305 is an N.sup.- -type epitaxial region, 306is a collector lead-out layer, 307 is a P-type region for element separation, 308 is a selective oxidation region, 309 is a P-type base region, 310 is an N.sup.+ -type emitter region, 311 is an interlayer insulating layer, 312, 313, and 314 are Al electrodes, and 315 is a passivation insulating layer.

In FIG. 68, a PNP-type lateral bipolar transistor is shown. The PNP-type lateral bipolar transistor 321 is electrically separated from other elements by an element separation region 322. Herein, 323 is a P-type silicon substrate, 324 is an N.sup.+ -type region which is a base region for the lateral bipolar transistor 321, 325 is an N.sup.- -type epitaxial region, 326 is a base lead-out layer, 327 is a P-type region for element separation, 328 is a selective oxidation region, 329 is a P.sup.+ -type emitter region, 330 is an P.sup.+ -type collector region, 331 is an interlayer insulating layer, 332, 333, and 334 and AI electrodes, and 335 is a passivation insulating layer.

In the silicon waver bulk process, if the element separation region for separation the transistor from other elements is not provided as above described, some elements bring about latch-up or a parasitic transistor is produced. Or even if the element separation region is provided, the element separation may not be successful. For these reasons, ICs sometimes malfunction and become inoperable due to the design.

In practice, a Bi-CMOS is used for a decoder unit such as a DRAM, and has a structure as illustrated in FIGS. 69A and 69B. However, when this Bi-CMOS is formed of bulk silicon, the process becomes extremely complex because when fabricating a CMOS and a vertical bipolar transistor, element separation must be performed. Therefore, the yield is reduced and the cost is increased. If the lateral bipolar transistor is fabricated in bulk, the process times may be decreased, but the element separation region must be made. To resolve this problem, numerous research has been performed for forming Bi-CMOS on the SOI substrate. The fabrication of Bi-CMOS using the SOI substrate. The fabrication of Bi-CMOS using the SOI substrate allows the dielectric separation between elements to be made simpler. When fabricating a bipolar transistor using the SOI substrate, the lateral bipolar transistor may be fabricated in a smaller number of process times. The lateral bipolar transistor may be inferior in performance to the vertical bipolar transistor, but can be fabricated through a fabricating process which is also used for the CMOS fabrication. Further, since the lateral bipolar transistor is fabricated on the SOI structure, it can eliminate any external base between emitter and base which will cause a degradation of current amplification gain (h.sub.FE) SO that its characteristics can be improved.

The method of forming a MOS transistor on the SOI substrate is suitable from the respects of suppressing the short channel effect and making the microstructure of an element. For the above reasons, the method of forming Bi-CMOS having lateral bipolar transistor on the SOI substrate is expected to be promising.

In fabricating Bi-CMOS on the SOI substrate, the lower voltage is required from a point of withstanding voltage and consumption of power of an element for the microstructure of necessary elements. However, in the bipolar transistor, the potential V.sub.BE between emitter and base is not zero volts, and may be about 0.6 to 0.7 volts at minimum. Consequently in a circuit producing waveforms as shown in FIG. 70, the amplitude of a signal transferred is reduced 1.2 to 1.4 volts from the power source voltage of 3.3 volts, and it is necessary that the effective voltage for driving is 1.9 to 2.1 volts. That it, the on-state voltage of a bipolar transistor is about 0.7V while the on-state voltage of a MOS transistor is about 0.3 to 0.4V.

For such reasons, there is a problem that the driving power for a Bi-CMOS is extremely degraded at low voltages, for which it is the only way in the state of the art to construct a Bi-CMOS with the MOS circuit when the lower voltage ICs for use with portable commodities are made or the reduction of power voltage due to a microstructure is obliged. The construction only with the MOS circuit may not allow the high speed IC to be fabricated.

According to the present invention one method proposed for resolving this problem is one in which a bipolar transistor provided with a control electrode on the base region (hereinafter referred to as a bipolar transistor with control electrode) is used to reduce the on-state voltage equivalent to that of the MOS transistor. This transistor can provide an on-state current with a large threshold for the on-state voltage by applying a voltage to the control electrode to adjust the base region to be in a weak inversion state (the p-type base region becomes i-type for the NPN transistor).

FIG. 71 shows a structure of the bipolar transistor with control electrode. In FIG. 71, 501 is an oxide film, 502 is a collector, 503 is a base, 504 is an emitter, 505 is a collector, 503 is a base, 504 is an emitter, 505 is an oxide film (insulating film), 506 is a control electrode, 507 is in interlayer insulating film, and 508 is a metal electrode.

FIG. 72 shows a gammel plot diagram of the bipolar transistor with control electrode. In FIG. 72, the solid line indicates the characteristic of the bipolar transistor with control electrode, and the dashed line indicates the characteristic of a conventional bipolar transistor. The axis of ordinates indicates the base current (I.sub.B) and the collector current (I O), and the axis of abscissas indicates the base voltage. Supposing that the on-state current occurs when the collector current (I.sub.0) flows at 1 .mu.A, it will be found that the on-state voltage of a conventional bipolar transistor not having control electrode is about 0.7V while that of the bipolar transistor with control electrode is smaller, such as about 0.4V. That is, the lateral bipolar transistor with control electrode can generate a equal on-state current with smaller on-state voltage than the bipolar transistor having no control electrode.

On the other hand, it is desired that the bipolar transistor with control electrode may be operated at a higher speed. However, since the transistor of FIG. 71 is of the lateral type, the base width (t.sub.m in FIG. 71) is of the lateral type, the base width (t.sub.m in FIG. 71) significantly affecting the high speed characteristic may be determined by a photolithography technique. In the state of the art, the base width becomes about 0.5 .mu.m at a minimum, making it difficult to fabricate the high speed transistor. Hence, according to the present invention a fabrication method is devised for reducing the base width of the bipolar transistor with control electrode.

Also, the bipolar transistor with control electrode as shown in FIG. 71 must control the voltage between the control electrode and the base region so that the base region may be in a weak inversion state, and always maintain its voltage during operation. Therefore, according to the present invention a semiconductor device has been devised which needs no application of voltage between the control electrode for the bipolar transistor with control electrode and the base region.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a transistor with high speed and a large current amplification factor, and a fabrication method which is highly coordinated with a MOS transistor manufacturing process.

Specifically, it is an object of the present invention to provide a semiconductor device capable of performing a low voltage operation which could not be implemented with conventional bipolar transistors through the same process as CMOS fabrication in the bipolar transistor with control electrode.

It is a second object of the present invention to allow a Bi-CMOS circuit necessary for driving a large load capacitor at a high speed to be operated at a low voltage.

It is a third object of the present invention to provide a semiconductor device which can be driven at low voltage and a fabrication method thereof in such a way as to make a transistor with control electrode of 0.3 .mu.m or less by, for example, a micro exposure process technique of about a 1 .mu.m rule.

It is a fourth object of the present invention to provide a bipolar transistor which is operable at a low voltage by controlling the voltage of a control electrode, and is capable of withstanding a large current, with a narrow base width and excellent high speed characteristic by forming the base region by diffusion of impurities.

It is a fifth object of the present invention to readily fabricate a bipolar transistor with control electrode in a multi-emitter structure, which is applicable for use where a large current is required.

In the light of the above objects, and as a result of research the invention as set forth below has been attained.

That is, a semiconductor device of the present invention comprising an insulating region residing adjacent to a first semiconductor region, a control electrode residing via said insulating region, a second semiconductor region and a third semiconductor region, which have an opposite conduction type to that of said first semiconductor region, residing adjacent to and carrying therebetween said first semiconductor region, characterized in that in the state where said first, second and third semiconductor regions and said control electrode are grounded, said first semiconductor region in contact with said insulating layer is adjusted to be in a weak inversion state, and the potential of said control electrode and that of said first semiconductor region are electrically coupled to be operable.

A structure may be produced in which said first, second and third semiconductor regions reside on a bulk semiconductor, and semiconductors in said first, second and third semiconductor regions are arranged in contact with one another in the order of said second, first and third semiconductor regions.

It is desirable that said first, second and third semiconductor regions reside on an insulating substrate, and said first, second and third semiconductor regions are in contact with one another in the order of said second, first and third semiconductor regions, and in contact with said insulating substrate to have a structure of a Silicon on Insulator (SOI).

Also, it is desirable to set the work function of said control electrode material, the film thickness of said insulating layer, and the impurity concentration of said semiconductor region of the first conduction type so that said first semiconductor region in contact with said insulating layer may be in a weak inversion state.

Herein, it is possible that said control electrode is gate electrode, said first semiconductor region is a channel region directly below the gate electrode, said second and third semiconductor regions are a source region and a drain region to constitute a MOS transistor.

It is desirable that said first semiconductor region in contact with said insulating layer is in weak inversion state, and a depletion layer with MOS structure reaches said insulating substrate.

Also, it is desirable to set the work function of said control electrode material, the film thickness of said insulating layer, and the impurity concentration and film thickness of said first semiconductor region so that said first semiconductor region in contact with said insulating layer may be in weak inversion state.

Also, a bipolar transistor may be constituted in such a way that said first semiconductor region is a base region, said second and third semiconductor regions are an emitter region and a collector region, respectively.

Herein, the distance from emitter junction of said base region to collector junction is desirably equal to or less than 0.3 .mu.m.

Then, it is desirable that a bipolar transistor is constituted by forming the base region of said first semiconductor region by diffusion of impurities from the substrate surface, and forming said control electrode via an insulating film on the side of said base region.

Herein, the impurity concentration profile is said base region is desirably smaller from emitter junction to collector junction.

Also, two or more emitter regions serving as said second semiconductor region are desirably formed.

It is desirable that a thin oxide film is provided between the emitter region serving as said second semiconductor region and the emitter electrode, the conduction between said emitter region and said emitter electrode being made through the use of a tunnel current.

Then, a SOI (Silicon on Insulator) is desirably constituted with said semiconductor device made on an insulator.

the emitter region serving as said second semiconductor region is desirably constituted from a semiconductor having a larger forbidden band width than the semiconductor constituting said base region.

Herein, said semiconductor having a larger forbidden band width is desirably constituted of microcrystalline or an amorphous semiconductor.

Also, said semiconductor having a large forbidden band width is desirably constituted of SiC.

The present invention also encompasses the fabrication methods thereof. That is, the first fabrication method of the present invention is a fabrication method for a semiconductor device wherein an emitter region, a base region and a collector region are laterally formed on a SOI substrate having a semiconductor region on the surface of an insulating layer or insulator, and comprising an electrode for controlling the potential of the base region via an insulating film, characterized by including the following processes (A) to (E) which are performed in sequence:

(A) a process of forming a first insulating film region and a second insulating film region having a greater thickness than that of said first insulating film region on said semiconductor layer of the first conduction type provided on the surface of said insulating layer or said insulator,

(B) a process of introducing and activating impurities of the second conduction type into said second semiconductor region below said first insulating film region with said second insulating film region as a mask,

(C) a process of depositing a conduction film on said first and second insulating film regions and forming a control electrode by anisotropic etching to leave behind at least a side wall portion between said first insulating film region and said second insulating film region to be directly above the base region,

(D) a process of making said emitter region and said collector region by introducing and activating impurities of the first conduction type with said control electrode and said second insulating film region as a mask, and

(E) a process of electrically connecting said control electrode with a lead-out electrode of said base region.

The first fabrication method of the present invention may use a process for implanting C ions into the emitter region to constitute said emitter region of SiC.

Further, the first fabrication method of the present invention may use a process of implanting Si ions into said emitter region to constitute said emitter region of a microcrystalline semiconductor or an amorphous semiconductor.

The second fabrication method of the present invention is a fabrication method of a semiconductor device wherein an emitter region, a base region, and a collector region are vertically formed, and the conduction type of said base region is controlled via a control electrode, characterized by including at least the following processes (A) to (E) which are performed in sequence:

(A) a process of implanting impurity ions from the surface and performing heat treatment to make on a semiconductor substrate of the first conduction type, a well region of the second conduction type opposite to that of the semiconductor substrate,

(B) a process of making epitaxial growth to deposit a region with a small impurity concentration of the second conduction type equal to that of said well region on said well region (the region made through this process is hereinafter abbreviated as an epitaxial region),

(C) a process of implanting impurity ions of the second conduction type into a part of said epitaxial region to make said emitter region a high concentration impurity region,

(D) a process of selectively removing said epitaxial region,

(E) a process of depositing an insulating region on said epitaxial region,

(F) a process of depositing a low resistive region on said insulating region and removing it with only the portion serving as the control electrode left behind,

(G) a process of depositing a new insulating region to cover said control electrode,

(H) a process of making said base region by implanting impurity ions of the first conduction type into said epitaxial region, and

(J) a process of making said emitter region by implanting impurity ions of the second conduction type into said epitaxial region.

The second fabrication method of the present invention may use a process of implanting C ions in implanting impurity ions into said epitaxial region is said (J) process to constitute said emitter region of SiC to have a greater forbidden band width.

Further, the second fabrication method of the present invention may use a process of implanting Si ions and implanting impurity ions into said epitaxial region in said (J) process to constitute said emitter region of microcrystalline or amorphous Si to have a greater forbidden band width.

The second fabrication method of the present invention may include a process (K) of depositing a thin insulating film on said epitaxial region which becomes an emitter region to render the current from the emitter electrode to emitter region passing through the insulating film only a tunnel current after the (J) process.

The second fabrication method of the present invention may include a process of making a plurality of emitter regions by implanting impurity ions of the second conduction type into the plurality of regions in the process (C).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view for explaining a fabrication process of semiconductor device.

FIG. 2 is an explanation view showing a projection of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a graphic representation for explaining the comparison between the semiconductor device according to the embodiment of the present invention and a conventional semiconductor device with the gammel plot.

FIG. 4 is a graphic representation for explaining the comparison between the semiconductor device according to the embodiment of the present invention and the conventional semiconductor device with the gammel plot.

FIG. 5 is a band diagram for explaining an operation principle of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the constitution of a lateral bipolar transistor with control electrode fabricated by a fabrication method of the semiconductor device of the present invention.

FIG. 7 is a cross-sectional view of the lateral bipolar transistor with control electrode showing a fabrication process thereof in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 8 is a cross-sectional view of the lateral bipolar transistor with control electrode showing a fabrication process thereof in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 9 is a cross-section view of the lateral bipolar transistor with control electrode showing a fabrication process thereof in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 10 is a cross-sectional view of the lateral bipolar transistor with control electrode showing a fabrication process thereof in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 11 is a cross-sectional view of the lateral bipolar transistor with control electrode showing a fabrication process thereof in accordance with the fabrication method of the semiconductor device of the present invention.

FIGS. 12A and 12B are a perspective view and a plan view of the lateral bipolar transistor with control electrode showing a fabrication process thereof in accordance with the fabrication method of the present invention.

FIG. 13 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 14 is a plan view of the semiconductor device according to the embodiment of the present invention.

FIGS. 15A and 15B are graphic representations for explaining the characteristics of the semiconductor device according to the embodiment of the present invention.

FIG. 16 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 17 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention.

FIG. 18 is a plan view of the semiconductor device according to the embodiment of the present invention.

FIG. 19A and 19B are graphic representations for explaining the characteristics of the semiconductor device according to the embodiment of the present invention.

FIG. 20 is an explanation view of the fabrication process of a semiconductor device according to the embodiment of the present invention.

FIG. 21 is an explanation view of the fabrication process of semiconductor device according to the embodiment of the present invention.

FIG. 22 is an explanation view of the fabrication process of semiconductor device according to the embodiment of the present invention.

FIG. 23 is an explanation view of the fabrication process of semiconductor device according to the embodiment of the present invention.

FIG. 24 is an explanation view of the fabrication process of semiconductor device according to the embodiment of the present invention.

FIG. 25 is an explanation view of the fabrication process of semiconductor device according to the embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the fabrication process of an embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 27 is a cross-sectional view showing the fabrication process of an embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 28 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 29 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 30 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of a semiconductor device of the present invention.

FIG. 31 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 32 is a plan view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 33 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 34 is a plan view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 35 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 36 is a plan view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 37 is a plan view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 38 is a cross-sectional view showing the fabrication process of another embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 39 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 40 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 41 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 42 is a plan view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 43 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 44 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 45 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 46 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 47 is a plan view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 48 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 49 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 50 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 51 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 52 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 53 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 54 is a cross-sectional view showing the fabrication process of the embodiment in accordance with the fabrication method of the semiconductor device of the present invention.

FIG. 55 is a plan view showing an embodiment of a bipolar transistor of the present invention.

FIG. 56 is a cross-sectional view taken along the line A--A in FIG. 55.

FIG. 57 is a cross-section view for explaining the fabrication method of the bipolar transistor as shown in FIGS. 55 and 56.

FIG. 58 is a cross-section view for explaining the fabrication method of the bipolar transistor as shown in FIGS. 55 and 56.

FIG. 59 is a cross-sectional view for explaining the fabrication method of the bipolar transistor as shown in FIGS. 55 and 56.

FIG. 60 is a cross-sectional view for explaining the fabrication method of the bipolar transistor as shown in FIGS. 55 and 56.

FIG. 61 is a cross-sectional view for explaining the fabrication method of the bipolar transistor as shown in FIGS. 55 and 56.

FIG. 62 is a cross-sectional view for explaining the fabrication method of the bipolar transistor as shown in FIGS. 55 and 56.

FIG. 63 is a cross-sectional view showing another embodiment of a bipolar transistor of the present invention.

FIG. 64 is a cross-sectional view showing another embodiment of a bipolar transistor of the present invention.

FIG. 65 is a cross-sectional view showing another embodiment of a bipolar transistor of the present invention.

FIG. 66 is a cross-sectional view showing another embodiment of a bipolar transistor of the present invention.

FIG. 67 is an explanation view of a conventional example.

FIG. 68 is an explanation view of a conventional example.

FIGS. 69A and 69B are explanation diagrams of one example of a Bi-CMOS circuit.

FIG. 70 is a explanation diagram of input/output results of the Bi-CMOS circuit.

FIG. 71 is a cross-sectional view of a lateral bipolar transistor with control electrode.

FIG. 72 is a characteristic diagram for explaining the characteristics of the lateral bipolar transistor with control electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described below in connection with a semiconductor device of the present invention, comprising an insulating region residing adjacent to a first semiconductor region, a control electrode residing via said insulating region, a second semiconductor region and a third semiconductor region, which have an opposite conduction type to that of said first semiconductor region, residing adjacent to and carrying therebetween said first semiconductor region, characterized in that in the state where said first, second and third semiconductor regions and said control electrode are grounded, said first semiconductor region in contact with said insulating layer is adjusted to be in weak inversion state, and the potential of said control electrode and that of said first semiconductor region are electrically couple to be operable.

According to the present invention a lateral bipolar transistor capable of turning on at low voltages is provided in such a way that a control electrode is made via an oxide film on a base region of a conventional SOI lateral bipolar transistor, and the control electrode material, the thickness of oxide film, the impurity concentration of the base region (channel region), and the oxide film are set so that the base region in contact with the oxide film may be placed in a weak inversion state, with the control electrode, an emitter and a collector of the same device being grounded, (i.e., in a sub-threshold region at a gate voltage V.sub.G =0 volt, when operated as a MOS transistor with the electrodes being a gate electrode, a source, a channel, and a drain of the MOS transistor), thereby electrically coupling the base electrode with the control electrode to be operable. Herein, the sub-threshold region is defined as the region where the drain current changes exponentially when the gate voltage is changed.

To drive the bipolar transistor at low voltages, it is effective to provide a control electrode 205 to a lateral bipolar transistor on an SOI substrate 201 as shown in FIG. 1, and to electrically connect the control electrode 205 with a base electrode 207 to effect the driving (hereinafter such device is referred to as a "lateral bipolar with control electrode"). Such lateral bipolar transistor with control electrode is of the same constitution as the MOS transistor in which the control electrode corresponds to gate electrode, and the emitter, base and collector correspond to source, channel and drain, respectively. The way of driving this lateral bipolar transistor with control electrode is adapted to the lateral bipolar transistors on bulk Si, but its detailed mechanism is not yet fully grasped. To be operable at low voltages, it is necessary to lower the voltage V.sub.ON required to obtain on-state current. Accordingly, it is important to make clear the operation mechanism in the low voltage region. Note that FIG. 2 is a projection view of the lateral bipolar transistor as shown in FIGS. 19A and 19B.

According to the present invention, it has been found, as a result of research, that the lateral bipolar transistor with control electrode can be divided into three regions in terms of the current component. Referring to FIG. 72 as previously used, its outline will be described. FIG. 72 shows the I.sub.C -V.sub.BE characteristic of the lateral bipolar transistor with control electrode by the solid line and the characteristic of conventional lateral bipolar transistor by the broken line. Among the three regions of current characteristic, the first region is a subthreshold region of a MOS transistor for the current component, the second region is a mixture of the on=state current region of a MOS transistor and that of the lateral bipolar transistor, and the third region is a region of conventional lateral bipolar transistor for the current component.

In the case of conventional bipolar transistor, it is necessary that a high current gain (h.sub.FE) is attained to obtain a high collector current in the low voltage region. For this purpose, there is a need for a technology capable of making a base having a thickness of several thousands angstroms. On the other hand, in the lateral bipolar transistor with control electrode, the current value in the first region is determined by the position in the sub-threshold region when the lateral bipolar transistor with control electrode, the current value in the first region is determined by the position in the sub-threshold region when the lateral bipolar transistor with control electrode is operated as the MOS transistor, whereby the collector current can be controlled by a parameter other than the base width.

FIG. 3 shows the characteristic of the lateral bipolar transistor with control electrode fabricated so that the threshold voltage (in the sub-threshold region) may be different, when operated with the MOS transistor, and FIG. 4 shows the characteristic of MOS transistor. The lateral bipolar transistor with control electrode according to the present invention has the characteristic as represented by the curve B, and the conventional lateral bipolar transistor with control electrode has the characteristic as represented by the curve C. These two characteristics are compared in the following. In the curve C, the gate voltage V.sub.G =0 volt is not in the sub-threshold region, while in the curve B the gate voltage V.sub.G =0 volt is in the sub-threshold region. In the curve B, the collector current increases at the same time when the base voltage V.sub.BE becomes 0 volt or greater, whereby it can be found that the collector current reaches the on-state current (e.g., 1 .mu.A) at a lower voltage than in the curve C. That is, the .mu..sctn. transistor in the curve B is likely to turn on, but if further shifted to the on-state side to have the gate voltage V.sub.G =0 volt out of the sub-threshold region, the MOS transistor follows the curve A, whereby the collector current does not increase exponentially to have a device with smaller on/off ration.

That is, to obtain a lateral bipolar transistor with control electrode with high on/off ration and low on-state voltage, it is important that the device is designed such that the gate voltage V.sub.G =0 volt may occur in the sub-threshold region when operated as the MOS transistor. Further, at which point of the subthreshold region it is set should be determined in accordance with the specification of dark current to be given to the device (current value and dispersion).

The above design items are given by the expression as follows, with reference to FIG. 5. Herein, the sub-threshold region of the MOS transistor begins upon entering the weak inversion region. That is, this occurs when the surface potential .phi..sub.S and the Fermi potential .phi.F satisfy the inequality .phi..sub.S .gtoreq.100 .sub.F. Accordingly, each parameter is required to satisfy the following numerical expression 1. ##EQU1##

where .epsilon..sub.S is a dielectric constant of silicon, N.sub.B is an impurity concentration for the base, q is a charge elementary quantity, and .phi..sub.F is a Fermi potential, given by the expression 2. .phi..sub.MS is the difference in work function between silicon and the gate electrode, Q.sub.SS is an interface charge density, and C.sub.OX is an insulating film capacity between the base region and control electrode. The "-" symbol indicates the NPN type while the symbol "+" indicates the PNP type. The present invention involves controlling the insulating capacity C.sub.OX with the thickness of oxide film and the insulating material and .phi..sub.MS with the substrate concentration N.sub.B and the control electrode material to satisfy the above condition. Also, when the semiconductor layer is thinner and the depletion layer spread at the gate voltage V.sub.G =0 volt reaches the insulating layer for backing, such controls can be made by the thickness of semiconductor film.

The semiconductor device of the present invention may be a bipolar transistor constituted such that the first semiconductor region is a base region and the second and third semiconductor regions are the emitter and collector regions, respectively, with the distance from the emitter junction of the base region to collector junction being 0.3 .mu.m or less.

This semiconductor device can be fabricated by carrying out a fabrication method for the semiconductor device wherein an emitter region, a base region and a collector region are laterally formed on an SOI substrate having a semiconductor region on the surface of an insulating layer or insulator, and comprising an electrode for controlling the potential of the base region via an insulating film, characterized by including the following processes (A) to (E) which are performed in sequence:

(A) a process of forming a first insulating film region and a second insulating film region having a greater thickness than that of said first insulating film region on said semiconductor layer of the first conduction type provided on the surface of said insulating layer or said insulator,

(B) a process of introducing and activating impurities of the second conduction type into said second semiconductor region below said first insulating film region with said second insulating film region as a mask,

(C) a process of depositing a conduction film on said first and second insulating film regions and forming a control electrode by anisotropic etching to leave behind at least a side wall conduction film deposited in a stepped side wall portion between said first insulating film region and said second insulating film region to be directly above the base region,

(D) a process of making said emitter region and said collector region by introducing and activation impurities of the first conduction type with said control electrode and said second insulating film region as a mask, and

(E) a process of electrically connecting said control electrode with a lead-out electrode of said base region.

A fabrication method with the distance between emitter junction and collector junction being made 0.3 .mu.m or less will be described in detail.

FIG. 6 is a cross-sectional view showing the constitution of a lateral bipolar transistor with control electrode fabricated by the fabrication method of semiconductor device of the present invention, and FIGS. 7 to 12A and 12B are cross-sectional views showing the fabrication processes of the lateral bipolar transistor with control electrode by the fabrication method of semiconductor device of the present invention.

Note that an NPN-type lateral bipolar transistor with control electrode will be specifically described herein in connection with its structure and the fabrication method.

In FIG. 6, 101 is an insulating substrate, 102 is an N-type semiconductor layer, 103 is a second insulating film region having a film thickness T.sub.OX2, 104, 105 are first insulating film regions having a film thickness T.sub.OX1 (T.sub.OX1 <T.sub.OX2), 106 is a P-type region serving as the base region, 108 is a side wall, 109, 110 are emitter regions, which are N-type high density regions serving as the collector lead-out electrode region. The lateral bipolar transistor with control electrode according to the present invention utilizes the side wall 108 as the control electrode.

Next, the fabrication method of the lateral bipolar transistor with control electrode having the above constitution will be described below.

First, the second insulating film region 103 having a film thickness T.sub.OX2 and the first insulating film regions 104, 105 having a film thickness T.sub.OX1 are provided on the N-type semiconductor layer 102 on the insulating substrate 101, as shown in FIG. 7. Then, -T.sub.OX1 and T.sub.OX2 satisfy the following relation.

Next, ions of P-type impurity, such as boron are implanted, with the second insulating film region 103 as a mask, to form the P-type region 106, as shown in FIG. 8. Note that a part of the P-type region 106 is a base region, and this ion implantation can determine the base concentration of the lateral bipolar transistor. The concentration of P-type region 106 is preferably 1E17 cm.sup.-3 or greater.

Thereafter, a conduction film 107 such as polycrystalline silicon of high impurity concentration is deposited (FIG. 9) to form a side wall 108 by anisotropic etching (FIG. 10). In this case, the side wall on the side of collector electrode is removed. The removal can be made by etching with a resist provided only on the base side, for example. The width of the second insulating film region 103 may be about 1 .mu.m, and can be fully processed by exposure technique of micron order.

Then, N-type high concentration regions 109, 110 are formed by ion implantation, with the side wall 108 and the second insulating film region 103 as mask member (FIG. 11). In FIG. 11, 109 is an emitter region, 110 is a collector lead-out electrode region, and 106 is a base region. Since the base width can be determined by the width of side wall 108, the base width of 0.3 .mu.m or less can be realized without the use of micro exposure technique. Further, since the side wall which is a control electrode is masked, the control electrode can be formed directly above the base region is self-aligned manner. As a result, the capacity between control electrode and emitter can be suppressed to a small value. Also, owing to the existence of the second insulating film region 103, the capacity with respect to the collector can be reduced.

Note that in forming the emitter region 109 by ion implantation, the emitter region may be constituted of SiC having a greater forbidden band width by implanting C ions. In this case, the emitter region may be also constituted of microcrystalline Si or amorphous Si having a great forbidden band width by implanting Si ions.

There are several possible means for electrically coupling the control electrode with the base lead-out electrode, and one such means is shown in FIGS. 12A and 12B, for example. FIG. 12A is a perspective view showing the coupled stat