An image processing apparatus for effecting a series of processes for capturing an image and scrutinizing the captured image is disclosed. Each process in series of processes is selected from different modes of processes. Selector selects a mode of process for each of the series of processes. A preselected number of parameters are set for each of the selected mode of processes, and the set parameters are stored in a parameter memory sequentially. Mode data indicative of the selected modes for the series of processes are stored in the mode memory. A parameter number table informs the number of parameters necessary for each mode in each of the series of processes. When the parameters and the mode data are read from the parameter memory and said mode memory, respectively, parameter allocator allocates and produces proper parameters to corresponding modes of processes with reference to the parameter number table.

Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image processors to process digital image data, and providing one or more parametric controls within each of the two or more image processors. The aspects further include accessing chosen controls of the one or more parametric controls to modify the two or more image processors for alteration of the image processing.

A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associated control signals: a data valid signal and a winner-take-all signal. The final output of the adder tree equals (a) a sum of those input values whose data valid signals are asserted provided that none of the winner-take-all signals are asserted, or (b) a selected one of the input values if one of the winner-take-all bits is asserted. The selected input value is the one whose winner-take-all bit is set. The adder tree may be used to perform sums of weighted sample attributes and/or sums of coefficients values as part of pixel value computations.

A method for manipulating image data in a digital image capture device includes forming two or more image processors, and providing the two or more image processors in the digital image capture device. The method further includes linking the two or more image processors to form an image processing chain, the image processing chain capable of manipulating image data in sequential and serial manners. In a system aspect, the system includes a digital image capture device, the digital image capture device capable of processing digital image data through two or more image processors. The system further includes a central processing unit within the digital image capture device and capable of linking the two or more image processors to form an image processing chain, wherein the image processing chain manipulates the digital image data in sequential and serial manners.

A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one or more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.