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Claims  |
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What is claimed is:
1. In a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of said array to read
out a stored data row as a data unit, and a plurality of sense amplifiers coupled via respective bit lines to columns of memory cells of said array for amplifying respective bits of said data row, memory test circuit means comprising detection means for
detecting that all bits of said data row, coupled through said sense amplifiers, are in a mutually identical logic state,
wherein said detection means comprises a plurality of field effect transistors having respective gate electrodes coupled through said sense amplifiers to respective ones of a set of said bit lines corresponding to said predetermined plurality of
bits, and wherein drain electrodes of said field effect transistors are connected in common to a fixed resistive load.
2. A semiconductor memory circuit according to claim 1, wherein said detection means comprises first coincidence detection means for detecting that bits constituting said data row are all in a "0" logic state and second coincidence detection
means for detecting that said bits are all in a "1" logic state.
3. In a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of said array to read out a stored data row as a data unit, and a plurality of sense
amplifiers coupled via respective bit lines to columns of memory cells of said array for amplifying respective bits of said data row,
memory test circuit means comprising detection means for detecting that all bits of said data row, coupled through said sense amplifiers, are in a mutually identical logic state,
said detection means comprising first coincidence detection means for detecting that bits constituting said data row are all in a "0" logic state and second coincidence detection means for detecting that said bits are all in a "1" logic state,
wherein said memory cells are divided into normal-phase memory cells in which said "1" and "0" state bits of said stored data are represented by high and low potentials respectively, and inverse phase memory cells in which said "1" and "0" state
bits of stored data are represented by low and high potentials respectively, said normal phase memory cells being respectively coupled to corresponding normal phase bit lines, and wherein said first coincidence detection means comprises a first plurality
of field effect transistors having gate electrodes thereof coupled through said sense amplifiers to respective ones of said normal phase bit lines and having drain electrodes thereof connected in common to a first fixed resistive load, and said second
coincidence detection means comprises a second plurality of field effect transistors having gate electrodes thereof coupled through said sense amplifiers to respective ones of said inverse phase bit lines and having drain electrodes thereof connected in
common to a second fixed resistive load.
4. In a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of said array to read out a data row as a data unit, and a plurality of sense amplifiers
coupled via respective bit lines to columns of memory cells of said array for amplifying respective bits of said data row,
memory test circuit means comprising detection means for detecting that all bits constituting said data row, coupled through said sense amplifiers, are in an arbitrarily predetermined combination of "1" and "0" logic states,
wherein said memory cells are divided into rows of normal-phase memory cells in which "1" and "0" state bits of said stored data are represented by high and low potentials respectively, and rows of inverse phase memory cells in which said "1" and
"0" state bits of stored data are represented by low and high potentials respectively, said normal phase memory cells being respectively coupled to corresponding normal phase bit lines and said inverse phase memory cells being respectively coupled to
corresponding inverse phase bit lines, and wherein said detection means comprise a plurality of field effect transistors (5, 8) with gate electrodes of a first set of said plurality of field effect transistors being connected through said sense
amplifiers to respective ones of said inverse phase bit lines which correspond to bits of said data row that are to be tested for the "1" logic state, and with gate electrodes of a second set of said plurality of field effect transistors being connected
through said sense amplifiers to respective ones of said normal phase bit lines which correspond to bits of said data row that are to be tested for the "0" logic state, and wherein respective drain electrodes of said first and second sets are connected
in common to a fixed resistive load (2) said sets being respectively predetermined in accordance with said combination of "1" and "0" logic states.
5. In a semiconductor memory circuit having a array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of said array to read out a data row as a data unit, and a plurality of sense amplifiers
coupled via respective bit lines to columns of memory cells of said array for amplifying respective bits of said data row, memory test circuit means comprising:
first coincidence detection means for detecting that all odd-numbered bits of said data row are in a first logic state, and that all even-numbered bits of said data row are in a second logic state; and
second coincidence detection means for detecting that all of said odd-numbered bits of said data row are in said second logic state, and that all of said even-numbered bits are in said first logic state,
wherein said memory cells are divided into rows of normal-phase memory cells in which "1" and "0" state bits of said stored data are represented by high and low potentials respectively, and rows of inverse phase memory cells in which said "1" and
"0" state bits of stored data are represented by low and high potentials respectively, said normal phase memory cells being respectively coupled to corresponding normal phase bit lines and said inverse phase memory cells being respectively coupled to
corresponding inverse phase bit lines, wherein said first coincidence detection means comprises a first plurality of field effect transistors (8) having gate electrodes thereof coupled through said sense amplifiers to respective ones of said normal phase
bit lines and with drain electrodes of even-numbered ones of said first plurality of field effect transistors being connected in common to a fixed resistive load (19) and odd-numbered ones of said first plurality of field effect transistors being
connected in common to a second fixed resistive load (2), and wherein said second coincidence detection means comprises a second plurality of field effect transistors (5) having gate electrodes thereof coupled through said sense amplifiers to respective
ones of said inverse phase bit lines, with respective drain electrodes of odd-numbered ones of said second plurality of field effect transistors being connected in common to said first resistive load and respective drain electrodes of even-numbered ones
of said second plurality of field effect transistors being connected in common to said second resistive load.
6. In a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of said array to read out a data row as a data unit, and a plurality of sense amplifiers
coupled via respective bit lines to columns of memory cells of said array for amplifying respective bits of said data row, memory test circuit means comprising:
coincidence detection means for detecting that all bits of said data row are in a "1" logic state and producing a first output signal as a detection result, for detecting that all bits of said data row are in a "0" logic state and producing a
second output signal as a detection result, for detecting that all even-numbered bits of said data row are in a "0" logic state and all odd-numbered bits of said data row are in a "1" logic state and producing a third output signal as a detection result,
and for detecting that all even-numbered bits of said data row are in a "1" logic state and all odd-numbered bits of said data row are in a "0" logic state and producing a fourth output signal as a detection result;
signal combining means for producing a plurality of predetermined combinations of said first, second, third and fourth output signals; and
test mode selection means controllable for selecting one of said combinations in accordance with a predetermined test data pattern that has been previously stored in said memory cells as said data row,
wherein said memory cells are divided into rows of normal-phase memory cells in which said "1" and "0" state bits of said stored data are represented by high and low potentials respectively, and rows of inverse phase memory cells in which said
"1" and "0" state bits of stored data are represented by low and high potentials respectively, said normal phase memory cells being respectively coupled to corresponding normal phase bit lines and said inverse phase memory cells being respectively
coupled to corresponding inverse phase bit lines and said inverse phase memory cells being respectively coupled to corresponding inverse phase bit lines, and wherein said coincidence detection means comprises a plurality of field effect transistors (38),
with a first set of said field effect transistors having gate electrodes thereof connected through said sense amplifiers to respective even-numbered ones of said normal phase bit lines, a second set of said field effect transistors having gate electrodes
thereof connected through said sense amplifiers to respective odd-numbered ones of said normal phase bit lines, a third set of said field effect transistors having gate electrodes thereof connected through said sense amplifiers to respective
even-numbered ones of said inverse phase bit lines, and a fourth set of said field effect transistors having gate electrodes thereof connected through sense amplifiers to respective odd-numbered ones of said inverse phase bit lines, wherein respective
drain electrodes of said first set of field effect transistors are connected in common to a first resistive load (23), respective drain electrodes of said second set of field effect transistors are connected in common to a second resistive load (24),
respective drain electrodes of said third set of field effect transistors are connected in common to a third resistive load (25), and respective drain electrodes of said fourth set of field effect transistors are connected in common to a fourth resistive
load (26), wherein said signal combining means comprise a plurality of logic gate circuits (27, 28, 29, 30) each coupled to a plurality of aid common connections to said resistive loads, and wherein said test mode selection means comprises means (31)
controlled for selecting one of a plurality of output signals produced from said logic gate circuits, in accordance with said test data pattern that has been stored as said data row.
7. In a video random access memory circuit including a random access memory having an array of memory cells, a serial access memory and a serial data input/output port, and means for writing into said serial access memory a data row which is
transferred serially through and serial data input/output port, for writing said data row in parallel into an arbitrarily selected row of said array of memory cells of said random access memory, for reading the contents of an arbitrarily selected memory
one of said rows of memory cells as a data row and writing said data row in parallel into said serial access memory, and for reading said data row from said serial access memory to be transferred out through said serial data input/output port,
memory test circuit means for comparing said data row that is read out from said memory cells with said data row in a condition prior to being written into and read out from said memory cells,
said memory test circuit means comprising a coincidence detection circuit (120) for comparing respective bits of a test data row, which are being read out from said random access memory after having been written into a row of memory cells
thereof, with corresponding bits of said test data row which are held in said serial access memory, and for producing a bi-level output signal as a test result,
wherein said coincidence detection circuit comprises a plurality of exclusive-OR gates (130) each coupled to receive one bit of said test data row which is held in said serial access memory, and a plurality of field effect transistors (131)
having gate electrodes thereof connected to respective outputs of said exclusive-OR gates and having drain electrodes thereof connected in common to a fixed resistive load.
8. A video random access memory circuit according to claim 7, wherein said memory test circuit means comprises:
recirculating shift register means (110);
comparator means (111) for comparing respective bits of a test data row which is being serially read out from said serial data input/output port after having been written into and read out from a row of said memory cells of said random access
memory, with corresponding bits of said test data row which are recirculating in said recirculating shift register means, to serially produce respective bits of test result data; and
selector circuit means (112) coupled between said serial data input/output port and each of said comparator means and recirculating shift register means and controlled by an externally supplied test mode signal, for transferring arbitrary data
between said serial access memory and said serial data input/output port in a normal mode of operation and for transferring said test result data from said comparator means to said serial data input/output port in a test mode of operation. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and in particular to a semiconductor memory which includes an internal test circuit for use in rapidly testing an array of memory cells of the semiconductor memory.
2. Description of the Related Art
With advances which have been made in recent years in semiconductor memory manufacturing technology, there has been a substantial increase in the number of elements which can be formed within a single chip of an integrated circuit. In the case
of a dynamic random-access memory (hereinafter referred to as a DRAM), the storage capacity of one chip can now be as high as 16 to 64 megabits, while in the case of a static random access memory (hereinafter referred to as a SRAM), the storage capacity
of one chip can be of the order of 4 to 16 megabits. With further advances that can be expected in future semiconductor device technology, greater increases can be anticipated in the amount of storage capacity achievable on one chip. One extremely
effective approach to increasing the storage capacity per chip, in the case of a DRAM or SRAM, is to minimize the number of circuit elements, as far as possible. However in the case of a very large-capacity semiconductor memory, due to limitations of
package size, number of IC pins, amount of power consumption, etc., it has also been found necessary to minimize the bit width (i.e. the number of bits which are conveyed in parallel) of the data I/O interface between the memory and the exterior. In the
case of a 16 megabit semiconductor memory for example, typical values used at present for the I/O data bit width are 1 bit, 4 bits, or 8 bits. Use of such a small value of I/O data bit width has the disadvantage that a very long time is required to test
all of the memory cells. In the case of a 16 megabit semiconductor memory having a 1-bit I/O data bit width, for example, only one bit can be written into or read out from the memory cells at each memory access operation. Thus to read or write data to
or from all of the memory cells, it is necessary to perform a total of at least 16 million accesses. Considering the case in which the "0" state and the "1" state have each to be written into and read out of every memory cell of a 16 megabit
semiconductor memory in order to test all of the cells, it becomes necessary to execute a total of (4.times.16,000,000) accesses. Thus the time required for memory testing becomes excessively long.
In the prior art, as attempts to reduce that problem of excessively long test time, methods have been proposed such as making the bit width of the internal data bus of the memory chip greater than the external I/O data bit width. In that way, by
supplying test data from the exterior and then expanding the test data to the larger bit width of the internal bus, the number of memory cells which can be written or read by a single memory access operation can be increased. Moreover it becomes
possible to execute internal comparison operations to determine whether data which are written into memory cells are identical to data that are subsequently read out from the cells, with only the comparison results being sent out from the memory to the
exterior. The time required for memory testing can thereby be further reduced.
In general, a video memory (referred to hereinafter as a VRAM) is a dual-port memory which is made up of a random access memory (referred to hereinafter as a RAM) with a corresponding random access I/O port, and a serial access memory (referred
to hereinafter as a SAM) together with a corresponding serial access I/O port. At present, storage capacity values of 1 to 4 megabits can be achieved for the RAM section of a 1-chip VRAM. The above problem of a long time being required for memory
testing also arises with the RAM section of a VRAM. In the prior art, testing of the RAM section of a VRAM has been executed in the same way as for testing a DRAM or SRAM, by utilizing the random access port to the RAM section of the memory, to input
test data and to output the test results.
FIG. 1A illustrates a memory cell array in an example of a prior art DRAM, which employs the folded bit line technique, whereby each bit is read out from a pair of memory cells as a differential signal appearing on a pair of bit lines, in order
to achieve a high speed of operation. FIG. 1B is a circuit diagram of a portion of the circuit of FIG. 1A, for describing differential data read and write operations. In FIG. 1A, numeral 1 denotes the memory cell array, in which respective memory cells
are designated as MC. Respective word line data rows are stored in corresponding rows of the memory cells MC, and an arbitrary one of these word line data rows can be selected during a read or write access operation by applying a selection signal to a
corresponding one of the word lines (WL0, WL1, . . . WLn). In practice, the word line selection is determined (by means which are well known in the art and are omitted from the drawings for simplicity) by bits of an address which is supplied to the
memory at the time of the read or write access. A selected word line data row is read out as a set of differential signals (i.e. appearing between the bit line pair BL0/BL0, the pair BL1/BL1, and so on) which are transferred via the pairs of bit lines
to respective ones of a set of differential sense amplifiers 2, to be amplified thereby. With the folded bit line technique, the successive rows of memory cells are alternately designated as normal phase rows and inverse phase rows. This signifies that
in each of the memory cells of a normal phase row (i.e. the rows which are selected by the word lines WL0, WL2, . . . WLn), a "1" state bit is represented by a high (e.g. positive) potential, referred to in the following as the "high" level, while a "0"
state bit is represented by a low (e.g. zero) potential, referred to in the following as the "low" level. However in each of the memory cells of an inverse phase row, a "1" state bit is represented by the "low" level while each "0" state bit is
represented by the "high" level. The even-numbered word lines (WL0, WL2, . . . ) will therefore be referred to as the normal phase word lines, and the odd-numbered word lines (WL1, WL3, . . . ) as the inverse phase word lines, and the bit lines
connected to the normal phase memory cells and to the inverse phase memory cells will similarly be referred to as the normal phase bit lines and inverse phase bit lines.
When a word line data row is selected by addressing the corresponding word line, then resultant amplified differential signals representing the data are produced from the set of differential sense amplifiers 2. A set of these differential
signals, representing a number of bits which is equal to the data bit width of the internal data bus 4, is selected from all of the differential signals, by the column selectors 3, and transferred to the internal data bus 4. That is to say, each bit
that is read out from or written into the memory cell array 1 from or to the exterior of the memory is transferred as a differential signal via a pair of lines of the internal data bus 4. The read operation will be described referring to FIG. 1B, in
which two of the array of memory cells 1, positioned at the intersections of the word lines WL0, WL1 and the bit lines Bl0, BL0 are designated as MC.sub.a and MC.sub.b respectively, the corresponding column selection transistors as 3a, 3b respectively,
and the corresponding data lines of the internal data bus 4 as 4a, 4b . Normally the bit lines BL0, BL0 are held at a potential which is midway between the "high" and "low" levels. As a result, if a "1" state bit is stored in MC.sub.a and the word line
WL0 is addressed to thereby read out the contents of memory cell MC.sub.a, a "high" level output will be supplied via the column selector 3ato the data line 4aand a "low" level output to the column selector 3b to the data line 4b, from the sense
amplifier 2a. A "high" level output, representing a "1" state bit will thereby be produced from the read amplifier, to be transferred to the external I/O data interface of the chip. If on the other hand a "1" state bit is stored in the memory cell
MC.sub.b, and the word line WL1 is addressed, then the "low" state contents of MC.sub.b will appear on the bit line BL0, so that again the sense amplifier 2awill supply a "high" level output to the data line 4aand a "low" level output to the data line
4b.
In a similar way, if "0" state data are stored in each of the memory cells MC.sub.a, MC.sub.b, the data lines 4a, 4b will be set to the "low" and "high" levels respectively when either of these memory cells is read out.
It can thus be understood that with such a folded bit line configuration, the number of conductors constituting the internal data bus 4 will be twice the data bit width of the internal data bus, since each bit must be transferred by a pair of
data lines of that bus.
The above description has been given assuming that the semiconductor memory is a DRAM, however a similar internal configuration, using such a folded bit line technique with data transferred as differential signal values, is commonly used for a
SRAM also.
As described hereinabove, the data bit width of the internal data bus 4 may be made larger than that of the external I/O interface.
FIG. 2 illustrates, in general form, the internal configuration of a prior art type of video random access memory (referred to in the following as a VRAM). The VRAM 100 is formed of a RAM (random access memory) 101 and a SAM (serial ,access
memory) 102, together with a random data I/O port 103 and address input port 107 for the RAM 101, and a serial data I/O port 105 and serial clock input terminal 106 for the SAM 102. Control signals for controlling the operation of the VRAM 100 are
supplied from an input terminal 104. An arbitrary row of data (e.g. the data for one scan line of a video signal frame) stored in a row of memory cells of the RAM 101 can be transferred in parallel from bit line outputs of the RAM 101 to the SAM 102, to
be then outputted serially from the serial data I/O port 105 in synchronism with the serial clock signal. Data can also be transferred serially in via the serial port 105 to the SAM 102 in synchronism with the serial clock signal, whereby an arbitrary
row of data can be written in parallel into the RAM 101 from the SAM 102. The internal configuration of the RAM 101 is generally as shown in FIG. 1A and described hereinabove. Respective bit lines of the RAM 101 are coupled (via sense amplifiers) to
corresponding parallel inputs of the the SAM 102, i.e. data rows which are transferred in parallel between the RAM 101 and the SAM 102 correspond to the word line data rows of the DRAM of FIG. 1A described above. In the prior art, during testing of the
RAM 101, in the same way as described for the memory of FIG. 1A, read and write data are transferred via the random data I/O port 103. To maximize the speed of memory testing by prior art methods, the data bit width of an internal data bus in the RAM
101 which communicates with the random data I/O port is made greater than that of the external I/O data bit width, as described hereinabove. That is to say, during each memory access operation in memory testing by a prior art method, the data bit width
of that internal data bus is utilized for reading/writing from/to the memory cells.
With such prior art types of semiconductor memory, in which the data bit width of the internal data bus is increased in order to increase the number of bits which can be simultaneously written into or read out from the memory cells in each memory
access, to thereby reduce the time required for memory testing, the bit width of the internal data bus would typically be made 16 bits, for example. Thus the internal data bus would have a total of 32 conductors. Hence, if the bit width of the internal
data bus is made large, the area of the chip surface that is occupied by the internal data bus will become excessively large, so that the overall chip size will tend to be increased. An increase in chip size will result in problems of increased levels
of connecting lead resistance and capacitance, which will cause a lowering of performance.
Thus it is difficult to achieve a sufficient reduction of the amount of time required for testing a semiconductor memory having a very large degree of storage capacity, simply by increasing the data bit width of the internal data bus of the
memory. This problem will become more severe in the case of new types of semiconductor memory which can be expected to be developed in the future, having even greater values of storage capacitance than those which are currently available.
SUMMARY OF THE INVENTION
It is an objective of the present invention to overcome the problems described above which arise with regard to testing a large-scale semiconductor memory. To achieve that objective, the present invention provides a simple built-in test circuit
within the semiconductor memory, whereby the time required to test all of the memory cells to be substantially reduced, by comparison with the prior art.
More specifically, according to a first aspect, the present invention provides, in a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of the array to
read out a stored data row as a data unit, and a plurality of sense amplifiers coupled via respective bit lines to columns of memory cells of the array for amplifying respective bits of the selected data row, memory test circuit means comprising
detection means for detecting that an arbitrarily predetermined plurality of bits of the selected data row, amplified by the sense amplifiers, are in a mutually identical logic state.
The detection means preferably comprises a plurality of field effect transistors having respective gate electrodes coupled through the sense amplifiers to respective ones of a set of the bit lines corresponding to the predetermined plurality of
bits, with the drain electrodes of the field effect transistors being connected in common to a fixed resistive load.
Moreover the detection means can comprise first coincidence detection means for detecting that bits constituting the data row are all in a "0" logic state and second coincidence detection means for detecting that the bits are all in a "1" logic
state.
In the case of a semiconductor memory circuit of a type in which the memory cells are divided into normal-phase memory cells in which the "1" and "0" state bits of the stored data are represented by high and low potentials respectively, and
inverse phase memory cells in which the "1" and "0" state bits of stored data are represented by low and high potentials respectively, the normal phase memory cells being respectively coupled to corresponding normal phase bit lines and the inverse phase
memory cells being respectively coupled to corresponding inverse phase bit lines, the first coincidence detection means preferably comprises a first plurality of field effect transistors having gate electrodes coupled through the sense amplifiers to
respective ones of the normal phase bit lines and having drain electrodes connected in common to a first fixed resistive load, and the second coincidence detection means preferably comprises a second plurality of field effect transistors gate electrodes
coupled through the sense amplifiers to respective ones of the inverse phase bit lines and having drain electrodes connected in common to a second fixed resistive load.
According to a second aspect, the present invention provides, in a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of the array to read out a data
row as a data unit, and a plurality of sense amplifiers coupled via respective bit lines to columns of memory cells of the array for amplifying respective bits of the data row, memory test circuit means comprising detection means for detecting that bits
constituting the data row, amplified by the sense amplifiers, are in an arbitrarily predetermined combination of "1" and "0" logic states.
If the memory circuit is of the aforementioned type in which the memory cells are divided into normal-phase memory cells in which "1" and "0" state bits of the stored data are represented by high and low potentials respectively, and inverse phase
memory cells in which the "1" and "0" state bits of stored data are represented by low and high potentials respectively, then the detection means is preferably formed of a plurality of field effect transistors with gate electrodes of a first set of the
plurality of field effect transistors being connected through the sense amplifiers to respective ones of the inverse phase bit lines which correspond to bits of the data row that are to be tested for the "1" logic state, and with gate electrodes of a
second set of the plurality of field effect transistors being connected through the sense amplifiers to respective ones of the normal phase bit lines which correspond to bits of the data row that are to be tested for the "0" logic state, and with
respective drain electrodes of the first and second sets being connected in common to a fixed resistive load, the sets being respectively predetermined in accordance with the aforementioned combination of "1" and "0" logic states.
According to a third aspect, the present invention provides, in a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of the array to read out a data row
as a data unit, and a plurality of sense amplifiers coupled via respective bit lines to columns of memory cells of the array for amplifying respective bits of the data row, memory test circuit means comprising:
first coincidence detection means for detecting that all odd-numbered bits of the data row, as counted along a row direction of the memory cell array, are in a first logic state, and that all even-numbered bits of the data row are in a second
logic state; and
second coincidence detection means for detecting that all of the odd-numbered bits of the data row are in the second logic state, and that all of the even-numbered bits are in the first logic state.
If the semiconductor memory circuit is of the type wherein the memory cells are divided into normal-phase memory cells in which "1" and "0" state bits of the stored data are represented by high and low potentials respectively, and inverse phase
memory cells in which the "1" and "0" state bits of stored data are represented by low and high potentials respectively, the normal phase memory cells being respectively coupled to corresponding normal phase bit lines and the inverse phase memory cells
being respectively coupled to corresponding inverse phase bit lines, then the first coincidence detection means is preferably formed of a first plurality of field effect transistors having gate electrodes coupled through the sense amplifiers to
respective ones of the normal phase bit lines and with drain electrodes of even-numbered ones of the first plurality of field effect transistors being connected in common to a fixed resistive load and odd-numbered ones of the normal phase bit lines being
connected in common to a second fixed resistive load, and the second coincidence detection means is preferably formed of a second plurality of field effect transistors having gate electrodes coupled through the sense amplifiers to respective ones of the
inverse phase bit lines, with respective drain electrodes of odd-numbered ones of the second plurality of field effect transistors being connected in common to the first resistive load and respective drain electrodes of even-numbered ones of the second
plurality of field effect transistors being connected in common to the second resistive load.
According to a fourth aspect, the present invention provides, in a semiconductor memory circuit having an array of memory cells, word lines respectively addressable for selecting an arbitrary row of memory cells of the array to read out a data
row as a data unit, and a plurality of sense amplifiers coupled via respective bit lines to columns of memory cells of the array for amplifying respective bits of the data row, memory test circuit means comprising:
coincidence detection means for detecting that all bits of the data row are in a "1" logic state and producing a first output signal as a detection result, for detecting that all bits of the data row are in a "0" logic state and producing a
second output signal as a detection result, for detecting that all even-numbered bits of the data row are in a "0" logic state and all odd-numbered bits of the data row are in a "1" logic state and producing a third output signal as a detection result,
for detecting that all even-numbered bits of the data row are in a "1" logic state and all odd-numbered bits of the data row are in a "0" logic state and producing a fourth output signal as a detection result;
signal combining means for producing a plurality of predetermined combinations of the first, second, third and fourth output signals; and
test mode selection means controllable for selecting one of the combinations in accordance with a predetermined data pattern that has been previously stored in the memory cells as the data row.
According to a fifth aspect, the present invention provides, in a video random access memory circuit including a random access memory having an array of memory cells, a serial access memory and a serial data input/output port, and means for
writing into the serial access memory a data row which is transferred serially through the serial data input/output port, for writing the data row in parallel into an arbitrarily selected row of the array of memory cells of the random access memory, for
reading the contents of an arbitrarily selected one of the rows of memory cells as a data row and writing the data row in parallel into the serial access memory, and for reading the data row from the serial access memory to be transferred out through the
serial data input/output port, memory test means consisting of coincidence detection means for detecting that respective bits of a data row read from the memory cell array are all in a predetermined logic state.
According to a sixth aspect, the present invention provides, in such a video random access memory circuit, memory test means comprising:
first coincidence detection means for detecting that all odd-numbered bits of the data row read from the array of memory cells, as counted along a row direction of the memory cell array, are in a first logic state, and that all even-numbered bits
of the data row are in a second logic state; and
second coincidence detection means for detecting that all of the odd-numbered bits of the data row are in the second logic state, and that all of the even-numbered bits are in the first logic state.
According to a seventh aspect the present invention provides, in such a video random access memory circuit, memory test means formed of coincidence detection means for detecting that all bits of the data row are in a "1" logic state and producing
a first output signal as a detection result, for detecting that all bits of the data row are in a "0" logic state and producing a second output signal as a detection result, for detecting that all even-numbered bits of the data row are in a "0" logic
state and all odd-numbered bits of the data row are in a "1" logic state, and producing a third output signal as a detection result, for detecting that all even-numbered bits of the data row are in a "1" logic state and all odd-numbered bits of the data
row are in a "0" logic state, and producing a fourth output signal as a detection result, and test mode selection means controllable for selecting one of the first, second, third and fourth output signals in accordance with a predetermined data pattern
that has been previously stored in the memory cells as the data row.
According to an eighth aspect the present invention provides, in such a video random access memory circuit, memory test circuit means for comparing a data row that is read out from the memory cells with the data row in a condition prior to being
written into and read out from the memory cells.
Such a memory test circuit preferably comprises recirculating shift register means, comparator means for comparing respective bits of a test data row which is being serially read out from the serial data input/output port after having been
written into and read out from a row of the memory cells of the random access memory, with corresponding bits of the test data row which are recirculating in the recirculating shift register means, to serially produce respective bits of test result data,
and selector circuit means coupled between the serial data input/output port and each of the comparator means and recirculating shift register means and controlled by an externally supplied test mode signal, for transferring arbitrary data between the
serial access memory and the serial data input/output port in a normal mode of operation and for transferring the test result data from the comparator means to the serial data input/output port in a test mode of operation.
Alternatively, such a memory test circuit means for a video random access memory circuit can consist of a coincidence detection circuit for comparing respective bits of a test data row, which are being read out from the random access memory after
having been written into a row of memory cells of that memory, with corresponding bits of the test data row which are held in the serial access memory, and for producing a bi-level output signal as a test result.
When the present invention is applied to a dynamic random access memory or a static random access memory in which data are stored in alternating rows of normal phase memory cells and inverse phase memory cells, it becomes possible to easily
detect by a single memory access whether all of that row of stored data (or an arbitrarily determined portion of that row of stored data) are all in the "0" state or are all in the "1" state. Since the number of bits in a word line data row will be very
much .greater than the data bit width of the internal data bus, a substantial reduction in the time required for testing the memory cell array can be achieved, by comparison with prior art arrangements for semiconductor memory testing.
Moreover when the present invention is applied to a video memory formed of a random access memory and a serial access memory it becomes possible to write into a row of memory cells of the random access memory, by a single memory access operation,
a row of data of an arbitrary test pattern, and to then immediately obtain the results of a test executed using that row of test data. In addition, it is possible to rapidly write the same row of test pattern data into each of the rows of memory cells
of the random access memory from the SAM, or to write an arbitrary row of test pattern data into an arbitrarily selected row of memory cells of the random access memory from the SAM.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a partial circuit diagram of a prior art RAM, showing an array of memory cells, and FIG. 1B shows details of part of FIG. 1A.
FIG. 2 is a block diagram of a prior art VRAM;
FIG. 3 is a partial circuit diagram of a first embodiment of the present invention, which is a RAM according to the present invention incorporating a memory test circuit which detects an all "0" state or all "1" state of a selected data row;
FIG. 4 is a partial circuit diagram of a second embodiment of the present invention, which is a RAM according to the present invention incorporating a memory test circuit that is an alternative to the test circuit of FIG. 3;
FIG. 5 is a partial circuit diagram of a third embodiment of the present invention, which is a RAM according to the present invention incorporating a memory test circuit for detecting that odd-numbere | | |
