System for producing a video-instruction set utilizing a real-time frame differential bit map and microblock subimages

We claim:

1. An integrated system optimized for a video-instruction set executing a plurality of applications for the storage, retrieval and scaleable formatting of video data, comprising:

a frame capture state;

first data processing means for the selective receipt of a local or remote signal, said first data processing means preprocessing the remote signal to produce a real-time frame differential bit map and microblocks subimages at said frame capture stage during a first period of time;

first controller means producing a run time object priority assignment signal in accordance with said microblock subimages during a second period of time subsequent to said first period of time;

second controller means for producing and prefetching look-ahead group instruction sequences for run-time execution of each of said microblock subimages in accordance with said run-time object priority assignment;

third controller means connected to said first data processing means for producing a run-time bandwidth requirement signal for each of said microblock subimages in accordance with said frame differential bit map, based upon said prefetching look-ahead group instruction sequences produced during said first period of time;

second data processor means connected to said first data processor means and said second controller means for scaleable data formatting of the microblock subimage data to a compatible internal format in accordance with said run-time object priority assignment;

third data processor means connected to said second data processor for encoding said compatible internal format of said microblock subimages to produce encoded microblock subimages;

fourth data processor means connected to said third data processor means for packaging said encoded microblock subimages based upon said prefetched instruction-look-ahead sequences to produce packaged data, said fourth data processor means further comprising a transmitter means for remote network transmission;

scaleable and reconfiguration data memory means for receipt of said packaged data and automatically self-configuring said packaged data into a plurality of internally storable entities, said scaleable and reconfiguration data memory means comprising at least one memory cell and their associated sensing, register, control, management and interface circuits, as well as a run-time adaptive decision-making logic means for receiving a set of run-time variables corresponding to user, application, and networking conditions, and producing a run-time executable data storage configuration in order to address, store, and retrieve the most recently-optimized run-time video articles or objects;

decoder means connected to said scaleable and reconfigurable data memory and said prefetched instruction-look-ahead sequences to produce a decoded signal; and

display means connected to said decoder means for post processing said decoded signal in accordance with said prefetched instruction-look-ahead sequences, said display means comprising a plurality of display, facsimile or printer adapters.

2. The system in accordance with claim 1 wherein said first data processing means comprises a video input capturer, a graphics input bit-map adaptor, a retrieval and storage register for said input signal processor, a frame differentiation processor; a motion processor, a foreground video object processor, a background image processor, at least one integrated sensor, and analog or digital preprocessor and storage means for non-video related data input.

3. The system in accordance with claim 1 wherein said first controller means comprises a priority assignment circuit, a priority reassignment circuit, and an object identification processor for producing run-time media object data types conforming to run-time bandwidth availability.

4. The system in accordance with 1 wherein said third controller means comprises a run-time attribute processor for producing run-time compression ratio, frame rate, and display resolution.

5. The system apparatus in accordance with claim 1 wherein said second controller means comprises a look-ahead-pipeline processor element for receiving an inbound differential video signal including bit-map, microblock, and motion vector, and producing a group of predefined instruction sequences for run-time execution.

6. The system apparatus in accordance with claim 1 wherein said second data processor means comprises an interpolating and extrapolating processor, an instruction and task prescheduler, a dynamic data formatter, a dynamic program scheduler and optimizer means and a scaling circuit means for reformatting an inbound signal to an appropriate internal format according to the run-time bandwidth requirement producing a coherent instruction bit stream for encoding processing, and controller means for invoking system calls for adjusting system clock rate, and resetting other system parameters.

7. The system apparatus in accordance with claim 1 wherein said third data processing means comprises a programmable encoder, a task queue, a pipeline buffer, and an interface circuit for selective on-board or off-board encoding of an internally formatted input still or motion video signal.

8. The system apparatus in accordance with claim 1 wherein said fourth data processing means comprises a multiple Layer protocol processing and control device, a pipeline buffer and register, an address generation device, and an external data interface circuit.

9. A system apparatus in accordance with claim 1 wherein said scalable and reconfigurable data is further comprised of a pointer manipulation circuit for receiving run-time requests to move, overlay, rotate, enlarge, or reduce a single or plurality of stored video articles, and producing the appropriate alternative referencing parameters for run-time manipulation of said video articles without physically modifying or moving their address or data.

10. A system apparatus in accordance with 1 wherein said decoder means comprises a programmable decoder, a task queue, a pipeline register and buffer, and an external data interface circuit.

11. An integrated system optimized for a video-instruction set executing a plurality of applications for the storage, retrieval and scaleable formatting of video data, comprising:

first data processing means for the selective receipt of a local or remote signal, said first data processing means preprocessing the remote signal to produce a real-time frame differential bit map and microblocks subimages;

first controller means producing a run time object priority assignment signal in accordance with said microblock subimages;

second controller means for producing and prefetching look-ahead group instruction sequences for run-time execution of each of said microblock subimages in accordance with said run-time object priority assignment;

third controller means connected to said first data processing means for producing a run-time bandwidth requirement signal for each of said microblock subimages in accordance with said frame differential bit map;

second data processor means connected to said first data processor means and said second controller means for scaleable data formatting of the microblock subimage data to a compatible internal format in accordance with said run-time object priority assignment;

third data processor means connected to said second data processor for encoding said compatible internal format of said microblock subimages to produce encoded microblock subimages;

fourth data processor means connected to said third data processor means for packaging said encoded microblock subimages based upon said prefetched instruction-look-ahead sequences to produce packaged data, said, fourth data processor means further comprising a transmitter means for remote network transmission;

scaleable and reconfiguration data memory means for receipt of said packaged data and automatically self-configuring said packaged data into a plurality of internally storable entities, said scaleable and reconfiguration data memory means comprising at least one memory cell and their associated sensing, register, control, management and interface circuits, as well as a run-time adaptive decision-making logic means for receiving a set of run-time variables corresponding to user, application, and networking conditions, and producing a run-time executable data storage configuration in order to address, store, and retrieve the most recently-optimized run-time video articles or objects;

a decoder means connected to said scaleable and reconfiguration data memory and said prefetched instruction-look-ahead sequences to produce a decoded signal; and

display means connected to said decoder means for post processing said decoded signal in accordance with said prefetched instruction-look-ahead sequences, said display means comprising a plurality of display, facsimile or printer adapters.

12. The system in accordance with claim 11 wherein said first data processing means comprises a video input capturer, a graphics input bit-map adapter, a retrieval and storage register for said input signal processor, a frame differentiation processor, a motion processor, a foreground video object processor, a background image processor, at least one integrated sensor, and analog or digital preprocessor storage means for non-video related video input.

13. The system in accordance with claim 11 wherein said first controller means comprises a priority assignment circuit, a priority reassignment circuit, and an object identification processor for producing run-time media object data types conforming to run-time bandwidth availability.

14. The system in accordance with claim 11 wherein said third controller means comprises a run-time attribute processor for producing run-time compression ratio, frame rate, and a display resolution.

15. The system apparatus in accordance with claim 11 wherein said second controller means comprises a look-ahead-pipeline processor element for receiving an inbound differential video signal including bit-map, microblock, and motion detector, and producing a group of predefined instruction sequences for run-time execution.

16. The system apparatus in accordance with claim 11 wherein said second data processor means comprises an interpolating and extrapolating processor, an instruction and task prescheduler, a dynamic data formatter, a dynamic program scheduler and optimizer means, and a scaling circuit means for reformatting an inbound signal to an appropriate internal format according to the run-time bandwidth requirement, producing a coherent instruction bit-stream for encoding processing, and controller means for invoking system calls for adjusting system clock rate, and resetting other system parameters.

17. The system in accordance with claim 11 wherein said third data processing means comprises a programmable encoder, a task queue, a pipeline buffer, and an interface circuit for selective on-board or off-board encoding of an internally formatted input still or motion video signal.

18. The system apparatus in accordance with claim 11, wherein said fourth data processing means comprises a multiple layer of protocol processing and control device, a pipeline buffer and register, and address generation device, and an external data interface circuit.

19. A system apparatus in accordance with claim 11 wherein said scaleable and reconfiguration data memory means is further comprised of a pointer manipulation circuit for receiving run-time requests to move, overlay, rotate, enlarge, or reduce a single or plurality of stored video articles, and producing the appropriate alternative referencing parameters for run-time manipulation of said video articles without physically modifying or moving their address or data.

20. The system apparatus in accordance with claim 11 wherein said decoder means comprises a programmable decoder, a task queue, a pipeline register and buffer, and an external data interface circuit.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention is related to an integrated circuit system based on a novel architecture entitled Video-Instruction-Set-Computing (VISC). More specifically, the present invention not only provides the core functions for a initial single chip realization, it can also be evolved into several generations of scalable high performance microprocessors. In particular, these novel VISC microprocessors can efficiently perform broad range of real time distributed video signal processing functions for applications such as interactive video, HDTV, and multimedia communications.

BACKGROUND OF THE INVENTION

Video signal processing, of motion and still image information, represents a critical functional component for many emerging computing systems. All of the prior video signal processing techniques, that have been proposed or implemented, employ a single or plurality of special purpose coprocessors based on the more traditional CISC or RISC computing principle. Consequently, these CISC/RISC host coprocessors can only partially improve the performance of specific subsystems, such as video encoding for multiple algorithms, high speed frame memory retrieval, and dynamic display management. The significant advantage is however, their ability to adapt with all existing DOS, WINDOW, or UNIX program data structures, through a traditional application programming interface.

Though practical, the speed and performance of these techniques are severely limited by the system throughput, the mismatch of data types, and the rigid CISC and RISC processor and memory system architecture, which have been designed to optimize the performance for text or graphics data types, but inefficient for real time interactive video processing. For example, see U.S. Pat. No. 4,777,620 to Shimoni, U.S. Pat. No. 4,772,946 to Hammer, U.S. Pat. No. 4,7227,589 to Hirose, and U.S. Pat. No. 4,398,256 to Nussmier. Typically, these special purpose host coprocessors would be implemented either as digital signal processing or custom application specific integrated circuit (custom ASIC's).

While the aforesaid patents teach various methods and apparatus for compressing and decompressing video data, improve frame memory subsystem performance, and enhancing the image quality of the display data. None of the aforesaid patents have ever directed themselves to the concept and structure of an effective and generalized system architecture, which would priortize the complex video data types, and optimize performance for video signal processing, while the traditional CISC or RISC application programs can still be efficiently performed.

This novel method and apparatus would interconnect all data processors among consumer, communications, and desktop computing, allows for individuals to select and convey multiple forms of information such as sound, image, graphics, data, and live video, automatically adjust to the available bandwidth, and capable of communicating in multiple bandwidths.

More specifically, although prior arts have shown CISC and RISC can be extremely suitable for dedicated desktop computing in processing the traditional text and graphics data types. None of the aforesaid patents have directed themselves to the concept and structure of further broadening the scope, and to develop a new computing platform, This new platform would not only interconnect the traditional desktop data processors such as computers and workstations, but it would also interconnect television, VCR's, CD player, cameras, multimedia sensors, or any other consumer and communications data processors in a totally integrated environment. Consequently, in this novel integrated computing environment, complex video data types declare much higher priority, and require much higher run-time performance as comparing to the traditional text and graphics data.

OBJECTS OF THE INVENTION

An object of the present invention is to define a integrated computing architecture which can accomodate communications, both transmission and retrieval, of all digitally-coded or algorithmic complex video data types.

Another object of the invention is to provide a novel integrated system architecture which is flexible and allows the control and communications among television, VCR's, CD player, cameras, sensors, or any other consumer and communications data processors, as well as the desktop data processors such as computer and workstations.

A still further object of the present invention is to provide for a novel process architecture which not only allows for digital coding techniques, but also can interface with traditional analog storage or transmission techniques.

A still further object of the present invention is to provide for a novel process architecture which allows the human users to interface with application program, and to select the appropriate media combination either before or during the communication session.

A still further object of the present invention is to provide for a novel process architecture which not only allows for an optimized system performance for complex video data types, but also can directly execute traditional desktop application programs using a CISC or RISC application coprocessor.

A still furhter object of the present invention is to provide for a novel process architecture which allows for an object-oriented real time operating system for complex video data types, and would accomodate traditional UNIX, DOS, or other traditional desktop operating systems.

Further objects and advantages of the present invention will become apparent from a consideration of the drawings and ensuing description of it.

SUMMARY OF THE INVENTION

Our present invention, VISC architecture, offers a totally new computing platform. Distinguish from all prior arts whcih have employed the traditional CISC or RISC computing disipline, VISC provides new methods and apparatus to organize a plurality of complex video data types, VISC also streamline, optimize and preschedule the video instruction clusters, and provide parallel or pipeline execution for these instructions. VISC also facilitates a CISC or RISC application coprocessor to conveniently process the traditional DOS or UNIX applications. Finally, VISC provides a distributed object oriented operating system facilities which can provide concurrent execution of traditional DOS or UNIX operating systems with the real time VISC video signal processing functions.

FIG. 2 shows the architecture principle of VISC (Video-Instruction-Set-Computing). Contrary to a traditional RISC or CISC architecture, the data processors and memory system are completely optimized to facilitate block oriented data instead of the traditional bit-oriented data streams. To be more specific, data information are organized according to selective internally reconfigurable block format, wherein these internal format can accomodate various processor configurations as well as data throughput. A scalable smart memory system architecture and memory management unit also provides the programmable data block addressing, frame memory management, block data manipulation, and associative block search.

In addition, VISC instruction sets can be readily compiled into a set of system look-up tables (SLUT's). Based upon the run time bandwidth constraints caused by either network conjestion or application request, the VISC instruction processors can prefetch a group of such CISC intructions, and designate them with various functional units for parallel or pipeline execution. Comparing to the more traditional cache memory techniques widely used in the existing RISC or CISC computer, The SLUT technique employes intelligent fast associative search schemes, and is able to perform scheduling, compilation, assembling, and simultaneously issuing instructions for execution and memory management.

In the VISC architecture, a smart memory system is connected to the functional units and scalable formatter, which can access, store, and transfer blocks of video data based on the selective internal format.

In FIG. 4, VISC architecture also illustrate an embedded RISC or CISC coprocessor (COP) element in order to directly execute the bit oriented application programs in DOS, Window, NT, Macintosh, OS2, or UNIX. In a more preferred embodiment, a VISC can include a real time object oriented operation system wherein concurrent execution of the application program and real time VISC based video instruction sets can be performed,

VISC architecture provides a single computing platform to perform a plurity of complex data types including motion video, voice, data, still image, and animated graphics. Consequently, it becomes feasible to integrate digital television, computer 108, cameras, 104s with human users and traditional application program.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the picturial illustration of a video instruction set computing (VISC) system environment.

FIG. 2 shows the core VISC integrated circuit system architecture in accordance with the present invention.

FIGS. 3A and 3B illustrate the major functional operations for a VISC (video instruction set computing) integrated circuit in accordance with the present invention.

FIG. 4 is a detailed block diagram illustrating a single chip VISC integrated circuit in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

GENERAL DISCUSSION

Referring now to the drawings wherein like reference numerals refers to similiar or identical parts throughout the several views, and more specifically to FIG. 1 thereof, there is shown a picturial representation of an novel integrated circuit VISC 112 (video instruction set computing) system apparatus. there is also shown a picturial illustration depicting most of the popular electronic apparatus relating to computer 108, communications, and consumers, presently available for the homes or offices. These include a VCR 102, CD Player, 104, television, personal computer 108, and fax machine.

It is Applicant's intention to disclose a unified system method towards integrated circuit design of all future generations' interactive television, video communications, and visual computing syetms.

It is also Applicant's intention to illustrate the architecture design of the VISC apparatus 112 according to this unified system design method.

Furthermore, The VISC 112 system apparatus allows for comaptibility with all existing electronic apparatus. VISC user/operator can control, complement, and utilize the functions of each electronic apparatus by means of the VISC 112 system apparatus. The VISC apparatus 112, being of compact size and shape, similar to that of a VCR 102, notebook PC, remote controller 116, or smaller, can locally integrate all existing electronic apparatus, and permit them to function complimentary with each other.

It is yet another Applicant's intention to further substantiate a distributed system architecture for VISC 112, in which a plurity of VISC's apparatus 112 can remotely communicate with each other and can also communicate with other non-VISC apparatus, regardless of whether other apparatus were analog, digital or algorithmic, and to encode or decode automatically to the available bandwidth, in a totally integrated system environment.

GENERAL INTRODUCTION OF VISC

FIG. 2 illustrates the core system architecture, operation, and methodology for a single chip design and implementation of VISC 112 integrated circuit. This VISC 112 microprocessor apparatus would make it possible to exchange a multitude of different forms of video articles over a wide range of communications networks. Prior arts have shown methods and apparatus to improve compression and decompression techniques for individual video coding algorithm and individual bandwidth ranges. However, since video coding algorithms are intrinsically incompatible with each other, there is a need for an apparatus to provide common interface whereby incompatible equipment can freely exchange video objects through interfacing with such apparatus.

The diagramatic representation illustrated in FIG. 2 comprises the following major system components. They are a preprocessing/motion processor (PREM) 202, a postprocessor (POST) 222, a bandwidth processor (BAND) 204, a formatting processor (FORM) 206, a encoding processor (ENC) 208, a packet processor (PACK) 210, a smart memory (SMART) 216, a transmission processor (TX) 212, a receiving processor (RX) 214, a decoding processor (DEC) 220, and a system controller (CON) 218.

The PREM 202 (preprocessing/motion processing) integrated circuit is able to capture, preprocess, differentiate, and generate a motion vector 302 signal either for a sequential input frames of live motion video, still photo image, or animated bit-mapped graphic files. Referring to FIG.2, The PREM 202 integrated circuit is further comprised of a video input capturer and a graphics input bit-mapper adapting elements. The video input capturer produces a digital video signal corresponding to any external video input conforming to RS-170, NTSC 246, PAL, or SCAM video formats. The graphics input bit-mapper, on the other hands, produces a digital signal corresponding to any animated graphics or still image input files conforming to PCX, GIF, EPS 248, TIFF, or alike popular file formats. The PREM 202 is also comprised of a memory element connecting to these input adaptors for receiving, storing, and transferring these digital video or bit-mapped graphics input signal. In a preferred embodiment, the PREM 202 integrated circuit is further comprised of a processor element which produces a differential frame signal and a motion vector signal corresponding to the sequential input frames of motion video, still image, or animated graphic files. the preocessor element produces a digital signal blocks conforming to the CCITT CIF or SIF video formatting standard. Both the processor element and the memory element can be specifically designed to optimize the performance of transferring, storage, retrieval, and processing of these CCITT CIF/SIF compatible digital signal blocks. In a more preferred embodiment, the PREM 202 is further comprised of a single or plurity of integrated sensor element, the sensor element produce the required inputs corresponding to the energy it received, the processor and memory element can efficiently perform similar analog and digital functions corresponding to other non-VISC foreign inputs including but not limited to text, data, and audio data streams.

The BAND 204 (bandwidth processor) integrated circuit is able to compute the required communication bandwidth for a local or remote digital video signal and generate a list of run-time attributes for the appropriate compression ratio, frame rate, and display resolution. The BAND 204 integrated circuit is also able to sensitize run-time networking traffic conditions, and dynamically reconfigure the aforementioned run-time attributes corresponding to the available run-time communication bandwidth. The BAND 204 integrated circuit is further able to sensitize user input or appliaction-specific requirements 356 and interactively update the aforementioned run-time attributes. Preferrably, the BAND 204 integrated circuit is further able to exchange a variety of digitally encoded input and output foreign video signals corresponding to intrinsically incompatible video coding algorithms whereby incompatible transmission, storage, retrieval, and display apparatus can inter-operate through such interface.

The BAND 204 integrated circuit is comprised of a look-ahead-pipelined processor element connected to the PREM 202 and RX (receiving processor) integrated circuit, which receives a local or remote inbound differential video signal and motion vector 302, it then calculate and produce a corresponding run-time attributes signal. The BAND 204 integrated circuit is also comprised of a controller element connected to the FORM 206 (format processor), ENC 208 (encoding processor) and CON 218 (system controller) integrated circuits, which receives a set of initial run-time attributes according to the algorithmically pre-determined default parameters retaining within the SLUT 234 (system look-up-table). Provided said video signal is requested by the CON 218 for outbound transmission, The BAND 204 integrated circuit is further comprised of a sensitizing 342 circuit connected to the TX 212 (transmission processor), which can intelligently analyze a plurality of networking traffic conditions, and dynamically reconfigure the run-time attributes corresponding to the available communication bandwidth. The aforesaid sensitizing 342 circuit will first initiate a request signal sending to the TX 212 along with the required communication bandwidth data, it will then either receive a grant signal from the TX 212 provided the network condition is sufficient, or TX 212 will issue a run-time bandwidth allowance signal to BAND 204 integrated circuit corresponding to the realistic network traffic condition. the BAND 204 integrated circuit will further produce a request for reset signal to the FORM 206, ENC 208, and CON 218 integrated circuits in order to reset the SLUT 234 table, and to reconfigure the appropriate run-time attributes. In a more preferred embodiment, the BAND 204 integrated circuit is further comprised of a user/application interface element connected to the FORM 206, ENC 208, and CON 218 integrated circuit which receives a plurity of signals regarding user/operator preference or application-specific requirements 356, it then send these signals to the processor element and dynamically produce a plurity of optional run-time attributes, the BAND 204 integrated circuit will further interact with the CON 218, FORM 206, and ENC 208 integrated circuits and to finalize the run-time attributes corresponding to the available communication bandwidth. In a further preferred embodiment, the BAND 204 integrated circuit will comprised of a interoperating circuit connected to the RX 214 and TX 212 integrated circuit in receiving a inbound video signal from RX 214 according to a SLUT 234 encoded video coding format, it then reset the SLUT 234 parameters and translate the inbound signal into a oubound signal according to another video coding standard, it further reformat the outbound signal and send to TX 212 for further transmission.

The FORM 206 (formatting processor) integrated circuit is able to statically compute the processing and storage bandwidth requirement corresponding to the run-time attribute lists of a digital input video signal, and translate them into an unified internal data format structure according to the run-time integrated circuit processing capabilities. The FORM 206 integrated circuit is also able to statically schedule, optimize, and produce the appropriate instruction and task sequences, then dynamically parse and partition them into a plurality of continuous signaling bitstreams for the fine grained pipelined or parallel encoding or decoding operations of the input video signal. Preferrably, the FORM 206 integrated circuit is further able to provide multidimensional rotation, shifting 360, preprocessing, and retrieval of the CIF or SlF compatible input signal blocks, The FORM 206 is further able to dynamically invoke system calls and look-up and reconstruct its run-time internal format corresponding to a plurity of system clock and SLUT 234 parameters options, external networking conditions, and interactive user appliaction requirements 356.

The FORM 206 integrated circuit is comprised of a interpolating and exterpolating processor element connected to the BAND 204 integrated circuit, which receives list of run-time attributes corresponding to a local or remote differential video signal and motion vector 302, and statically look-up nad formulate an internal data structure according to the pre-assigned system clock and SLUT 234 parameters. The FORM 206 integrated circuit is also comprised of a prescheduler connected to the ENC 208 and DEC 220 integrated circuit, which optimize, partition, and produce a coherent flow of instruction and task bitstreams for the required fine grained pipelined or parallel encoding and decoding operations. In a more preferrable embodiment, the FORM 206 is further comprised of a dynamic data format processor, which receives incoming data signals and perform multi-dimensional access, retrieval, rotating 358, shifting 360, and preprocessing according to the internally formatted data. the BAND 204 is further comprised of a dynamic program scheduler and optimizer connected to BAND 204 integrated circuit, which receives alert signal and further reformat the data signals corresponding to user application inputs and external networking conditions, in a further preferrable embodiment, the FORM 206 is further comprised of a scaling circuit connected to the SMART 216 (smart memory) integrated circuit, which invoke system calls and dynamically adjust system clock rate, aspect ratio, and SLUT 234 parameters in providing a linearly scalable VISC 112 system.

The ENC 208 (encoding processor) integrated circuit is able to encode a sequence of internally formatted input still or motion video signal and translate them into a bitstream of tokens corresponding to a plurality of pixel or frequency domain encoding algorithms. The ENC 208 is also able to encode the selective pixel or frequency domain algorithm at either macroblock, group of block, partial frame, or whole frame image level in order to achieve the selective VISC 112 system throughput. Preferrbly, the ENC 208 is further able to encode the algorithms employing additional external coprocessor elements. The ENC 208 integrated circuit is comprised of a instruction or task queuing circuit connected to the FORM 206, which receive and decode the prescheduled instruction task sequences for an entire encoding operation. The ENC 208 integrated circuit is also comprised of a pixel domain encoder and a frequency domain encoder circuits connected to the FORM 206 integrated circuit, which received the internally formatted still image or motion video signal, and produces bit streams of encoded tokens corresponding to a plurality of externally selectable image coding algorithms. The ENC 208 integrated circuit is further comprised of a pipelined buffer circuit connected to the SMART 216, and PACK 210 integrated circuits, which either transfer the encoded tokens to SMART 216 for internal storage or ship to the PACK 210 for outbound transmission. In a more preferrable embodiment, The ENC 208 is also comprised of a interface circuit which can pipeline, cascade, or parallelize a plurality of external encoding processor elements, and encode pixel and frequency domain algorithm at macroblock, group of block, partial frame, or whole frame level.

The PACK 210 (packet processor) integrated circuit is able to transcode or format video signals in CIF or SIF compatible macroblocks 306, it is also able to store, retrieve, or relay the transcoded CIF or SIF video signal in a single or plurality of packets or ATM (asyncronous transmission mode) cells for an inbound or outbound communication session. Preferrably, The PACK 210 is further able to correlate the CIF or SIF macroblocks 306 into VISC 112 internal format, and transcode voice, data, graphics, and other non-video 240 data types in CIF or SIF macroblock-based packets or cells.

The PACK 210 is comprised of a protocol processor element connected to the ENC 208 and TX 212 integrated circuit, which receives an encoded CIF or SIF compatible video signal macroblocks 306 from ENC 208, and generate and outbound a single or plurality of data, control, and maintainance packets to TX 212. The PACK 210 protocol processor element also connected to the DEC 220 and RX 214 integrated circuit, which receives an inbound video packet or cells from RX 214, and generates and relay a plurality of CIF or SIF compatible macroblocks 306 to DEC 220 for further decoding. The PACK 210 integrated circuit is also comprised of a pipelined buffer element connected to the TX 212 (transmission processor) and RX 214 (receiving processor) integrated circuit, which transmit and receive video signal in CIF or SIF compatible packets or ATM cells. The PACK 210 is further comprised of a address generation circuit connect to pipelined buffer element and F and SMART 216 integrated circuit, which access and transfer a CIF or SIF packets or cells into VISC 112 internal format via F, and then systematically enable the pipeline buffer circuit to download and store the reformatted CIF or SIF packets or cells in SMART 216. Reversely, the pipelined buffer element further retrieve directly the internal formatted packets and cells from SMART 216, and translate into CIF or SlF compatible macroblocks 306 via F. In a more preferred embodiment, the protocol control processor connected via TX 212 and RX 214 to a plurality of external PACK's 210, whcih establish, maintain, and terminate point-to-point and point-to-multipoint networking sessions, it further parse, assemble, or disassemble a video signal representation in CIF or SIF packets or ATM cells forms, according to specific TX 212 or RX 214 request and run-time networking conditions. In a further preferred embodiment, the protocol control processor element can transcode layerer signalling data structure according to OSI protocol architecture, which corresponds a plurality of user preference, application requirement, session control, transmission set-up, network control, and logical or physical link setup and termination, and the alike, and transcode non-video 240 data types in VISC 112 internal format.

The SMART 216 (smart memoty) integrated circuit is able to provide an optimized article-oriented architecture to address, store, and retrieve a single or plurality quantities of background still image and foreground motion video articles in accordance with the selected VISC 112 internally optimized format. The SMART 216 is also able to provide a set of run-time variables correspond with user, application, and networking conditions, and dynamically reconfigure itself to address, store, and retrieve these most-recently-optimized video articles. Preferrably, The SMART 216 is further able to provide a set of alternative referencing parameters in order to dynamically move, overlay, rotate, enlarge, or reduce a single or plurality of motion video articles at run-time without physically modifying or moving their address and data.

The SMART 216 integrated circuit is comprised of single or plurality of memory cells and their associated sensing, control, management, and interface circuits connected to the F integrated circuit, which receives a single or plurality of VISC's 112 internally modified CIF or SIF macroblocks 306, and produce an optimized data structure to perform an article-oriented addressing 308, storage, and retrieval of the still and motion video articles. The SMART 216 is also comprised of a run-time adaptive decision-logic circuit connected to the CON 218, BAND 204, and ENC 208 integrated circuit, which receives a set of run-time variables correspond with user, application, and networking conditions, and produces a run-time executable configuration in order to address, store, and retrieve these most-recently-optimized video articles. In a more preferred embodiment, the SMART 216 is further comprised of a pointer manipulation circuit connected to the ENC 208, DEC 220, CON 218, POST 222, and PREM 202 integrated circuits, which receives run-time requests to move, overlay, rotate, enlarge, or reduce a single or plurality of these stored video articles, and produces the appropriate alternative referencing parameters to dynamically manipulate these articles without physically modifying or moving their address and data. In further preferred embodiment, the SMART 216 is comprised of pipeline self-synchronization circuit connected to the CON 218, PREM 202, BAND 204, FORM 206, ENC 208, PACK 210, and DEC 220 integrated circuits, which sensitize and register the abnormal instances of PREM 202, BAND 204, F, ENC 208, DEC 220, and PACK 210 subsystem's pipelined operations, and send a system alert signal to CON 218 in requesting further fine-tuning of the system look-up-table, the CON