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Claims  |
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What is claimed is:
1. For a memory having a plurality of storage locations, each storage
location having a unique address, a method for testing said memory for
defects, comprising the steps of:
(a) writing an initial set of data to a particular address in said memory;
(b) reading a set of stored data from the address just written to;
(c) modifying the stored data to produce a set of modified data;
(d) writing the modified data to another address in said memory;
(e) repeating steps (b) through (d) until all addresses in said memory have
been written to; and
(f) comparing data values stored in said memory with reference data values
to determine whether said memory contains any defects.
2. The method of claim 1, wherein the step of modifying the stored data
comprises the step of:
processing the stored data through a data modifier to produce a set of
modified data, said data modifier having a property that, if the stored
dater does not contain an error, said data modifier will produce a set of
modified data which is distinct from any set of modified data previously
written into said memory.
3. The method of claim 2, further comprising the steps of:
(g) writing a complementary set of data, which represents the complement of
said initial set of data, to said particular address in said memory;
(h) reading a set of saved data from the address just written to;
(i) modifying the saved data to produce a set of altered data;
(j) writing the altered data to another address in said memory;
(k) repeating steps (h) through (j) until all addresses in said memory have
been written to; and
(l) comparing data values stored in said memory with a second set of
reference data values to determine whether said memory contains any
defects.
4. The method of claim 3, wherein the step of modifying the saved data
comprises the step of:
processing the saved data through said data modifier to produce a set of
altered data, said data modifier having a further property that, if the
saved data does not contain an error, said data modifier will produce a
set of altered data which is distinct from any set of altered data
previously written into said memory.
5. For a memory having a plurality of storage locations, each storage
location having a unique address, an apparatus for testing said memory for
defects, comprising:
a data modifier having a modifier input coupled to a data output of the
memory, and a modifier output coupled to a data input of the memory, said
data modifier receiving stored data from the data output of said memory,
and processing said stored data to produce a set of modified data at said
modifier output;
a controller for controlling operation of said memory, said controller
causing an initial set of data to be written to a particular address in
said memory, said controller further causing said memory to output a set
of stored data from the address just written to, and to store the modified
data received from said modifier output into another address, said
controller continuing to cause said memory to output a set of stored data
from the address just written to, and to store the modified data received
from said modifier output into another address, until all addresses in
said memory have been written to; and
a comparator coupled to the data output of the memory for comparing data
values stored in said memory with reference data values to determine
whether said memory contains any defects.
6. The apparatus of claim 5, wherein said data modifier has a property
that, if the stored data received at said modifier input does not contain
an error, said data modifier will produce a set of modified data which is
distinct from any set of modified data previously written into said
memory.
7. The apparatus of claim 6, wherein said controller further causes a
complementary set of data, representing the complement of said initial set
of data, to be written into said particular address, said controller
further causing said memory to output a set of stored data from the
address just written to, and to store the modified data received from said
modifier output into another address, said controller continuing to cause
said memory to output a set of stored data from the address just written
to, and to store the modified data received from said modifier output into
another address, until all addresses in said memory have been written to a
second time.
8. The apparatus of claim 7, wherein said comparator, after all locations
in said memory have been written to at least two times, further compares
data values stored in said memory with a second set of reference data
values to determine whether said memory contains any defects.
9. The apparatus of claim 8, wherein said data modifier has the following
additional property:
given said initial set of data as input, said data modifier generates a
first sequence of data values;
given said complementary set of data as input, said data modifier generates
a second sequence of data values; and
the data values in said second sequence are complementary to the data
values in said first sequence.
10. The apparatus of claim 6, wherein said data modifier receives eighteen
bits of data, denoted as D[18:1], at said modifier input, and provides
eighteen bits of modified data, denoted as MD[18:1], at said modifier
output, and wherein said data modifier derives said modified data MD[18:1]
as follows:
MD[i]=D[i-] for all i, except;
MD[8]=D[7] D[18] MCTL;
where denotes an exclusive-OR (XOR) operation and MCTL denotes a
complementary control signal.
11. The apparatus of claim 6, wherein said data modifier receives
forty-four bits of data, denoted as D[44:1], at said modifier input, and
provides forty-four bits of modified data, denoted as MD[44:1], at said
modifier output, and wherein said data modifier derives said modified data
MD[44:1 ]as follows:
MD[i]=D[i-1] for all i, except;
MD[28]=D27] D[44] MCTL;
MD[27]=D[26] D[44] MCTL;
MD[2]=D D[1] D[44]D MCTL;
MD[1]=MD[44];
where denotes an exclusive-OR (XOR) operation and MCTL denotes a
complementary control signal.
12. The apparatus of claim 6, wherein said data modifier receives fifty-six
bits of data, denoted as D[56:1], at said modifier input, and provides
fifty-six bits of modified data, denoted as MD[56:1], at said modifier
output, and wherein said data modifier derives said modified data
MD[56:1], as follows:
MD[i]=D[i-1] for all i, except;
MD[23]=D[22] D[56] MCTL;
MD[22]=D[21] D[56] MCTL;
MD[2]=D[1] D[56] MCTL;
MD[1]=MD[56];
where denotes an exclusive-OR (XOR) operation and MCTL denotes a
complementary control signal.
13. The apparatus of claim 6, wherein said data modifier receives
sixty-four bits of data, denoted as D[64:1], at said modifier input, and
provides sixty-four bits of modified data, denoted as MD[64:1], at said
modifier output, and wherein said data modifier derives said modified data
MD[64:1] as follows:
MD[i]=D[i-1] for all i, except;
MD[5]=D[4] D[64] MCTL;
MD[4]=D[3] D[64] MCTL;
MD[2]=D[1] D[64] MCTL;
MD[1]=MD[64];
where denotes an exclusive-OR (XOR) operation and MCTL denotes a
complementary control signal.
14. The apparatus of claim 6, wherein said data modifier receives
seventy-two bits of data, denoted as D[72:1], at said modifier input, and
provides seventy-two bits of modified data, denoted as MD[72:1], at said
modifier output, and wherein said data modifier derives said modified data
MD[72:1] as follows:
MD[i]=D[i-1] for all i, except;
MD[54]=D[53] D[72] MCTL;
MD[48]=D[47] D[72] MCTL;
MD[7]=D[6] D[72] MCTL;
MD[1]=MD[72];
where denotes an exclusive-OR (XOR) operation and MCTL denotes a
complementary control signal.
15. For a memory having a plurality of storage locations, each storage
location having a unique address, a method for testing said memory for
defects, comprising the steps of:
(a) writing an initial set of data to a particular address in said memory;
(b) reading a set of stored data from the address just written to;
(c) processing the stored data through a data modifier to produce a set of
modified data, said data modifier having a property that, if the stored
data does not contain an error, said data modifier will produce a set of
modified data which is distinct from any set of modified data previously
stored into said memory;
(d) writing said modified data into another address in said memory;
(e) repeating steps (b) through (d) until all addresses in said memory have
been written to, thereby allowing said data modifier to generate a
sequence of modified data values;
(f) comparing data values stored in said memory with reference data values
to determine whether said memory contains any defects;
(g) writing a complementary set of data, representing the complement of
said initial set of data, to said particular address in said memory;
(h) reading a set of saved data from the address just written to;
(i) processing the saved data through said data modifier to produce a set
of altered data;
(j) writing the altered data to another address in said memory;
(k) repeating steps (h) through (j) until all addresses in said memory have
been written to a second time, thereby allowing said data modifier to
generate a sequence of altered data values; and
(l) comparing data values stored in said memory with a second set of
reference data values to determine whether said memory contains any
defects;
wherein said data modifier has the additional property that, if the stored
data and the saved data do not contain any errors, then the altered data
values in said sequence of altered data values will be complementary to
the modified data values in said sequence of modified data values. |
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Claims |
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Description |
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FIELD OF THE INVENTION
The present invention relates generally to very large scale integration
(VLSI) chips, and more particularly, to a method and apparatus for testing
a random access memory embedded within a VLSI chip.
DESCRIPTION OF THE BACKGROUND ART
Many VLSI chips currently manufactured have one or more random access
memories (RAM) embedded within the chip as part of an overall device. The
RAM, because it is an integral part of the chip, needs to be tested to
determine whether it will function properly. Testing of the RAM may be
achieved in one of two ways. The first method involves the use of an
external testing device for accessing and manipulating the RAM. Because
the RAM is embedded within the chip, it is very difficult for the external
testing device to access the RAM. Hence, testing using the external
testing method is difficult and inefficient. An alternative testing method
involves the use of a built-in self-test (BIST) mechanism which is
incorporated into the chip to enable the chip to test its own RAM. Because
the BIST mechanism is a part of the chip and, hence, is internal to the
chip, it does not experience any difficulties in accessing the RAM. Thus,
the BIST mechanism tests the RAM much more effectively and efficiently
than the external device. For this reason, many VLSI chips include a BIS T
mechanism for testing on-chip RAM.
A typical BIST mechanism includes a test pattern generator and a test
response evaluator. The test pattern generator generates pseudo-random
patterns for the data and addresses and feeds these to the RAM. The test
response evaluator, in turn, implements a compaction method (such as
signature analysis) to evaluate the output data from the RAM. From the
evaluation of the RAM output data, the BIST mechanism determines whether
the RAM exhibits any faults.
A shortcoming of the current BIST mechanisms is that they cannot guarantee
complete fault coverage for certain RAM fault models. This is due to the
fact that, in traditional BIST techniques, fault coverage is estimated
through fault simulation. Instead of simulating all possible faults (which
is computationally impractical), only a sample of faults is simulated.
This means that the fault determination of the BIST mechanism represents
only a probability that the RAM is fault free. As with all probabilities,
there is a chance that the RAM may have faults despite the fact that it
passed the BIST test. For systems which demand high reliability, this
possibility of error cannot be tolerated. High reliability systems require
a BIST method and apparatus which can guarantee that any instance of
certain fault models will be detected. Currently, there is no BIST
mechanism believed to be available which can guarantee fault coverage for
certain RAM fault models.
SUMMARY OF THE INVENTION
The present invention provides a BIST method and apparatus which guarantees
that all stuck-at, address uniqueness, address coupling, and bit coupling
(within a particular storage location) faults within a memory are provoked
and detected. According to the method of the present invention, a memory
is put through three phases of testing. In the first phase, an initial set
of data is written to a particular address, preferably the first address,
in the memory. Data is read from the address just written to and then
modified to produce a set of modified data. The data is preferably
modified such that the set of modified data is distinct from any set of
data stored in a previous address in the memory. The modified data is
thereafter written to another address, preferably the next sequential
address, in the memory. The steps of reading data from the address just
written to, modifying the data, and writing the modified data to another
address are repeated until all addresses in the memory have been written
to. Thereafter, the data values stored in the memory are read and compared
to a set of reference data values to determine whether the memory exhibits
any faults. Since all addresses are accessed and written to in phase one,
phase one serves to provoke and detect all address uniqueness faults.
The steps performed in phase two are identical to those carried out in
phase one except that, in phase two, the first address in the memory is
initialized with a set of data which is the complement of the initial set
of data used to initialize the memory in phase one. This subtle change
causes each address of the memory to be written with a set of data which
is the complement of the set of data with which it was written in phase
one. Hence, phase two in effect complements each storage location in the
memory to ensure that each cell in each storage location is written with
both a 0 and a 1 value. If any cell is stuck at a particular value, phases
one and two will provoke and detect it.
At the end of phase two, each storage location in the memory will have been
written with a distinct set of data. In phase three, a particular address
of the memory (preferably the first address) is first selected. Data is
read from the selected address and modified to produce a modified set of
data. This modified data is then written back to the selected address.
Thereafter, data is read again from the selected address, the data is
modified, and the modified data is again written back to the selected
address. This process is repeated a selected number of times with the
selected number preferably being equal to the number of storage cells in
each storage location. Preferably, at some point during the process of
iteratively writing modified data to the selected address, each and every
pair of storage cells in the selected address simultaneously experiences
opposite binary values. After the above process is repeated the proper
number of times, another address is selected and this new address is
processed as described above. This process continues until all of the
addresses in the memory have been selected. By iteratively reading,
modifying, and writing data to a selected address, phase three provokes
all address coupling faults and all bit coupling faults within a storage
location. The faults provoked, if any, are detected by reading and
comparing the data values stored in the memory to a reference list of data
values. Together, phases one, two and three serve to provoke and detect
all stuck-at, address uniqueness, address coupling, and bit coupling
(within a storage location) faults in the memory.
The apparatus of the present invention preferably comprises a data
modifier, a comparator, and a controller. The controller is coupled to the
memory to selectively send address and control signals to the memory to
cause the memory to selectively input and output data. The controller
preferably comprises a plurality of counters for generating addresses and
a BIST controller. The data modifier, which has an input coupled to an
output of the memory, and an output coupled to an input of the memory,
receives output data from the memory and processes this data to produce a
set of modified data. This modified data is sent to the input port of the
memory. The controller, working together with the data modifier, causes
data to be read from, and modified data to be written to, the memory to
fill the memory with distinct sets of data. Thereafter, the controller
causes data to be read out of the memory and sent to the comparator to be
compared with a set of reference data values. If the comparator determines
that there is a discrepancy between the data from the memory and the
reference data, then an error signal is generated to indicate that the
memory contains a defect.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow diagram of the first phase of the method of the present
invention.
FIG. 2 is a block diagram of a test memory 40 and a magic function 42 to
illustrate the sequence of operation of phase one of the method of the
present invention.
FIG. 3 is, a flow diagram of the second phase of the method of the present
invention.
FIG. 4 is a flow diagram of the third phase of the method of the present
invention.
FIG. 5 is a block diagram representation of a system for implementing the
method of the present invention.
FIG. 6 is circuit diagram of a specific implementation of the data modifier
112 of FIG. 5.
FIG. 7A is a flow diagram of the sequence of operation of BIST controller
150 during phase one of the method of the present invention.
FIG. 7B is a flow diagram of the sequence of operation of BIST controller
150 during phase two of the method of the present invention.
FIG. 7C is a flow diagram of the sequence of operation of BIST controller
150 during phase three of the method of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Before describing the invention in detail, a brief discussion of the common
faults occurring within memories will be provided in order to facilitate a
complete understanding of the invention. A typical random access memory
comprises a plurality of storage locations, each storage location having a
unique address and a plurality of storage cells. Ideally, each address
should be uniquely addressable, each storage cell should be capable of
storing both a 0 and a 1, and each storage cell should operate
independently of the other storage cells. However, due to manufacturing
imperfections, some memories will contain defects. Usually, these defects
manifest themselves in the form of one or more fault conditions.
A first common fault condition is the stuck-at fault. Stuck-at faults occur
when a storage cell is frozen at a particular data value. No matter what
data is written into the cell, the cell always exhibits the same data
value. Another common fault condition is the address uniqueness fault.
This fault condition arises when one or more of the addresses in the
memory cannot be accessed. Address uniqueness faults are normally caused
by one or more of the memory's decoder outputs being stuck at a particular
value. A third common fault condition is the address coupling fault. The
result of such a fault is that accessing one address causes another
address to also be accessed. A fourth common fault condition is the bit
coupling fault. For a memory having this fault condition, changing a data
value in one storage cell affects the data value in another storage cell.
These four fault conditions are the most common manifestations of memory
defects. The present invention provides a method and apparatus for testing
a memory which provokes and detects all stuck-at faults, all address
uniqueness faults, all address coupling faults, and all bit coupling
faults within a particular storage location.
According to the method of the present invention, a memory is tested in
three phases. In phases one and two, data is iteratively read from one
address, modified, and written to another address to provoke and detect
all stuck-at and address uniqueness faults. In phase three, data is
iteratively read from each address, modified, and written back to the same
address to provoke and detect all address coupling faults and all bit
coupling faults within a particular storage location. Together, these
three phases provide a thorough test for verifying the accuracy and
integrity of the memory.
With reference to FIG. 1, the method of the present invention will now be
described in greater detail. FIG. 1 shows a flow diagram of the first
phase of the inventive method. As shown in FIG. 1, a memory is tested by
first writing 20 a set of initial data to a particular storage location in
the memory. This step is preferably carried out by writing 0x1 into the
first address in the memory. The "x" is used here to represent a variable
number of 0's. If each storage location in the memory has eight storage
cells, then the "x" represents six 0's. If each storage location has
eighteen storage cells, then the "x" represents sixteen 0's, and so forth.
After the initial data is written, data is read 22 from the address which
was just written to, namely, the first address. This data is then modified
24 to produce a set of modified data. Preferably, the data is modified by
passing it through a "magic" function. This magic function has several
important properties. One important property is that the magic function
ensures the modified data produced is distinct from any set of data stored
in a previous address in the memory. As will be explained later, this
property plays an important role in facilitating the detection of faults.
Other properties of the magic function will be disclosed and explained in
subsequent sections.
After the data from the first address is modified, the set of modified data
is written 26 to another address in the memory, preferably the next
address. Thereafter, it is determined 28 whether more addresses remain in
the memory to be written. If so, steps 22, 24, 26, and 28 are repeated to
again read data from the address just written to, modify the data, and
write the modified data to another address. This iterative process
continues until all addresses in the memory have been written to. At the
end of this process, if the memory has no defects, each memory location in
the memory has a distinct set of data. This is due to the fact that the
magic function ensures that each set of modified data written into the
memory is distinct from any set of data stored in a previous address in
the memory. The magic function guarantees data distinctiveness among the
memory locations if the memory is a 2.sup.k .times.n memory (2.sup.k
memory locations, each location having n bits or storage cells) and n is
greater than k. This condition is satisfied by most memories. After the
memory is fully written with data, the contents of the memory are read out
30 and compared 32 to a set of reference data values. The set of reference
values represents the data values which should be stored in the memory if
the memory is free of defects. Any deviation from the reference values
indicates a defect.
Phase one serves to provoke and detect all address uniqueness faults and
some stuck-at faults. To illustrate this more clearly, reference is made
to FIG. 2, which shows a block diagram of a test memory 40 having
addresses 0 to 2.sup.k -1 and n bits, and a magic function 42. According
to phase one, an initial set of data (0x1) is written to the first address
in memory. Hence, in address 0 of memory 40, there is stored a set of data
having the value of 0x1. The data stored in address 0 is then read and
sent to the magic function 42 to be modified. The modified data MD.sub.1
from the magic function 42 is thereafter written into the next address of
the memory 40, namely, address 1. The data in address 1 is then read and
outputted to the magic function, which modifies the data to produce
another set of modified data MD.sub.2. MD.sub.2 is then written into
address 2 of the memory. This process repeats until modified data MD.sub.z
is written into address 2.sup.k -1. Note that the data in each subsequent
address is determined based upon the data read out of the previous
address. This means that if a previous memory location contains a fault,
this fault will be reflected in the data of subsequent memory locations.
By checking the values stored in the memory, the fault can be detected.
To illustrate how phase one detects address uniqueness faults, suppose that
address 1 is inaccessible. This means that MD 1 cannot be written into,
nor can it be read from, address 1. Hence, when an attempt is made to read
from address 1, the data at the output of the memory 40 will not be equal
to MD 1. Since it is this erroneous output data which is modified and the
modified data written into address 2, the data MD.sub.2 in address 2 will
not have the proper data value. Since MD.sub.2 is in turn used to generate
MD.sub.3, MD.sub.3 will also contain an incorrect data value. In fact, all
subsequent memory locations will contain erroneous data values. Hence,
this one address uniqueness fault taints the data in the remainder of the
memory locations. By checking the data stored in the memory 40, this
address uniqueness fault can be easily detected.
A stuck-at fault can be detected in a similar fashion. Suppose, for
example, that 0x1 is written into address 0 but that, due to a stuck-at
fault, 0x0 is the data actually stored at address 0 . When data is read
from address 0, data value 0x0 will be outputted and sent to the magic
function 42. Using this incorrect data, magic function 42 produces
modified data MD.sub.1, which is written into address 1. Since magic
function 42 uses the erroneous data to generate MD.sub.1, MD.sub.1 will
have an incorrect data value. The data stored in subsequent storage
locations will also have incorrect data values. Thus, the stuck-at fault
can be detected by comparing the data stored in the memory to a set of
reference data values.
Phase one serves to provoke and detect all address uniqueness faults, but
it only provokes half of the stuck-at faults. This is because each storage
cell has only been written with one value, a 0 or a 1. To provoke and
detect all stuck-at faults, it is necessary to write each storage cell
with both a 0 and a 1 to determine whether the storage cell is capable of
storing both values. Phase two of the inventive method serves to provoke
and detect the stuck-at faults left untested by phase one.
Referring to FIG. 3, there is shown a flow diagram of phase two of the
method of the present invention. A brief review of FIG. 3 will reveal that
substantially the same steps are performed in phase two as in phase one.
The only difference is that in phase two, the complement of the initial
set of data used in phase one is written 50 to a particular address in the
memory. This set of complementary data is preferably written to the same
address as that to which the initial set of data was written in phase one.
Hence, in step 50 of phase 2, the complement of 0x1 (.about.(0x1)) is
preferably written to the first address in the memory. Thereafter, data is
read 52 from the address just written to, the data is modified 54 by the
magic function to produce a set of modified data, and the modified data is
written 56 to another address in the memory, preferably the next address.
It is then determined 58 whether other addresses remain in the memory to
be written. If so, steps 52, 54, 56, and 58 are repeated until all
addresses in the memory have been written to. Thereafter, the contents of
the memory are read out 60 and compared 62 to a set of reference data
values to determine whether the memory contains erroneous data. If so, a
defect in the memory is indicated.
The purpose of phase 2 is to write into each storage location in the memory
the complement of the set of data written into the storage location in
phase one. In effect, phase two complements the data stored in the memory.
At the end of phase 2, if the memory contains no defects, each storage
location in the memory has a distinct set of data, and each set of data is
the complement of the set of data previously written into the storage
location in phase one. In this manner, each storage cell is forced to
store both a 0 and a 1 value. If any cell is stuck-at a particular data
value, phases one and two will provoke and detect this defect.
It should be noted here that, preferably, the same magic function is used
in both phases one and two to modify data read from the memory. Since the
purpose of phase two is to complement the data generated in phase one, the
magic function preferably has the following additional property: Given the
complement of the set of initial data used in phase one, the magic
function is capable of generating a sequence of data which is
complementary to the sequence of data generated in phase one. That is,
given the complement of 0x1, the magic function 42 generates a sequence of
data wherein each set of data in the sequence is complementary to a
corresponding set of data generated by steps 42-48 (FIG. 1) of phase one.
This property allows the same magic function to be used in both phases,
and this, in turn, simplifies implementation of the inventive method.
After phase two is completed, the inventive method proceeds on to phase
three. With reference to FIG. 4, there is shown a flow diagram of phase
three of the inventive method, wherein the first step is to initialize 70
the memory with distinct data. This is preferably achieved by writing a
distinct set of data into each storage location. Recall that the magic
function ensures (if no faults are encountered) that each set of modified
data written into the memory is distinct from any set of data written into
a previous storage location. Thus, if phase three is carried out
immediately after phase two (as is preferred), and if no faults are
encountered in phases one and two, then each storage location in the
memory will already contain a distinct set of data. Thus, step 70 may not
need to be performed.
After the memory is initialized, phase three enters into a first loop,
wherein an address in the memory is selected 72. This selected address is
preferably the first address in the memory. Thereafter, a second loop is
entered to read 74 data from the selected address, to modify 76 the data
to produce a set of modified data, and to write 78 the modified data back
into the selected address. Preferably, the data from the selected address
is modified by passing the data through the same magic function as in
phases one and two. After the modified data is written back to the
selected address, it is determined 80 whether steps 74-78 have been
performed a selected number of times. If not, steps 74-78 are repeated.
Preferably, steps 74-78 are performed an n number of times where n
represents the number of storage cells in each storage location. After
nested loop 74-80 has been executed, it is determined 82 whether more
addresses remain in the memory to be processed. If so, another address,
preferably the next sequential address in the memory, is selected 72 and
this newly selected address is processed by the nested loop 74-80 as
described above. Steps 72-82 are repeated until all addresses in the
memory have been selected and processed. Thereafter, the contents of the
memory are read out 84 and compared 86 to a set of reference data. If
there is any discrepancy between the stored data and the reference data,
then a memory defect is indicated.
As mentioned above, the data from the selected address is modified using
the same magic function as in phases one and two. In order to provoke and
detect all address coupling faults and bit coupling faults within a
storage location, the magic function preferably has the following
additional properties: (1) the magic function ensures that the last set of
data written into each selected address is distinct from any set of data
stored in a previous address; and (2) the magic function ensures that, at
some point during the execution of nested loop 74-80, each and every pair
of storage cells in the selected address simultaneously experiences
opposite binary values.
Additional property (1) guarantees (if no faults are encountered) that the
data stored in each storage location of the memory is distinct. This
property is important when it comes time to detect the possible faults. To
illustrate this point, suppose that each memory location does not contain
a distinct set of data, but that locations 1 and 5 contain the same data.
When it comes time to check the contents of the memory, both locations
will output the same data. However, there is always uncertainty as to
whether the data came from location 1 or location 5. It is possible that
an address coupling fault exists between the two memory locations which
causes location 5 to be accessed when the address for location 1 is fed to
the memory. If such a fault exists, it will go undetected. Consequently,
in order to guarantee that all address coupling faults are detected, the
magic function preferably ensures data distinctiveness among the various
memory locations.
To illustrate that phase three provokes and detects all address coupling
faults, suppose that writing data to address 1 changes the data in address
3 so that address 3 now contains incorrect data. After addresses 1 and 2
are processed, address 3 is selected. In accordance with steps 74-78, data
is read from address 3, the data is modified, and the modified data is
written back to address 3. Because address 3 is first read from and then
written to, the change in the data caused by the address coupling fault is
preserved. Since this incorrect data is used to produce the modified data
which is written back to address 3, the data stored in address 3 will
reflect the error. Thus, when the contents of address 3 are later compared
to a corresponding reference data value, the address coupling fault will
be detected.
Suppose instead that writing data to address 3 changes the data in address
1. Such a fault will also be detected. Assuming that address 1 is
processed prior to address 3, the data change caused by the address
coupling fault is preserved in address 1 throughout phase three. When the
contents of address 1 are eventually compared to a corresponding reference
data value, the change in data will be detected. Hence, the address
coupling fault is exposed. Therefore, phase three provokes and detects all
address coupling faults.
Additional property (2) plays an important role in provoking all bit
coupling faults. To elaborate, when two storage cells are bit coupled, a
binary value written into one cell is also stored in another cell. Hence,
if two cells are bit coupled, they must store the same binary value. Since
property (2) guarantees that at some point during phase three, each and
every pair of cells in the selected address will simultaneously experience
opposite binary values, there will come a time when the bit coupled
storage cells must take,, on different values. Since the cells are
incapable of storing different binary values, the bit coupling fault will
manifest itself in the form of incorrectly stored data. This incorrect
data will alter the data sequence generated by the magic function, and
this data alteration will, in turn, be detected when the contents of the
memory are compared to the set of reference data. Thus, any and all bit
coupling faults within a single storage location are provoked and detected
by phase three. Together, phases one, two, and three provide a thorough
test for verifying the accuracy and integrity of a memory.
With reference to FIG. 5, there is shown a system 100 wherein the method of
the present invention is implemented. System 100 is preferably
incorporated into a VLSI chip (not shown) as part of an overall device to
allow the chip to self-test the on-chip memory 102. The memory 102 to be
tested preferably is a read/write memory having 2.sup.k storage locations,
each storage location having a unique address and n storage cells. As
mentioned previously, the magic function ensures data distinctiveness
among the various storage locations if n>k. For this reason, n is
preferably greater than k for memory 102. Memory 102 also preferably
comprises a decoder 104 for receiving and decoding address and read/write
control signals, an output port 106 for outputting data from the memory
102, and an input port 108 for receiving data to be stored within the
memory 102.
Note that input port 108 is coupled to the output of a 2-port data register
110 which, in turn, has its inputs coupled to a data bus and the output
from the data modifier 112. Register 110 is included in system 100 to
accommodate operation in both the standard and the self-test mode. In
standard operation, memory 102 receives data from other components on the
chip (not shown). Hence, the input port 108 should receive data from the
chip's data bus. In self-test mode, however, memory 102 receives data from
the data modifier 112. To accommodate both operational modes, register 110
receives data from both the data bus and the data modifier 112 but sends
only one of the two sets of input data to the input port 108. The select
control signal 114 determines which set of input data is sent to the input
port 108 of the memory 102.
The component in system 100 responsible for carrying out the magic function
described above is the data modifier 112. Data modifier 112 has a data
input port 114 coupled to the output 106 of the memory 102 for receiving
data D[n:1] therefrom, and a data output port 116 coupled to register 110
for outputting modified data MD[n:1] thereto. Modifier 112 also has a
control input port 118 for receiving a complementary control signal MCTL.
The MCTL signal determines the operational mode of modifier 112. If MCTL
is set to logic 0, modifier 112 operates in regular mode to generate a
particular data sequence using 0x1 as the initial set of data. If MCTL is
set to logic 1, modifier 112 operates in the complementary mode to
generate, using .about.(0x1) as the initial set of data, a data sequence
which is complementary to the data sequence generated in regular mode.
These two modes ensure that each set of data generated is complemented to
provoke all stuck-at faults in the memory 102.
Because data modifier 112 is responsible for carrying out the magic
function, the modifying function performed by modifier 112 preferably has
the properties articulated above for the magic function. While all
modifying functions have the same general properties, the specific
implementation of a modifying function will depend upon the dimensions of
the particular memory tested. Several examples of modifying functions are
provided below for specific memories.
Denoting input data to the modifier 112 as D[n:1] and modified data from
the modifier 112 as MD[n:1], the modifying function for a 2.sup.10
.times.18 memory is as follows:
for all i:
MD[i]=D[i-1];
except
MD[8]=D[7] D[18] MCTL,
where denotes an exclusive OR (XOR) operation.
A possible implementation of this modifying function is shown in FIG. 6.
Note that the implementation of modifier 112 includes only one XOR gate
120 and a plurality of wires. Most of the modified data bits MD[n:1] are
derived directly from one of the input data bits D[n:1]. The only bit
which requires a logic gate to generate is bit MD[8]. Note that gate 120
receives the MCTL signal as one of its inputs. This means that the value
of bit MD[8] is a function of the complementary control signal MCTL. For
the modifier 112 shown in FIG. 6, MD[8] is the only bit whose value is a
function of MCTL. While the effect of MCTL on the modified data is subtle,
this effect is sufficient to cause modifier 112 to generate a
complementary data sequence using .about.(0x1) as the initial set of data.
As a further example, the modifying function for a 2.sup.9 .times.44 memory
is as follows:
for all i:
MD[i]=D[i-1]; except
MD[28]=D[27] D[44] MCTL;
MD[27]=D[26] D[44] MCTL;
MD[2]=D[1] D[44] MCTL; and
MD[1]=D[44].
The modifying function for a 2.sup.8 .times.56 memory is:
for all i:
MD[i]=D[i-1];except
MD[23]=D[22] D[56] MCTL;
MD[22]=D[21] D[56] MCTL;
MD[2]=D[1] D[56] MCTL; and
MD[1]=D[56].
The modifying function for a 2.sup.4 .times.64 memory or a 2.sup.7
.times.64 memory is:
for all i:
MD[i]=D[i-1]; except
MD[5]=D[4] D[64] MCTL;
MD[4]=D[3] D[64] MCTL;
MD[2]=D[1] D[64] MCTL; and
MD[1]=D[64].
The modifying function for a 2.sup.6 .times.72 memory is:
for all i:
MD[i]=D[i-1];except
MD[54]=D[53] D[72] MCTL;
MD[48]=D[47] D[72] MCTL;
MD[7]=D[6] D[72] MCTL; and
MD[1]=D[72].
These modifying functions may be implemented in substantially the same
manner as that shown in FIG. 6 using direct connections and XOR gates.
Note that even for memories having a large number of output bits, the
modifying functions are rather simple. This means that the implementations
of the modifying functions are likewise simple. By keeping implementation
of modifier 112 simple, costs are reduced and testing speed is increased.
This is one of the major advantages of the present invention.
Referring again to FIG. 5, system 100 further comprises a comparator 160
and a reference data provider 162. Comparator 160 has a first data input
port coupled to receive data from the output 106 of memory 102, and a
second data input port coupled to receive reference data from data
provider 162. Comparator 102 compares the two sets of input data, and if
they are not equivalent, an error signal is generated at the output 164 of
the comparator 160. Preferably, the output 164 of comparator 160 is error
latched so that, if any discrepancy is detected between a set of reference
data and a set of data from the memory 102, the output 164 remains at the
error state regardless of the result of subsequent comparisons. Comparator
160 preferably further has a control port for receiving a sync control
signal. The sync control sign | | |
