A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divide-by-two binary. A binary code C representing a decimal integer value V is applied to the divider circuit. The frequency divider comprises circuits that enable the performance of a variable order division (V+1, V, . . . V-p, where p is a whole number greater than or equal to 1 and smaller than N-1) for one and the same binary code C.
A variable frequency dividing circuit adjusts the frequency dividing ratio by a non integer. The variable frequency dividing circuit includes a sequence storing part for storing an N-bit sequence data to output the N bits of the sequence data in parallel. The variable frequency dividing circuit also includes a sequence generator for receiving the N-bit sequence data from the sequence storing pan to generate a sequence control signal and a sequence control signal converter for converting the sequence control signal according to a frequency variation request to generate the converted sequence control signal. The variable frequency dividing circuit further includes a frequency divider for dividing a clock signal frequency according to the converted sequence control signal outputted from the sequence control signal converter and a clock signal generator for producing a clock waveform in accordance with the divided clock signal frequency.
