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Claims  |
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What is claimed is:
1. A memory system for storing data, said memory system coupled to a system
bus, said system bus further coupled to one or more caches, said memory
system comprising:
a memory;
control means for receiving address and control signals from said system
bus to control transfers of the data between said memory and said system
bus, said control means comprising an address path including a separate
read address path and a separate write address path, and a control path
including a separate read control path and a separate write control path;
and
sending and receiving means, coupled between said system bus and said
memory, and further coupled to said control means, said sending and
receiving means for transferring the data, under control of said control
means, between said system bus and said memory, said sending and receiving
means including at least one write data path, said at least one write data
path coupled to at least one write first-in-first-out (FIFO) buffer means
for temporarily storing data received from said system bus as part of a
bus transaction requiring the data to be stored in said memory to permit
priority processing of bus transactions requiring data to be read out of
said memory.
2. The memory system of claim 1, wherein said system bus is coupled to two
or more caches, and wherein said at least one data path is further coupled
to at least one reflective first-in-first-out (FIFO) buffer means for
storing a copy of data being transferred over said system bus from one of
said two or more caches to another one of said two or more caches
associated with a processor requesting the data being transferred.
3. The memory system of claim 1 or 2, wherein said control means further
comprises control register means for storing system information including
system bus size and memory structure information.
4. The memory system of claim 2, wherein said control means further
comprises an address comparator means for comparing a posted write
transaction address signal with a read transaction address signal to
determine priority of access to said memory.
5. A memory system for storing data, said memory system coupled to a system
bus, said system bus further coupled to one or more caches, said memory
system comprising:
a memory;
control means for receiving address and control signals from said system
bus to control transfers of the data between said memory and said system
bus, said control means comprising an address path including a read
address path and a write address path, and a control path including a read
control path and a write control path; wherein said write address path
comprises a first write address path for a first write transaction address
signal, and a second write address path for a second write transaction
address signal, including a write address register means for temporarily
storing said second write transaction address signal; and wherein said
write control path comprises a first write control path for a first write
transaction control signal, and a second write control path for a second
write transaction control signal including a write control register means
for temporarily storing said second write transaction control signal; and
sending and receiving means, coupled between said system bus and said
memory, and further coupled to said control means, said sending and
receiving means for transferring the data, under control of said control
means, between said system bus and said memory, said sending and receiving
means including at least one write first-in-first-out (FIFO) buffer means
for temporarily storing data received from said system bus before
transferring the received data to said memory.
6. The memory system of claim 5 further comprising an address source
multiplexer coupled to said first and second write address paths, and a
control source multiplexer coupled to said first and second write control
paths.
7. A memory system for storing data, said memory system coupled to a system
bus, said system bus further coupled to one or more caches, said memory
system comprising:
a memory;
control means for receiving address and control signals from said system
bus to control transfers of the data between said memory and said system
bus, said control means comprising an address path including a read
address path and a write address path, and a control path including a read
control path and a write control path;
sending and receiving means, coupled between said system bus and said
memory, and further coupled to said control means, said sending and
receiving means for transferring the data, under control of said control
means, between said system bus and said memory, said sending and receiving
means including at least one write first-in-first-out (FIFO) buffer means
for temporarily storing data received from said system bus before
transferring the received data to said memory; and wherein said memory
system is operated under an MBus protocol, and wherein said at least one
write FIFO buffer means is also for buffering data received during normal
write transactions and during all MBus write transactions.
8. A memory system for storing data, said memory system coupled to a system
bus, said memory system comprising:
a memory;
control means for receiving address and control signals from said system
bus to control transfers of the data between said memory and said system
bus, said control means including an address path through which said
address signals are processed and a control path through which said
control signals are processed, said address path comprising a read address
path and a write address path, said write address path comprising a first
write address path and a second write address path, and said control path
comprising a read control path and a write control path, said write
control path comprising a first write control path and a second write
control path; and
sending and receiving means for transferring the data between said system
bus and said memory, said sending and receiving means including at least
one write first-in-first-out (FIFO) means for temporarily storing data
received from said system bus; and wherein an address for the temporarily
stored data is being provided by one of said first and second write
address paths.
9. The memory system of claim 8, wherein said address path further
comprises a write address register means located in said second write
address path for temporarily storing a second write transaction address
signal while a first write transaction address signal is processed; and
wherein said control path further comprises a write control register means
located in said second write control path for temporarily storing a second
write control signal while a first write control signal is processed.
10. The memory system of claim 8 further comprising an address comparator
means for comparing a posted write transaction address signal with a read
transaction address signal to determine priority of access to said memory.
11. A memory system for storing data, said memory system coupled to a
system bus, said system bus further coupled to two or more caches, said
memory system comprising:
a memory;
control means for receiving address and control signals from said system
bus to control transfers of the data between said memory and said system
bus; and
sending and receiving means, coupled between said system bus and said
memory and further coupled to said control means, for transferring the
data between said system bus and said memory, said sending and receiving
means including at least one reflective first-in-first-out (FIFO) buffer
means for storing a copy of data being transferred over said system bus
from one of said two or more caches to another one of said two or more
caches associated with a processor requesting the data being transferred.
12. A memory system for storing data, said memory system coupled to a
system bus, said system bus further coupled to one or more caches, each of
said one or more caches associated with a processor, said processor for
processing the data, said memory system comprising:
a memory;
sending and receiving means for transferring data between said system bus
and said memory, said sending and receiving means including one or more
data channels, said one or more data channels having a write data path and
a read data path, said one or more data channels further including a write
first-in-first-out (FIFO) buffer means located in said write data path for
buffering data being transferred during a normal write transaction and
data being transferred during a write transaction occurring as part of a
cache purge operation, said one or more data channels further including a
reflective first-in-first-out (FIFO) buffer means located in said write
data path for storing a copy of data being transferred over said system
bus during a coherent-read transaction, said sending and receiving means
further comprising an error detection and correction (EDC) means located
in said read data path for detecting errors and correcting detected errors
in data obtained from said memory during read transactions; and
control means for providing control signals to said memory and to said
sending and receiving means.
13. The memory system of claim 12, wherein said control means further
comprises means for processing the data being transferred during a write
transaction having a data width which is less than a specified data width
of said memory, said means for processing further comprising a means for
instructing the data sending and receiving means to read data having the
specified data width from a location in said memory in which the data
being transferred is to be stored, said data sending and receiving means
further comprising means for combining the data being transferred with
said read data output from said EDC means under control of said control
means so that the data being transferred has a data width equal to said
specified data width.
14. The memory system of claim 12, wherein said memory is a dynamic random
access memory (DRAM). |
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Claims |
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Description |
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FIELD OF THE INVENTION
The present invention is related to a memory system, and more particularly
to a memory system which can be coupled with different buses to
efficiently support both single and multi-processor architectures.
BACKGROUND OF THE INVENTION
With the wide use and rapid development of random access memories ("RAM"),
especially dynamic random access memories ("DRAM"), the storage capacity
of memory devices doubles approximately every two years. In addition,
different types of memory devices, such as DRAMS with different storage
capacities, are now available in the market. They include DRAMS of sizes
256 k.times.1, 1 M.times.1, 4 M.times.1, 16 M.times.1, 256 k.times.4, 1
M.times.4, 4 M.times.4, and soon will include wider DRAMS with storage
capacity of 256 k.times.16 and 1 M.times.16. However, the questions of how
to provide a main memory structure which can efficiently support different
processor and bus systems, and allow the use of different types of memory
devices, have not yet been solved by the prior art. Further, if such a
main memory is provided, the next issue is providing a memory controller
which can efficiently control the access to such memory in accordance with
different processor system requirements.
In order to satisfy different processor system requirements, a variety of
different system buses have been introduced having different bandwidths to
support different processors. These buses may also have different bus
clock frequencies.
One bus available on the market is a bus called MBus, developed by Sun
Microsystems Inc., which is compatible with complementary metal-oxide
semiconductor (CMOS) technology. The MBus is normally classified into two
levels. Level 1 supports a single processor system. An example of a
uniprocessor system is generally shown in FIG. 1A, in which bus 2 is
coupled between processor 3 and memory controller 4, the latter connected
to memory 5. Another example of a uniprocessor system is shown in FIG. 1B,
wherein the processor 6 is coupled to a cache 7 which is further coupled
to a system bus 8. Level 2 supports multi-processor systems. An example of
a multi-processor system 10 is shown in FIG. 1C. A plurality of processors
11-12 (only two are shown) share common main memory 17 through bus 15 and
memory controller 16, with each processor 11 or 12 associated with at
least one local cache 13 or 14. An example of the level 2 MBus is the
SPARC.RTM. MBus Level 2 which can support normal read and write
transactions plus a number of additional transactions including coherent
invalidate transactions, coherent read transactions, coherent write and
invalidate transactions, and coherent read and invalidate transactions.
Each of these latter transactions requires that a local cache be
associated with each processor. Although the SPARC MBus is defined
currently with a 64 bit system bus operating at 40 MHz, system buses may
have different bus sizes, such as 32-, 64- and 128-bit data widths, and
different clock frequencies, such as 25 MHz, 33 MHz, 40 MHz, or 50 MHz.
Conventional memory systems are not flexible enough to support a variety of
buses which each have different bus sizes and clock rates. In particular,
conventional memory systems do not efficiently support bus systems which
are coupled to a number of processors, each of which is associated with at
least one local cache, and which share a common main memory.
For example, in some processor systems, cache controllers in copyback
environments may not have internal buffering allowing them to purge the
cache line internally, and then request a read of the main memory (a
DRAM), followed by a write of the old cache line back to the main memory.
They frequently are required to perform the write to main memory first,
followed by the read. This wastes processor cycle time waiting for the
missed cache line to be filled. Conventional memory systems have no
mechanism to support a cache purge operation. In addition, during a
coherent read transaction, conventional memory controllers can only
monitor the transaction without being able to convert the inhibited read
operation to write operation, thereby implementing a reflective memory.
Some conventional memory controllers are provided with a data buffering
device, such as a FIFO, to buffer normal write or read data. However, the
configuration of such controllers are generally not suitable for support
of the above mentioned cache purge or reflective read operations. Further,
such controllers cannot efficiently perform a data transaction between
main memory and the system bus when the data buffering device is occupied
by a previous transaction. In addition, short byte and long burst
transactions normally cannot be performed in an efficient and reliable
manner.
Finally, conventional memory systems are not flexible enough to enhance the
timing resolution of the memory in accordance with different system bus
clock frequencies.
Examples of these conventional memory systems are disclosed in the
following references: U.S. Pat. No. 4,954,951 issued on Sep. 4, 1990; a
product specification of Advanced Micro Devices titled "4M Configurable
Dynamic Memory Controller/Driver", product No. AM29C668, published in
March, 1990; a product specification of SAMSUNG titled "Dynamic RAM
Controllers", product No. KS84C31/32, published in November, 1989; a
product specification of Signetics titled "Intelligent DRAM Controller",
product No. FAST 74F1763, published on May 12, 1989; a product
specification of Signetics titled "DRAM and Interrupt Vector Controller"
product No FAST 74F1761, published on May 5, 1989; and an article by Brian
Case titled "MBus Provides Processor--Independent Bus", published in
Microprocessor Report on Aug. 7, 1991, pp. 8-12.
SUMMARY OF THE INVENTION
Thus, it is an objective of the present invention to provide a memory
system which has the flexibility for use with different types of system
buses which may have different bus sizes and clock frequencies.
It is another objective of the present invention to provide a memory system
which has a novel memory structure for supporting different processors and
bus systems. The memory structure includes a plurality of blocks, each of
which can be configured with a different type of memory chip which can be
of different sizes and configurations.
It is yet another objective of the present invention to provide a memory
system which can efficiently support all MBus Level 1 and Level 2
transaction types, cache purge operations and a coherent read with
simultaneous copyback operation.
It is still another objective of the present invention to provide a memory
system which can support 32-, 64- and 128-bit wide system buses, including
additional bits for parity generation and checking for data, parity
checking on the address, and additional control bits for increased
flexibility in supporting multiple processors.
It is still another objective of the present invention to provide a memory
system which can be coupled to different types of system buses having
different bus clock frequencies, and which provides enhanced memory timing
resolution.
It is still another objective of the present invention to provide a memory
system which provides a plurality of data channels to allow efficient data
transactions.
It is still another objective of the present invention to provide a memory
system which supports a plurality of blocks in a memory and provides
efficient access to one or more banks comprising each one of the blocks,
depending on bus and data sizes.
It is still further an objective of the present invention to provide a DRAM
controller which can reduce system bus traffic and enhance the efficiency
of multiple processors which share a common main memory.
In accordance with the objectives of the present invention, a
high-performance dynamic memory system is provided having a main memory
and a memory controller coupled between a system bus and the main memory.
The main memory includes at least one block which includes a plurality of
banks. Each of the banks has a predetermined memory bandwidth. Each block
of the main memory is constructed of one or more DRAM-type memory
elements.
The system bus can have different bus sizes and different bus frequencies.
The system bus is coupled to a plurality of processors, each of which is
associated with at least one local cache so that the main memory is shared
by all of the processors. In a first embodiment of the invention, the
system bus is an extended MBus which can support different processor
systems.
The memory controller includes control circuitry to receive address and
control signals from the system bus to control transfer of data to and
from the system bus, to and from main memory. The controller also includes
data sending and receiving circuitry to send and receive data to and from
the system bus, to and from the main memory, again under control of the
control circuitry.
The control circuitry includes an address signal path and a control signal
path. On the address signal path, the control circuitry is provided with a
read address path and a write address path. The write address path is
further provided with two write paths. One is used for providing a path
for the first data transaction address when consecutive write data
transactions occur on the system bus. The other is used for holding the
subsequent data transaction address while the first data transaction is
completed in the DRAM. On the control signal path, the control circuitry
is provided with a read control signal path and a write control signal
path. The write control signal path further includes a first path for a
first data transaction control signal and a second path for holding the
subsequent data transaction control signal.
The control circuitry is configured to provide program information with
respect to the structural parameters of main memory, system bus sizes, and
system bus frequency multiplication factors, to support different memory
types in main memory, different types of system buses which have different
bus sizes and bus speeds, and to enhance the timing resolution of main
memory.
The data sending and receiving circuitry includes a plurality of data
channels, each of which includes a write data path on which there is at
least one write first-in-and-first-out device (write FIFO). The write FIFO
temporarily maintain data received from the system bus to be stored into
main memory, and allows any of the processors to obtain data from the
memory at any time without loss of the data previously stored in the
FIFOs. Also on the write data path, there is at least one reflective
first-in-and-first-out device (reflective FIFO) to capture data on the
system bus which is transferred from a local cache associated with one of
the processors, to a local cache of another data requesting processor,
such that the data is simultaneously stored in the reflective FIFO and in
the local cache of the data requesting processor.
Each data channel also includes a read data path for transfer of read data
between the system bus and main memory. An error detection and correction
circuit is provided on the read data path which is used to support the
correcting of data.
In a second embodiment, two data channels are combined into a single data
channel unit in the form of an integrated circuit. A data sending and
receiving circuit can include two or more of these data channel units.
The control circuitry of the memory controller also includes control logic
which can identify and select the proper data channels and channel units.
This selection depends on the system bus size, the status of each data
channel, and the data sizes to be transferred. During the write of a data
burst, the channels in each unit can operate in an alternating fashion, so
that more data words within the main memory boundary can be accumulated in
the proper channels for efficient transfer into main memory.
In a third embodiment, main memory is structured as a plurality of blocks
each of which can be configured with a different DRAM type. Each block
includes a plurality of banks each populated with an identical DRAM type.
The main memory system also includes a frequency multiplier for multiplying
the bus frequency to provide a memory clock for enhancing the main memory
timing resolution. The frequency multiplier uses a bus frequency
multiplication factor produced by the programmable memory controller.
In a fourth embodiment, the programmable memory controller includes a
number of program registers which store programming functions. Among these
program registers, there is a command register which stores a variety of
information for control purposes, including the number of blocks in main
memory, and each block's size and its location in the processor's memory
maps, the bus size, the bus frequency multiplication factor and the data
bandwidth of the error detection and correction circuit. A timing register
is provided to store the timing of control signals for the main memory
read and write operations with an enhanced timing resolution. The memory
controller also includes a status register to store the status of each
data channel, such as the status of each FIFO (empty or not empty) on each
data channel and the error information occurring during data transactions.
There is also a location program register supplied to store information
describing the location of the blocks of main memory in the overall memory
map, which is connected to a comparator to allow correct selection of one
of the blocks in the memory when an incoming address matches one of the
programmed locations in the location program register. Associated with the
location program register, there is a mask register for storing mask bits
used to identify which processor's address bits should participate in the
address match.
The features and advantages of the present invention, including those
mentioned above and others not yet mentioned, will become apparent after
studying the following detailed description of the embodiments with
reference to the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows an example of a uniprocessor system,
FIG. 1B shows another example of a uniprocessor system,
FIG. 1C generally shows a multi-processor system in which the cache is
used.
FIG. 2 shows an embodiment of a main memory structure constructed in
accordance with the present invention.
FIG. 3 shows a block diagram of an embodiment of a control circuit of a
memory controller constructed in accordance with the present invention,
FIG. 4 shows a block diagram of an embodiment of a data sending and
receiving circuitry of a memory controller circuitry constructed in
accordance with the present invention,
FIG. 5 shows a block diagram of an embodiment of an error detection and
correction device (EDC) used in the data sending and receiving circuitry
of the memory controller constructed in accordance with the present
invention,
FIGS. 6A-6E show various embodiments of the data sending and receiving
circuitry arrangements for efficiently supporting system buses which have
different bus sizes, and data transactions which have different data
sizes.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following descriptions are directed to embodiments of a memory system
constructed in accordance with the present invention.
The memory system includes a DRAM structure and a unique DRAM controller
which is suitable for support of a large memory structure and buses having
different bus sizes, such as of 32-, 64- or 128-bit data widths, and also
having different bus clock frequencies, such as 25 MHz, 33 MHz, 40 MHz or
50 MHz. The memory system is also suitable for support of a number of bus
transactions to provide high-performance and high-efficiency memory
services to different processor systems. Such processor systems include
single processor systems as shown in FIGS. 1A and 1B, and multi-processor
systems as shown in FIG. 1C. The DRAM controller includes a DRAM control
device (DRAC) (FIG. 3) and a data sending and receiving device (DSRD)
(FIG. 4). The DRAC is coupled to the DSRD, and between the system bus and
the DRAM. The DSRD is coupled between the system bus and the DRAM. The
system bus can be either a single multiplexed address/data bus or contain
separate address and data buses. The bus interface is fully synchronous
and uses the rising edge of the bus clock. Bus signal definitions are an
extension of the MBus standard, so that an MBus can be used to support
additional processor systems.
The memory system of the present invention consists of a high-performance
address/control path and at least one high performance error detecting and
correcting data path. On the address/control path, the memory controller
is provided with a programmable DRAC for efficiently controlling memory
accesses for a number of bus systems and data transactions. On the data
path, the memory controller is provided with a DSRD which includes FIFO
buffers and an error detection and correction circuit (EDC). The DSRD
serves as a high-performance data buffer and demultiplexer on writes and
as an error corrector on reads. The DRAC and DSRD can be respectively made
into integrated circuits.
1. MEMORY STRUCTURE
Referring now to FIG. 2, an embodiment of a memory structure constructed in
accordance with the present invention is shown. The memory of FIG. 2 is
constructed using a plurality of DRAM chips.
The memory of FIG. 2 is organized into 4 blocks (blocks 0-3). Each block
consists of 4 banks (banks 0-3). Each bank is 39 bits wide (i.e. 32 data
bits and 7 error check bits). Banks 0-3 can be accessed simultaneously as
a 156-bit wide block, to achieve maximum memory performance.
The memory has 12 address lines (multiplexed as row and column addresses)
connected to the memory side of the memory controller. Each one of the
blocks of the main memory is coupled to one of four DRAM Read/Write [3:0]
lines, one of four Row Access Strobe control lines RAS [3:0] and one of
four column Access Strobe control lines CAS [3:0]. The memory is written
using the early write cycle, i.e. DRAM chips having common input/output
(I/O) will be controlled in the same manner as the DRAM chips having
separate I/O. External buffers are required to drive the substantial
address and control capacitance that exists when using DRAMS in such large
configurations.
The memory controller chip set (DSRD and DRAC) is designed to support
either 256 K.times.1 or 4, 1 M.times.1 or 4, or 4 M.times.1 or 4 and 16
M.times.1 DRAM chips. The controller will also support wider 4 Mbit DRAMS
(256 K.times.16) and wider 16 Mbit DRAMS (1 M.times.16) when these devices
become available. The maximum total capacity of the memory system can be
extended from four Mbytes using 256 K.times.1 DRAMS and populating a
single block, up to 1 Gbyte using 16 M.times.1 DRAMS and populating all
four blocks. Storage capacity is expandable in binary increments. DRAM
chip types remain identical within all four banks comprising a block,
however, each block may be populated with a different type of DRAM. The
possible configurations of the DRAM structure are given below in Table 1.
A multiple frequency clock (2.times. a 40 or 50 MHz bus clock, 3.times. a
33 MHz bus clock, or 4.times. a 25 MHz bus clock) input is provided to
control DRAM timing to 10 ns intervals (12.5 ns. for 40 MHz bus clocks).
Each 156-bit block has its data lines connected to the respective data
lines of the other blocks. The appropriate block is selected by asserting
its RAS and CAS lines. The 156 bits emerging from the selected block will
be steered through the DSRD where the data will be checked and corrected
if necessary. The error check bits are removed and the data is placed on
the bus. The memory can support 32-, 64- or 128-bit wide data paths.
TABLE 1
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CAPACITY CAPACITY
DRAM DRAM DRAM PER BLOCK
NUMBER PER SYSTEM
TYPE BANK BLOCK MBYTES OF BLOCKS
MBYTES
__________________________________________________________________________
256K X 1
256K X 39
4 X 256K
4 1-4 4-16
X 39
1M X 1
1M X 39
4 X 1M X
16 1-4 16-64
39
4M X I
4M X 39
4 X 4M X
64 1-4 64-256
39
16M X 1
16M X 39
4 X 16M
256 1-4 256-1024
X 39
256K X 4
256K X 40
4 X 256K
4 1-4 4-16
X 40
1M X 4
1M X 40
4 X 1M X
16 1-4 16-64
40
4M X 4
4M X 40
4 X 4M X
64 1-4 64-256
40
__________________________________________________________________________
It should be understood that each bank in a block of the main memory can
also be configured with other predetermined data widths, such as with 64
data bits.
2. BUS STRUCTURE AND DEFINITION
The system bus can comprise different buses, including the MBus which is
currently available on the market. In accordance with the present
invention, the bus signal specification may be reorganized and extended in
order to efficiently support multiple processor systems. In one
embodiment, a signal specification is provided for support of existing
32-, 64-, and 128-bit data buses, with additional bits for data parity
generation and checking, address parity checking, and control bits for
supporting different processor systems. Separate address and data lines
can be provided to support non-multiplexed system bus applications. The
signals can also be multiplexed to support MBus compatibility. The signal
specification, in cooperation with the memory system of the present
invention, not only supports all MBus Level 1 and Level 2 transaction
types including bursts, but also allows premature termination of burst
transactions, provides support of various burst orders (sequential and
Intel style bursts), provides support of different processor's burst
length requirements (Intel, Motorola, Sparc), and allows write posting of
cache data lines into a FIFO. Additionally, read/write or I/O operations
can be inhibited to allow conversion of data transactions, such as from
read to write or from write to read, so as to enhance bus transaction
speed.
The control signals transferred through the system bus, as an example, can
include address signals (AD), address strobe signals (AS*) to identify the
address phase, data strobe signals (DS*) for identifying the data phase,
address/data parity signals (ADP), and data burst last signals (BLST) for
premature termination of bus transactions. An asterisk (*) following a
signal name indicates that the signal is active low. The control signals
can further include interface mode signals (IMD) for identifying bus
interface mode, transaction type signals (TYPE) for specifying transaction
type, transaction size signals (SIZE) for specifying the number of bytes
to be transferred during a bus transaction, and memory inhibit signals
(INH) for aborting a DRAM read/write or I/O cycle already in progress.
Other control signals can include transform cycle signals (TRC) for
transforming an inhibited transaction cycle into another, snoop window
signals (SNW) for extending the snoop window beyond the timing interval
programmed in a timing register, bus acknowledge signals (BACK) for
supplying the transaction acknowledge to the bus master, bus error signals
(BERR) for indicating a bus error occurrence, and bus request signals (BR)
issued by the DRAC to hold ownership of the bus during reflective read
transactions. Still other control signals include bus busy signals (BB)
asserted by DRAC 8 for the duration of its bus ownership, bus grant
signals (BG), and interrupt out signals (INT) asserted whenever an error
condition occurs. Finally, the control signals can include clock signals
(CLK) for synchronizing all bus transactions, multiple frequency clock
signals (MCLK) for generating enhanced DRAM timing resolution, reset-in
signals (RSTIN) for resetting DRAM, and identification signals (ID).
The following describes some of these control signals in more detail.
IMD is used to specify the bus type or bus mode which is currently coupled
to the main memory system, such as MBus mode or a generic bus mode.
TYPE specifies the data transaction type during the address phase. The
interpretation of the TYPE bits is determined by IMD. For example, when
IMD indicates that the bus type is SPARC.RTM.type, the TYPE bits identify
all the data transaction types of the SPARC MBus, which include write,
read, coherent invalidate, coherent read, coherent write and invalidate,
and coherent read and invalidate. When IMD indicates that the bus type is
a generic type, the TYPE bits identify various data transaction types of
either MBus or generic applications, which include write, read,
read-in-default burst size, write, write-in-default burst size, sequential
burst order, non-sequential burst order (such as Intel processors), posted
write, posted write in default burst size, position of byte 0 on the bus.
Byte 0 appears as either the lowest byte on the bus or as the highest byte
on the bus.
SIZE bits are used to specify the transaction size and the particular byte
or bytes to be enabled. The available transaction sizes may include a
byte, a halfword (2 bytes), a word, double words, 16-byte burst, 32-byte
burst, 64-byte burst, or a 128-byte burst. The particular byte enable
information is added to the original MBus specification to provide byte
enable and misaligned data transfers compatible with processors such as
the i486 and 68040. Any combination of byte enables may be asserted
simultaneously. Interpretation of transaction size information is a
function of a particular one or more bytes' addresses in an address
signal, which allows, for example, selection of one or more data channels
in the memory controller, or to access one or more bytes in a bank in main
memory, or to access one or more banks in main memory.
PMD bits specify the parity computation algorithm and identify those
signals that participate in the parity computation. PMD bits are valid
during the entire system bus cycle. The parity modes include parity
computation disabled, address parity computed, data parity computed,
address and data parity computed, odd parity computed, or even parity
computed.
BACK bits supply a transaction acknowledge signal to the master system
processor (i.e. the bus master). In the MBus mode, the acknowledge signal
includes MBus definitions, such as uncorrectable error, valid data
transfer, and idle cycle. In the generic mode, the acknowledge signal may
include valid data transfer, error exception, and idle cycle.
AS* is asserted by the bus master to identify the address phase of the
transaction.
DS* is asserted by the bus master during the data phase of a transaction.
DS is internally pipelined in the DRAC and appears one clock cycle before
the clock cycle in which the data is transferred. Data is transferred and
BACK is asserted during every system bus cycle after the clock cycle in
which DS is asserted (provided that the DRAM controller can acknowledge a
transfer). The bus master may use DS to control (suspend) the slave's
response on a cycle-by-cycle basis.
BLST is used by the bus master to prematurely terminate bus transactions.
BLST is only recognized during clock cycles in which DS is also asserted.
Therefore BLST should be asserted one system bus cycle before the last
desired data transfer.
INH is asserted by a cache controller in multi-processing environments to
abort a DRAM read/write or register I/O cycle already in progress. When
INH is received before the data transfer begins, the operation is
terminated before any data is transferred. When INH is received after the
memory controller has begun to issue bus acknowledges, it is ignored. When
the memory is reflective, the read of DRAM is converted into a write. The
BACK signal, now originating from the snooping cache that owns the data,
is interpreted to provide a write strobe to the FIFO/EDC data path.
Inhibited writes may also be converted to reads for ownership.
TRC, when asserted, transforms an inhibited read cycle into a write cycle
(reflective) or an inhibited write cycle into a read cycle (read for
ownership).
SNW, when asserted, extends the snoop window beyond the interval that
results from the values programmed into the DRAM timing register. This
signal can be permanently de-asserted if it is not used.
BERR indicates that a bus parity error has occurred during the address or
data phase of a data transaction. The signal is asserted asynchronously
(i.e. one or more clocks late). This signal is valid one clock cycle after
the error occurs and lasts until cleared. The signal is cleared by writing
an appropriate bit to the Command Register.
BR is issued by the DRAC during reflective-read transactions. BR issued by
the main memory system is interpreted as the highest priority request for
ownership to the system's bus arbitration logic. Additional system bus
transactions are suspended until the ongoing write (resulting from the
reflective-read) to main memory is complete. The original MBus
specification has no explicit mechanism for a reflective main memory to
postpone the next bus transaction while the data being transferred between
two caches is simultaneously written to DRAM. Systems having more
elaborate protocols for acknowledging data transfers between a requesting
cache and a cache data owner can use BR to create a data strobe to prevent
the next transaction from overwriting the reflective data path inside the
DSRD.
BG is asserted by external arbitration logic in response to a BR to
indicate that the DRAC has been granted ownership of the bus.
BB is asserted by the DRAC for the duration of its bus ownership. The DRAC
will acquire the bus as it completes the main memory write transaction
during reflective read operations.
INT is an output which is asserted (if enabled) whenever an error condition
occurs. For example, system bus parity errors or memory errors can cause
INT to be asserted.
CLK synchronizes all bus data transactions. For example, the maximum clock
frequency is 50 MHz and all data transactions are strobed in at the rising
edge of the clock signal.
RSTIN is used to reset the DRAC. The signal must be asserted for at least
four clocks.
ID bits have two interpretations. When IMD indicates MBus mode, ID bits
interpretation is strictly MBus compatible. In MBus mode, the ID field
selects various configuration spaces within the MBus address space for
access to the port register and other I/O registers. When used in non-MBus
modes, the ID bits are used in conjunction with address signals to define
the nature of the bus transaction and select I/O | | |
