Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer
A hierarchical network hierarchically connects a plurality of networks whose nodes are mutually connected by connection paths as a p-array n-dimensional cube to configure a single network. A plurality of nodes are selected from lower layer p-array n-dimensional cubes, and the selected gate nodes are mutually connected as a p-array m-dimensional cube to configure a p-array m-dimensional network on the next layer. Similarly, gate nodes are selected from a plurality of next-layer p-array m-dimensional networks, and mutually connected as a p-array l-dimensional cube to configure a p-array l-dimensional network in a further upper layer, thereby configuring a single hierarchical network as a whole.
The invention is directed to techniques for managing a network of nodes by automatically configuring the arrangement of nodes in the network. A network manager in a node selects a group of nodes and compares network metrics for each node in the group, such as a bottleneck bandwidth measurement from each node to a root node of the network. The network manager selects a target node using the network metrics. Optionally, the network manager can select a new group of nodes using the target node, compare network metrics for the new group, and optionally select a new target node. If the node is a newly connecting node to the network, the network manager can repeat this process of selecting new groups until establishing a relationship with a target node that is not a root node (e.g., with performance that is the same, or about the same, as the root node), because the goal is not to overload the root node with too many relationships. If the node is a node with an established relationship to the network that is trying to reconnect to a new target node, the network manager can repeat the process of selecting new groups until establishing a relationship with a new target node that provides improved performance than the previous target node, but is, preferably, not the root node.
A hierarchical fat hypercube topology provides an infrastructure for implementing a multi-processor system at a plurality of levels. A first level is comprised of a plurality of n-dimensional hypercubes. This plurality of n-dimensional hypercubes is interconnected at a second level utilizing an m-dimensional metacube. The number of dimensions at each level and the number of bristles at each level can be customized depending on the requirements of the application. Additionally, routers can be implemented such that the system can be expanded to meet increasing system requirements. This is particularly useful at the second level of the hierarchical topology.
A network architecture for configuring nodes and links into a plurality of interconnected hypercubes is presented. Each hypercube is interconnected with at least one other hypercube and operates substantially independently of the other hypercubes in the network. Each hypercube provides high levels of traffic routing diversity and restorative capability with less link capacity. Unique node labeling reduces inter-nodal communication, and traffic routing and recovery is accomplished with less complex algorithms.
A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem , a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.
A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem, a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.