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Integrated circuit I/O using a high performance bus interface    
United States Patent5473575   
Link to this pagehttp://www.wikipatents.com/5473575.html
Inventor(s)Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
AbstractThe present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
   














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Drawing from US Patent 5473575
Integrated circuit I/O using a high performance bus interface - US Patent 5473575 Drawing
Integrated circuit I/O using a high performance bus interface
Inventor     Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Owner/Assignee     Rambus, Inc. (Mountain View, CA)
Patent assignment
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Publication Date     December 5, 1995
Application Number     07/847,532
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     March 5, 1992
US Classification     365/230.06 327/379 327/391 327/437 365/190 365/191 365/198
Int'l Classification     H03K 019/003
Examiner     Nguyen; Viet Q.
Assistant Examiner    
Attorney/Law Firm     Blakely, Sokoloff, Taylor & Zafman
Address
Parent Case     This is a divisional of application Ser. No. 07/510,898, filed Apr. 18, 1990 now abandoned.
Priority Data    
USPTO Field of Search     365/230.01 365/230.06 365/230.08 365/190 365/191 365/198 365/189.01 327/379 327/391 327/437
Patent Tags     integrated circuit i/o high performance bus interface
   
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