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CROSS-REFERENCE TO RELATED APPLICATION
Related subject matter is disclosed in U.S. patent application Ser. No. 08/024,124 now U.S. Pat. No. 5,291,062 by Leo M. Higgins, III entitled "Area Array Semiconductor Device Having a Lid with Functional Contacts," filed Mar. 1, 1993, in
U.S. Patent application Ser. No. 08/012,193 now U.S. Pat. No. 5,378,981 by Leo M. Higgins, III, entitled "Method for Testing a Semiconductor Device on a Universal Test Circuit Substrate," filed Feb. 2, 1993, and U.S. Patent application Ser. No.
07/876,315 now U.S. Pat. No. 5,273,938 by Paul T Lin et al., entitled "Resin Encapsulated Multichip Semiconductor Device and Method for Its Fabrication" filed Apr. 30, 1992, and assigned to the assignee hereof.
1. Field of the Invention
This invention relates to a semiconductor device in general, and more specifically to a plastic encapsulated semiconductor device having no die supporting surface and a method for making the same.
2. Background of the Invention
Plastic encapsulated semiconductor devices are susceptible to moisture ingress due to the permeable nature of plastic molding compounds. Devices containing moisture levels exceeding some critical amount run the risk of cracking or "popcorning"
during the rapid heating of the solder reflow operation associated with board mounting of devices. Typically, the cracks begin at an interface within the package. FIG. 1 illustrates, in a top view, a typical leadframe 10 of the prior art. The
leadframe 10 has a plurality of leads 12, a die supporting surface 14, and a plurality of tie bars 16 which physically connect the die supporting surface 14 to the rest of the leadframe 10. The die supporting surface 14 is also known as a flag, a die
pad, or a die paddle in the art. The leadframe 10 is the framework for assembling a semiconductor device 20, as illustrated in FIG. 2.
In FIG. 2 the semiconductor device 20 is illustrated in cross section so that the interfaces within the packaged device can be discussed. A semiconductor die 22 is mounted on die supporting surface 14 with a die attach adhesive 24. A plurality
of wire bonds 26 electrically connect the semiconductor die 22 to the plurality of leads 12. The tie bars which physically connect the die supporting surface to the leadframe are not seen in this cross section. As illustrated in FIG. 2, the die
supporting surface is downset below a plane as defined by the leads 12. This downsetting is typically done to aid in the symmetry of the plastic package body 28 in order to reduce stress within the packaged device. Plastic package body 28 is normally
formed from transfer molding a resin encapsulant or mold compound, a process well known in the art.
When a semiconductor device, such as the one illustrated in FIG. 2, cracks during a solder reflow operation normally associated with board mounting, the crack typically initiates at one of the interfaces 30, 32, or 34. Interface 30 is an
interface between the backside of die supporting surface 14 and the mold compound of package body 28. Adhesion between the leadframe metal and a mold compound is relatively weak as compared to adhesion between the silicon die 22 and the mold compound.
A second interface 32, an interface between the die attach adhesive 24 and the die supporting surface 14, has also been observed to be a crack initiation site. Interface 34, an interface between the backside of the semiconductor die 22 and the die
attach adhesive 24, is another potential crack initiation site within the packaged device. Typically, the weakest interface in the package will be the initiation site of a crack. The weakest interface delaminates, and the crack propagates through the
plastic package body to the outer surface of the package body. On occasion, where the die attach adhesive 24 has a lot of voids (not illustrated), the package crack will initiate within the die attach adhesive itself at one of the voids. Mechanical
failure of a semiconductor device often times lead to subsequent electrical failure of the same device due to thermal and mechanical stresses induced on the device during its operation.
FIG. 3 illustrates another semiconductor device 40 known in the prior art to have "popcorning" or cracking problems. In this type of device, semiconductor die 22 is mounted onto a substrate 42 that has a die supporting surface 44. Substrate 42
is typically a printed circuit board (PCB) material that has metallizations 46 and 48 on the top and bottom surfaces of the substrate. Metallizations 46 and 48 are typically connected to each other with plated vias (not illustrated). The interfaces 50
and 52 are the two interfaces that have been observed to be crack initiation and/or delamination sites. Again, it has been observed on occasion that cracking initiates within the die attach adhesive 24.
Another factor to be considered when utilizing a plastic encapsulated semiconductor device is its thickness. It is often desirable to minimize the thickness of a packaged semiconductor device since they are widely used in various types of
electronic products, portable consumer products, telephones, pagers, automobiles, integrated circuit cards, and the like, in order to make the final products as thin as possible.
Thus, it is desirable to manufacture a plastic encapsulated semiconductor device which is resistant to package cracking during a solder reflow operation, in addition to obtaining a thin package profile in the encapsulated device.
SUMMARY OF THE INVENTION
This invention provides a semiconductor device having no die supporting substrate and a method for making the same. In one embodiment, a semiconductor die having an active surface and a periphery is provided. The semiconductor die is placed on
a supporting workholder, where the die is rigidly held in place. A plurality of conductors extending toward the periphery of the semiconductor die is provided. The active surface of the semiconductor die is electrically connected to the plurality of
conductors. A package body is formed from a resin encapsulant to cover at least the active surface of the semiconductor die and the electrical connections. A plurality of external conductors electrically connected to the semiconductor die is provided.
The invention also provides a device produced by the same method. In the device, the semiconductor die is substantially centered within a die cavity, wherein the die cavity has no die supporting surface.
These and other features, and advantages,
will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other
embodiments of the present invention which are not specifically illustrated.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates, in a top view, a conventional leadframe of the prior art.
FIG. 2 illustrates, in cross-section, a plastic encapsulated semiconductor device of the prior art, having a conventional leadframe.
FIG. 3 illustrates, in cross-section, an overmolded semiconductor device of the prior art, having a conventional PCB substrate.
FIGS. 4-6 illustrate, in cross-section, process steps for manufacturing a wire bonded semiconductor device having no die supporting surface in accordance with a first embodiment of the invention.
FIG. 7 illustrates, in cross-section, an alternative molding method in accordance with a second embodiment of the invention.
FIG. 8 illustrates, in cross-section, a wire bonded semiconductor device in the second embodiment of the invention.
FIG. 9 illustrates, in cross-section, yet another alternative molding method in accordance with a third embodiment of the invention.
FIG. 10 illustrates, in cross-section, a wire bonded semiconductor device in the third embodiment of the invention.
FIG. 11 illustrates, in cross-section, a wire bonding step for a wire bonded semiconductor device in accordance with a fourth embodiment of the invention.
FIGS. 12-13 illustrate, in a top and bottom view, respectively, the PCB substrate of FIG. 11 showing a plated die cavity.
FIG. 14 illustrates, in cross-section, a molding step in accordance with the fourth embodiment of the invention.
FIG. 15 illustrates, in cross-section, a wire bonded semiconductor device in the fourth embodiment of the invention.
FIGS. 16-17 illustrate, in cross-section, process steps for manufacturing a wire bonded semiconductor device in accordance with a fifth embodiment of the invention.
FIGS. 18-20 and 22 illustrate, in cross-section, process steps for manufacturing a wire bonded semiconductor device in accordance with a sixth embodiment of the invention.
FIG. 21 illustrates, in a bottom view, annular tings of solder resist tape on the inactive surface of a semiconductor die in accordance with the sixth embodiment of the invention.
FIGS. 23-25 illustrate, in cross-section, process steps for manufacturing a wire bonded semiconductor device in accordance with a seventh embodiment of the invention.
FIG. 26 illustrates, in cross-section, another wire bonded semiconductor device having a recessed substrate in an eight embodiment of the invention.
Many figures which illustrate various embodiments of the present invention incorporate many of the same or similar elements. Therefore, like reference numerals designate identical or corresponding parts throughout the figures.
DETAILED
DESCRIPTION OF A PREFERRED EMBODIMENT
FIGS. 4-6 illustrate, in cross-section, process steps for manufacturing a wire bonded semiconductor device 58 (illustrated in FIG. 6) having no die supporting surface in accordance with a first embodiment of the invention. As illustrated in FIG.
4, semiconductor die 22 is placed directly on a supporting workholder 60. The plurality of leads or conductors 12 extend toward the periphery of the semiconductor die 22. Leads 12 effectively make a die cavity, wherein the semiconductor die 22 is
disposed in a substantially centered position. The leads 12 comprise a portion of a leadframe, which is not fully illustrated because the outer portion of the leadframe is not relevant to the present invention. What is important to note is that the
leadframe does not have a flag or die supporting surface, hence, no tie bars, such as shown in FIG. 1 of the prior art. Therefore, the semiconductor die is placed directly on the supporting workholder 60 for the wire bonding process. The workholder 60
has a vacuum line 62 that is activated to rigidly hold the semiconductor die 22 in place. Although FIG. 1 only illustrates a single vacuum line, any number of vacuum lines or holes can be used in the workholder to rigidly hold the die in place. The
workholder is typically heated to a temperature in a range of 175.degree. C. to 250.degree. C. for wire bonding, preferably 200.degree. C. to 230.degree. C. The active surface of the semiconductor die 22 is wire bonded to the plurality of conductors
12. Gold or gold alloy wires are typically used for the wire bonds, although other conductive metals and metal alloys may also be utilized. Methods of wire bonding are well known in the art. It is also possible to use low loop wire bonding in place of
conventional wire bonding to make the electrical connections. Usage of low loop wire bonding will allow a thinner package body to be molded in a subsequent process step. However, other methods of electrically connecting the die to the leads or
conductors are also possible, such as tape automated bonding.
FIG. 5 illustrates, in cross-section, a next step in the process of making the wire bonded semiconductor device 58 of FIG. 6. As illustrated in FIG. 5, the semiconductor die 22 has been removed from the supporting workholder 60, illustrated in
FIG. 4, so that the die 22 is supported solely by the plurality of wire bonds 26. The stiffness of the wire bonds 26 is sufficient to hold the semiconductor die 22 in place during handling, transport, and most importantly, the molding process. The die
22 and the plurality of conductors 12 making up the leadframe are placed inside a mold cavity 64 formed by two mold platens 66 and 68. A resin encapsulant is injected into the mold cavity 64, typically under elevated temperature and pressure, to form a
package body around the die 22, the wire bonds 26, and a portion of the plurality of conductors 12. Conventional transfer molding equipment using existing mold designs can be used for this molding step. No modification of the molding equipment is
necessary. Typical resin encapsulants that can be used for the package body include epoxy novolac resins and silicone resins. However, other materials may also be suitable for the package body such as phenolics, other thermosets, thermoplastics, and
glob top materials. As illustrated in FIG. 5, the sidewalls of the mold cavity 64 are angled. Although not a requirement in practicing the invention, having tapered sidewalls aid in the release of a molded package body from the mold.
FIG. 6 illustrates, in cross-section, the completed wire bonded semiconductor device 58 in a first embodiment of the present invention. After the step of molding in FIG. 5, the plastic encapsulated device is removed from the mold. The
semiconductor die 22, the plurality of wire bonds 26, and a portion of the plurality of leads or conductors 12 are encapsulated by the package body 70. Package body 70 corresponds substantially in size and shape to that of the mold cavity 64,
illustrated in FIG. 5. The portion of the plurality of leads 12 which is external to the package body 70 is formed into a desired external lead configuration. In this illustration, the device 58 has a gull-wing lead configuration, but other external
lead configurations may also be possible, such as J-lead or an in-line configuration. It should also be understood that other assembly process steps may follow after the step of molding prior to the step of lead forming. Those assembly process steps
may include, but are not limited to, post mold curing, deflashing/dejunking, plating, marking, dam bar removing, and singulating. However, these steps are well known in the art.
The wire bonded plastic encapsulated semiconductor device 58 of FIG. 6 offers several advantages over the prior art. Since there is no die supporting surface, the three critical interfaces where package cracking normally initiates have been
eliminated in this first embodiment of the invention. In addition to a more crack resistant package, substantial cost savings can be realized in materials, equipment, and cycle time. The die attach process has been eliminated, thus eliminating the need
for a die attach adhesive, refrigerators for storing the die attach adhesive, die attach equipment, ovens for curing the die attach adhesive, and floor space to accommodate all the equipment associated with the die attach process. Moreover, the
resulting package profile of the wire bonded device 58 is thinner than that of a conventional plastic encapsulated device because the thickness of the leadframe in the die cavity and the thickness of the die attach adhesive have been eliminated from the
packaged device. In addition to a thinner profile, the wire bonded device of the present invention may also provide shorter wire bond lengths because the tie bars have been eliminated from the leadframe. Therefore, the space made available by the
elimination of the tie bars can be used to route the leads or conductors closer to the periphery of the semiconductor die, thus enabling the shorter wire bond lengths.
FIG. 7 illustrates, in cross-section, an alternative method of molding a wire bonded semiconductor device 76 (illustrated in FIG. 8). In FIG. 7, the two mold platens 66 and 78 form the cavity 64' wherein the lower mold platen 78 has a support
pin 80 and a vacuum line 82 which are used to support and stabilize the lower inactive surface of the semiconductor die 22 during molding. It should be understood that any number of support pins and vacuum lines may be used to support the die during the
step of molding. It is envisioned that the semiconductor die may require the additional support provided by the support pin 80 if the semiconductor die were to exceed some critical die size, where the die may tilt during molding if not further
supported. The support pin 80 provides stability in the z-direction, while the vacuum 82 provides stability in the x-y plane while additionally preventing a theta rotation of the die.
FIG. 8 illustrates the wire bonded semiconductor device 76 in a second embodiment of the invention. As illustrated in FIG. 8, the resultant package body 84 has a hole 86 in the lower half of the package body which exposes a portion of the
inactive surface of the semiconductor die. This hole 86 can serve as a venting hole for the device. Alternatively, if the hole is made large enough, a drop-in heat sink (not illustrated) could be attached to the exposed portion of the inactive surface
of the semiconductor die for added thermal dissipation. If a heat sink were to added, the device should be mountable in an inverted manner, thus, the external portion of the leads would be formed in the opposite direction. Additionally, if a number of
support pins were used during molding, the package body would have the corresponding number of holes in the lower half of the package body.
Although not specifically illustrated in FIG. 7, it is also possible to support the inactive surface of the semiconductor die 22 with just a support pin, without the additional vacuum line. The support pin could be either retractable or
nonretractable during the molding process. If the support pin is retracted during the molding process while the resin encapsulant is filling the mold cavity, then the resin encapsulant will flow into the area previously occupied by the support pin to
fully encapsulate the semiconductor die. The resulting package body will look the same as that previously illustrated in FIG. 6. However, if the support pin is not retracted during the molding process, the resin encapsulant will flow around the support
pin while filling the mold cavity. The pin would then be retracted after the package body has been formed. The resulting package body will have a vent hole the size of the support pin in the bottom of the package body. Vent holes have been employed in
the past to provide a path for moisture to escape from the package body without causing the package body to crack.
FIG. 9 illustrates, in cross-section, yet another alternative method of molding a semiconductor device 90 (illustrated in FIG. 10) in accordance with a third embodiment of the invention. In this method, the inactive surface of the wire bonded
semiconductor die 22 is placed directly on a lower mold platen 92 to be supported by the surface of the mold platen. The mold platen 92 includes a vacuum line 94. When vacuum line 94 is activated, the semiconductor die 22 is held rigidly in place
against the lower mold platen surface for the molding process. The activated vacuum line 94 also aids in the prevention of flash which may occur as a result of transferring the resin encapsulant into the mold cavity 64" under high pressure.
FIG. 10 illustrates the wire bonded semiconductor device 90 produced by the method of FIG. 9. As illustrated, the package body 96 of device 90 exposes the inactive surface of the semiconductor die 22. The leads 12 have been formed externally
into a J-lead configuration, where the die 22 has been inverted. Thus, after the device 90 is mounted to a board (not illustrated), the heat generated by the device 90 can be efficiently dissipated into the environment instead of being distributed
through the board since silicon is a good conductor. Furthermore, a heat sink (not illustrated) can be attached to the exposed inactive surface of the die 22 for enhanced thermal dissipation. In addition to the aforementioned advantages of device 58,
another advantage to device 90 is that the total thickness of the device has been decreased because the package body 96 is not a total encapsulation of the semiconductor die 22. It should be obvious that although device 90 is illustrated to be a
J-leaded type of device, other external leads configurations are possible such as gull-wing and dual-in-line.
FIGS. 11 and 14 illustrate, in cross-section, process steps for manufacturing a wire bonded semiconductor device having no die supporting surface in accordance with a fourth embodiment of the invention. As illustrated in FIG. 11, a substrate 100
having a die cavity 102 is provided. Substrate 100 is preferably, but not limited to, a PCB material such as bismaleimide triazine resin (BT resin). Other epoxy glass-reinforced cloth and other PCB materials are also suitable. In this embodiment, the
area typically used for a die supporting surface in the substrate is removed to provide the die cavity 102. Semiconductor die 22 is disposed inside die cavity 102 and is placed directly on the supporting workholder 60 for the wire bonding process. The
die 22 is substantially centered inside die cavity 102. The vacuum 62 rigidly holds the die 22 in place. FIG. 11 illustrates a plurality of low loop wire bonds 26' accomplished with a low loop wire bonder which is known in the art. However,
conventional wire bonding may also be used in this embodiment. An advantage to having the die cavity 102 instead of a die supporting surface (such as illustrated in FIG. 3 of the prior art) is that a lower package profile can be obtained because two
aforementioned interfaces found in the prior art have been eliminated.
Also illustrated in FIG. 11 are pluralities of conductive traces 104 and 106 and on the top and bottom surfaces of the PCB substrate 100, respectively. The two pluralities of conductive traces are electrically connected to each other by a
plurality of plated vias (not illustrated in this view). As can be seen in FIG. 11, the die cavity has plated sidewalls 108, although the plating is not a requirement in practicing the present invention. However, it is advantageous to have plated
sidewalls in the die cavity. The plated sidewalls 108 can be used as a power supply bus. All common power or ground traces can be tied to the plated sidewalls. Moreover, the plating also provides a smooth surface for the sidewalls, whereas an unplated
sidewall may have a rough surface which could trap contaminants during the assembly process. Such contaminants would be encapsulated into the device during molding and could be detrimental to the device during its operation by causing corrosion.
FIGS. 12 and 13 further illustrate, in a top and bottom view, respectively, the PCB substrate 100 of FIG. 11. As illustrated in FIG. 12, the plated sidewalls 108 of die cavity 102 are connected to representative power supply traces 110 of the
plurality of conductive traces 104. It should be understood that the conductive traces depicted are only intended to be illustrative and that the actual pattern and location of specific traces depend on the semiconductor die to be packaged. Also
illustrated in FIG. 12 is a plurality of vias 112, which are normally plated to electrically connect the traces 104 on the top surface of the substrate 100 to the conductive traces 106 on the bottom surface of the substrate. FIG. 13 illustrates a bottom
view of the substrate 100. In addition to the plurality of vias 112, a plurality of solder pads 114 is also illustrated. Solder balls (not illustrated) are typically attached to the solder pads 114 to form external electrical contacts for the device.
FIG. 13 also illustrates conductive traces 110' which electrically connect the plated sidewalls 108 of the die cavity 102 to power supply solder pads. It should be understood that the traces 110' are merely illustrative because the actual location and
routing of these traces and corresponding solder pads depend on the device.
Illustrated in FIG. 14 is a molding step for the wire bonded semiconductor device in accordance with the fourth embodiment of the invention. After the semiconductor die 22 is wire bonded to appropriate conductive traces 104 on the PCB substrate
100, the substrate assembly is placed inside a mold having a top platen 66' and a bottom platen 116. The top and bottom mold platens define a mold cavity 118. A support pin 80 is used to support the inactive surface of the semiconductor die 22 during
the step of molding. The pin 80 provides stability to the die 22 in the z-direction, which may be required while the resin encapsulant is filling the mold cavity if the die size is large. A small semiconductor die may not require the support pin
because rigidity of the wire bonds 26' would be enough to hold the die in place during the filling of the mold cavity. Normally, the larger the die, the more likely it will tilt during molding if not supported. A very large die may require a plurality
of support pins to provide stability to the die during the molding process.
FIG. 15 illustrates a molded wire bonded device 120 in the fourth embodiment of the invention. The device 120 has a package body 122 which substantially conforms to the size and shape of the mold cavity 118 of FIG. 14. A vent hole 124 for the
release of moisture is present in the bottom of the package body 122 due to the support pin used during the molding process. A plurality of solder balls 126 provide external electrical connections for the device. The solder balls 126 are attached to
the solder pads on the bottom surface of the substrate 100. The solder pads are illustrated in the bottom view of the substrate in FIG. 13. Device 120 shares the same low profile and crack resistant advantages of device 58 (FIG. 6) and device 76 (FIG.
8) because the interface between the die attach adhesive and the die supporting surface and the interface between the die supporting surface and the resin encapsulant have been eliminated.
Illustrated in FIGS. 16-17 are process steps for manufacturing a wire bonded semiconductor device having no die supporting surface in accordance with a fifth embodiment of the invention. In FIG. 16, a semiconductor die 22 is wire bonded to
conductive traces 106' on a surface of a substrate 130. Substrate 130 has conductive traces on one surface of the substrate. The conductive traces 106' terminate in a plurality of solder pads (not illustrated in this figure) in the same manner as
previously illustrated in FIG. 13. Substrate 130 does not require conductive vias because there is no metallization on the opposing surface of the substrate to be connected to traces 106'. Accordingly, substrate 130 can be thinner than substrates
requiring double sided metallization by the thickness of the metallization. However, if the routing pattern of the conductive traces 106' becomes complex or too dense, the other surface of the substrate may be used to support a second pattern of
conductive traces which would be electrically connected to traces 106' with plated vias, much in the same manner as substrate 100 of FIG. 11. However, the solder pads of substrate 130 must be on the same side of the substrate as the conductive traces
106' which are wire bonded to the die. The semiconductor die 22 is wire bonded to the substrate 130 in substantially the same manner as that previously illustrated in FIG. 11. After the step of wire bonding, the substrate with the wire bonded die is
placed inside a mold cavity 132 which is formed by two mold platens 66' and 134. The lower platen 134 has a pedestal 136 which directly contacts and supports the inactive surface of the semiconductor die 22. In conjunction with the pedestal is an
activated vacuum line 94' which rigidly holds the die 22 to the pedestal 136 so that flashing does not occur during the molding process. A resin encapsulant is typically transferred into the mold cavity 132 under elevated temperature and pressure, with
the pressure being in a range of 1000 psi to 2000 psi. With such a high pressure, flashing of the resin encapsulant can occur unless the clamping pressure on the mold platens is sufficient to prevent flash, or unless a vacuum is used to prevent flash
from forming on the inactive surface of the die 22.
FIG. 17 illustrates a wire bonded semiconductor device 140 in the fifth embodiment of the invention. After the step of molding, the substrate 130 is inverted so that the conductive traces 106' are on the bottom. A plurality of solder balls 126
are then attached to the substrate. The solder balls are actually physically bonded to solder pads which are not shown in this illustration. However, the solder pads are substantially the same as that previously illustrated in FIG. 13. Conductive
traces 106' terminate with the solder pads so that the plurality of solder balls 126 are electrically connected to the traces, hence, the semiconductor die. The package body 122' has an opening 142 which exposes a large portion of the inactive surface
of the semiconductor die 22. A heat sink 144 can be optionally attached to this exposed portion of the inactive surface to increase the thermal dissipation capacity of the device during operation.
FIGS. 18-22 illustrate process steps for manufacturing a wire bonded semiconductor device in accordance with a sixth embodiment of the invention, where FIG. 22 illustrates the finished device 146. FIG. 18 illustrates, in cross-section, a wire
bonding step for the device. A patterned removable tape 148 is affixed to the bottom surface of the substrate 100 including the die cavity 102. The tape can be applied by the manufacturer of the substrate in the normal fabrication steps of the
substrate. The tape 148 provides a temporary die supporting surface whereupon the semiconductor die 22 is placed. The tape rigidly holds the die in place on top of the supporting workholder 60". The tape must be a solder resist material, such as a
polyimide tape, a teflon tape, or a UV releasable tape. A UV releasable tape completely crosslinks upon exposure to UV light or radiation, thereby losing its adhesive quality thus enabling easy removal of the tape. Other high temperature tapes may also
be used in practicing the invention. Tape 148 is perforated | | |
