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CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to patent application Ser. No. entitled, "Computer with Graphic Interface," application Ser. No. 07/827,076, filed on the same day as the present application, Jan. 28, 1992, and application Ser. No.
08/240,098, a continuation of application Ser. No. 07/827,076, filed May 9, 1994, each owned now, and at the time of the invention, by the same assignee.
FIELD OF THE INVENTION
The present invention relates to the field of infrared communications; and more particularly, to digital communication systems based on transmission and reception of infrared signals.
BACKGROUND OF THE INVENTION
Widespread use of frequencies in the infrared band for communication by telemetry has been made. Using an infrared signal in a business or household environment, however, has been hampered by the large amount of background infrared radiation
present. Thus, the uses of infrared communications has been limited to remote control devices for home entertainment systems and the like which are required to communicate a relatively small set of codes with significant redundancy, and do not require
the ability to communicate large amounts of digital data at a high rate of speed.
The problem of using infrared communication systems for high speed digital communications is further complicated by the desire to transmit data between battery operated hand-held devices, and a host computer system. These battery operated
devices must be able to communicate with relatively low power consumption, therefore, making long high power infrared communication signals impractical.
Therefore, it is desirous to have an infrared communication system, which utilizes relatively low power and communicates data at a high rate of speed, sufficient for transferring files of digital information between the hand-held computer and a
host system.
SUMMARY OF THE INVENTION
In the present invention, the transmitter generates an infrared signal that represents a bit stream of binary data. Each binary signal generated by the transmitter has a set of infrared pulses representing one state of the binary signal and a
second set of infrared pulses representing a second state of the binary signal. The pulses associated with each state of the binary signal have specific characteristics which enable the receiver to distinguish the transmitted signal from any background
radiation. The specific characteristics of each set of pulses, therefore, create in essence a signature which can be recognized by the receiver as implemented within an ASIC.
In one aspect of an invention, a sequence of bits of digital information are generated by a transmitter in which the first binary state of the bit is represented by a sequence of a first signature set of infrared pulses, and the second binary
state of the bit is represented by a second signature set of infrared pulses. The signature sets of pulses are detected by a receiver in which an electrical signal is generated by the receiver in response to the detected pulses. The electrical signal
is then filtered to detect the signature sets of pulses generated by the transmitter. The signature sets of pulses are then decoded to reconstitute the binary digital signal.
In another aspect, the signature sets of pulses are communicated according to a specific communications protocol for high speed communication of digital data, at greater than 30,000 bits per second.
Other aspects and advantages of the present invention can be seen upon review of the drawings, the detailed description and the claims which follow.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 is a perspective view of a portable computer using the present invention.
FIG. 2 is a functional block diagram of the computer of FIG. 1 according to the present invention.
FIG. 3 is a diagram of the infrared communications receiver of the present invention
FIG. 4 is a block diagram of the power management and biasing and main sub-circuits of the communications receiver.
FIG. 5 is a schematic of the power management and biasing circuits of the receiver.
FIG. 6 is a schematic of the log pre-amp, high-pass filter, balanced compression amplifier, pseudo-differential low-pass filter amplifier and VCVS high-pass filter amplifier circuits of the receiver.
FIG. 7 is a schematic of the active band-pass filter, two quadrant voltage-to-logarithmic current convertor, peak detector, comparator, analog output stage, and digital output stage circuits of the receiver.
FIG. 8 is a timechart showing pulse sets representing bit 1.
FIG. 9 is a timechart showing the transmission of 31,250 bits in one second and sets of pulses representing binary 1 and 0.
FIG. 10 is a block representation of a data packet.
FIG. 11 is a stylized diagram showing the timing relationships between the peaks of signal PKT on the upper voltage axis and the "crossing" of signals PKO and PKC on the lower voltage axis.
DETAILED DESCRIPTION
A detailed description of a preferred embodiment of the present invention is given with reference to the figures. FIG. 1 shows a perspective view of the computer system. FIG. 2 is a functional block diagram of the computer.
The computer according to the preferred embodiment of the present invention is an extendable, portable, text and graphics processing system, which is small enough to fit into a pocket, such as the standard size breast pocket of a man's suit coat. Inside the casing, data storage, data processing, display, user interface, and communications systems are packaged along with a power supply and storage system.
FIG. 1 shows a perspective view of the casing tablet 10. The tablet 10 can easily fit into a breast pocket of a coat.
The external features of the tablet 10 include a top surface 11, which is dominated by an opening exposing a liquid crystal display 12 with touch sensitive overlay 18. Also, the single mechanical user control switch, called the attention button
15, is provided on the top surface.
The bottom surface (not shown) of the casing incorporates a battery cover for a back-up lithium battery storage, to provide for real time clock power and long term memory retention. Also, on the bottom surface of the casing, an acoustic port is
provided through which sound produced by the speaker may emanate to a user.
A infrared lens 19 on a first end 13 of the casing 10 provides an optical port 14 whereby the infrared emitter/detector pair can communicate with compatible peripheral devices.
The placement of the optical port 14 is on the end opposite the battery pack 17. The optical port 14 will be covered by a plastic material, attached to the casing 10, which is optically transparent in the frequency range of the infrared system
and optically opaque in the visible light spectrum.
At the second end 16, a battery pack is connected to the tablet. The battery pack shown in FIG. 1 is adapted to hold four AAA batteries. Alternative battery pack designs, such as for AA batteries, could be adapted to fit with the tablet 10.
FIG. 2 is a functional block diagram of the computer system which is mounted within the casing 10 of FIG. 1. The system includes battery pack 50, a touch sensitive transparent overlay 51, an LCD display screen 52, the infrared transmitter 53,
and an infrared receiver 54. Also, an attention button 55 is included in the circuit.
The processing capability of the computer is provided by microcontroller 56, memory controller 57, LCD controller 58, communication controller 59, and a variety of other elements as shown in the circuit.
The microcontroller, such as the NATIONAL SEMICONDUCTOR HPC46003, is a central processing unit. The HPC has a UART on chip, which is used to support the communications system.
The microcontroller 56 is coupled to the memory control circuit 57 across bus 60. The memory control circuit 57 provides an interface across memory bus 80 to the storage unit, designated generally by the reference number 61. The storage unit 61
includes static RAM 62 used for a display RAM, a bank of static RAM 63, a bank of ROM 64, and a connector 65 for an external memory cartridge.
The memory controller 57 also manages the input from the touch screen 51 across input bus 81, in combination with the LCD controller 58. The LCD controller 58 manages display refresh and display buffer 62 management.
The batteries 50 of the removable battery pack are coupled to a voltage regulator 66, such as the Intercell ICL 7665S or equivalent, which generates a regulated output voltage for powering the circuits. The primary power is supplied by power
packs 50 which provide nominal unregulated 6 voltage DC. A secondary battery 67, or "retention" power source, provides long term power for retention of memory in volatile storage elements on the system. This is supplied, for instance, by a lithium
battery, such as EVERREADY CR2032 or the equivalent. The back-up battery 67, is coupled through diodes 68 and 69 to the output of the voltage regulator 66 and to the RAM bank 63 and clock/calendar 90 to provide back-up voltage.
A clock/calendar chip 90 is included, such as the INTERCELL ICM 7170, NSC DP8573, or equivalent. This chip includes a comparer alarm, whereby the CPU designated time month/day, hour/minute is used to generate a clock interrupt, or power on the
CPU. When the system is on, the clock/calendar chip 90 is powered by the primary power source. When the system is off, this chip draws power from the back-up lithium battery.
Overlay row and column decoders 70, 71 are connected between the memory controller 57 and the transparent overlay 51 across bus 81. The 4.5V regulated output of the voltage regulator 66 is coupled to a DC to DC converter 82 to supply negative
bias voltage to the LCD display module 52.
The communication control circuit 59 is connected to the memory controller 57 on serial lines 83 and 84, and through the memory controller to UART 85 coupled with the microcontroller 56.
A crystal oscillator 73 is coupled to the memory controller 57 for providing a clock signal.
Infrared emitter 53 and detector 54 are provided for communications with external equipment. The transmitter and receiver have peak power at or near a wavelength of 940 nanometers.
A speaker 72 is coupled to the microcontroller 56.
The system speaker 72 is capable of generating audible tones under control of the CPU.
The system includes a socket 65, interfaced via the memory controller chip, whereby an external ROM or RAM, or hybrid ROM+RAM card may be electronically inserted. This system is compatible with a card such as the ITT CANNON STAR CARD.
These ROM/RAM cards could be available as masked ROM, one time programmable ROM, E2PROM, S/RAM, or other memory devices.
The touch screen 51 overlays the liquid crystal display. It is a transparent resistive overlay controlled by the memory control block 57. It provides 9 bit by 9 bit resolution across the LCD screen. Touching the pad presents a finite
resistance across the X and Y directions of the pad. Electrodes are provided for the purpose of interconnections to measure these resistances. When no pressure is applied, a very large or infinite resistance is provided to the electrodes.
The attention button 55 is implemented with an electronically separate section of the touchscreen and acts as single pole, single throw, normally open push button. The button 55 is mounted directly onto the top of the tablet casing. Actuation
of the button is accomplished by using a custom plastic piece which fits into the casing. The switch activates the primary power system when the system is off. When the system is on, the switch provides an interrupt to the CPU via the memory controller
57.
The computer system, when mounted within the casing 10 of FIG. 1, is a monolithic electronic assembly powered by the power packs. The power packs can be provided in any number of configurations, based on variations of battery size. For
instance, battery packs could be configured for four AAA alkaline batteries, four AA alkaline batteries, five AA nickel-cadmium batteries, or for attachments to any number of external power supplies.
The user interface consists of the liquid crystal display 52 under the touch screen, the attention button 55, and an input control program as described below. The casing 10 and display 52 is designed to be held and operated in either a portrait
or landscape orientation by either a right or left handed person.
The user requests an "interactive power-on" via the attention button 55. Pressing this button will signal a power-up of the processing system.
A power-on can also be initiated by reaching a specific date/time within the clock/calendar chip 90.
When powering on automatically, the apparatus will inform the user via an alarm tone through the speaker and an event specific screen illustrating the reason for the power-on.
The primary user interface on the apparatus is provided by "soft function-keys" as implemented using the bit mapped liquid crystal display 52 and an associated transparent touch sensitive overlay 51.
The processing system is powered down under software control according to a power management scheme.
Low battery capacity is detected by the system for both the primary and long term retention cells, and reported to the user under software control. As a battery saving feature, the unit will automatically turn itself to a low power data
retention mode after the preset user adjusted interval, if no user command selection is made.
Peripheral communication is provided by modulated infrared communication media exchanging information with peripheral devices, such as personal computers, modems, keyboards, and the like.
The circuit provides a minimum of 256 kilobytes of 100 nanosecond OTP ROM. This ROM contains the code necessary to perform the basic functions and hardware diagnostics, and store necessary character fonts, hard coded displays, icons, symbols, et
cetera. The ROM is accessed in 32 blocks of 8 kilobytes each, under control of the memory controller chip.
A minimum of 128 kilobytes of non-volatile read/write memory (SRAM) is provided. This memory is arranged in 16 banks of 8 kilobytes using four 32 kilobyte static RAMs.
While the system is active, the SRAMs are powered using the primary power source. While the system is quiescent, the SRAM is placed in low power mode and powered from the back-up power cell. Replacement of the back-up power cell can be
accomplished only while the unit is connecting to its primary power source.
The system further includes 32 kilobytes of display RAM. This RAM may be a volatile memory, if required. This display memory is utilized by the system as image buffers.
The liquid crystal display provides a 400 by 192 pixel bit map display screen overlaid with a transparent touch sensitive pad.
The CPU processes information in either a portrait or landscape orientation as selected by application code, and appropriate user information. As such, the contrast ratio for the LCD must be reasonably constant as the assembly is rotated through
360.degree..
The outside dimensions of the LCD are about 6.259 inches by 3.252 inches by 0.315 inches. The viewing area is at least 4.724 inches by 2.267 inches. Center to center dot spacing of 0.3 millimeters is required for the 400 by 192 dot resolution.
The panel provides a reflective type LCD with a grey background color.
In the preferred system, the memory controller chip is an application specific integrated circuit. The chip provides bus control and memory segmentation, interrupt control and identification, power management, and direct memory access functions.
Because the selected CPU provides linear addressing space of only 64 kilobytes, the processor segments memory into banks.
A 16 bit address A15-A0 from the microcontroller is translated into a 21 bit memory address MA20-MA0 by means of the bank registers. The three high order bits A15-A13 of the microcontroller address are used to address the bank registers. Each
bank register stores the eight high order bits of a given memory address MA20-MA13.
Interrupts are generated in the system from the voltage monitor, the attention button, and the clock/calendar chip 90. Upon receipt of an interrupt, the memory controller circuit notifies the CPU of the event, performing a CPU "power-on", if
required. The memory controller chip provides a method whereby the processor can uniquely identify the source of external interrupts.
The memory controller chip also provides DMA services in a variety of contexts. Transfer from the image RAM to the LCD drivers, as well as from ROM and SRAM into the blitter, the memory controller provides a two-channel DMA circuit. The DMA is
designed to minimize bus contention between the CPU, the blitter, and the LCD controller. This DMA utilizes real addresses, so that it is not constrained by the limited address space of the CPU. In the case of bus conflicts, the LCD controller channel
prevails. Bus conflicts between the blitter and the CPU are resolved in favor of the blitter access.
The LCD control chip integrates an LCD controller and the hardware blitter operations.
The LCD controller 58 implements raster scan refresh of the LCD by synchronously accessing image data within the image RAM, serializing it, and shifting it out to the LCD drivers. The CPU provides a base address for a particular display,
particularly within the display RAM.
Also, this chip provides a blanking signal for disabling the LCD.
The hardwater blitter is a registered barrel-shifter combined with a logical function selector. The hardware blitter is capable of read modify write operations between the image RAM and information contained in either the static RAM or the ROM
of the processor. The blitter is capable of performing simple masking (and), merging (or), complimenting (not), filling with ones or clearing with zeros within the image RAM in conjunction with a barrel shifter.
The memory control chip also implements the circuitry necessary to allow the CPU to periodically scan the touch screen.
Registration of the dots of the liquid crystal display and dots on the touch screen is performed in software during user configuration session. The touch screen controller provides a mode whereby the sense of the user touch will awaken the CPU
at completion of an X/Y read cycle. The CPU may initiate a touch screen scan based on an internal timer. 9 bits resolution in the long X axis of the touch sensitive screen and 9 bits resolution in the short Y axis is provided.
The hand-held computer, according to the present invention, may be configured for use by either a left-handed or a right-handed user. Because of the location of the transmitter/receiver and because the center of gravity of the computer is such
that its balance is better if held near the end having the battery pack, a right-handed user will tend to hold the computer so that the screen has a first orientation and a left-handed user will hold the computer so that the screen is turned over. The
touch screen control and the LCD display refresh circuitry are adapted to accommodate either a left-handed or a right-handed user.
In the preferred embodiment, the transmitter of a hand-held computer generates an infrared signal to be detected by a receiver in a personal computer interface or other peripheral device. As shown in FIGS. 8-9, the signal generated is a binary
data stream 300, such that each piece of binary data consists of a signature set of two 5 microsecond pulses 302 spaced by 5 microseconds for binary zero 400, and a signature set of no pulses for a binary one 401. Each of these signature sets falls
within a 32 microsecond window 301, so that the pulse pairs of successive binary zero signature sets will be separated by 17 microseconds. These signature sets of pulses provide the receiver with the capability of distinguishing the infrared signal sent
by the transmitter from any background infrared radiation present, while accomplishing communication at speeds greater than 30,000 bits per second, high enough for communication of digital files by telemetry.
Communication between the hand held computer and the personal computer interface or other peripheral device is according to a packet protocol. With reference to FIG. 10, each packet 500 communicated by the system consists of a preamble 501 and
an optional body 502 of data appropriate, described as follows:
______________________________________ PREAMBLE + [BODY] Every PREAMBLE contains; BitSync ByteSync Lead-In ToID MyID Etype [EData] CRC Where: BitSync = 20 0x00's ByteSync = 3 0xFF's Lead-In = 0x1DA1 (short packet) 0xA210 (long packet)
ToID = 0 = packet for any unit listening; or = n (0<n<251) = packet for unit. with logical ID `n` MyID = n (1<n<255) = logical ID of the sending unit EType = Type of this packet preamble d7-d4 = Preamble type d3 = Repeated
transmission d2-d0 = Number of preamble [Edata] bytes prior to preamble CRC 0x12 = Broadcast Packet (future) 0x22 = Diagnostic Packet (reserved) 0x30 = SLAVE WRU 0x40 = MASTER WRU (future) 0x52 = IMA 0x60 = ZIT (request for `ACK me`) 0x70 =
Solicit 0x82 = ToYou 0x91 = ACK 0xA0 = (reserved) 0xB0 = (reserved) 0xC0 = Special 1 0xD0 = Special 2 0xE0 = Special 3 0XF0 = Special 4 [EData] = Envelop data (optional) [AckStatus] . . . when EType is ACK [BodyLong] = Number of bytes of BODY
contained within this packet. May be zero! Sent with ETypes: 0x12 = Broadcast Packet 0x22 = Diagnostic Packet 0x52 = IMA 0x82 = ToYou Ack Status Bits are dedicated as follows: d7 = 0 Version 1.0 d6 = 0 Version 1.0 d5 = 1 EMPTY d4 = 1 HOST
OFFLINE d3 = 1 NO HOST/NO CARRIER d2 = 1 BODY OVERFLOW d1 = 1 GARBAGE d0 = 1 FULL; Where: FULL: An indication that the unit initiating this ACK has no more buffers available for another packet. GARBAGE: An indication that the unit initiating
this ACK received a packet with a bad BODY CRC. NOTE: This could also be an indication of a failure in the preamble CRC. BODY OVERFLOW: An indication that the unit initiating this ACK received a packet where the body `length` exceeded the
available buffer size. NO HOST/NO CARRIER: Status bit indicating that the unit initiating this ACK does not currently have a host that is responding to any traffic. This is generated by the vPCI and MODEM peripherals only. HOST OFFLINE: Status
bit indicating that the unit initiating this ACK is connected to a HOST but that the HOST has notified this unit that it is unavailable. This is typical when, for example, a Personal Computer Interface (PCI) is connected to a host, communications
has occurred, but the host is not currently executing compatible code. EMPTY: Status bit indicating that the unit initiating this ACK has no filled and/or valid packets to report (or be solicited). The optional body of a packet has the following
format: Start Type Dest Source Command Status Length Data CRC Where: Start - varies from 0 to 255, used for synchronization of packet transfers. (One unique value could suffice.) Type - packet type 1 = Data Packet 2 = Command Packet (can have
status from last xfer) 3 = Status Packet ECC long Pkt - (D7 on for the above types) (PC will never see this type) Destination Bit Assignments - 1 = PC SPO 2 = HH SPO 3 = HH ATP 10 = PCI ATP 11 = Printer 12 = Barcode 13 = Modem 20 = Network
30 = Keyboard Source Bit Assignments - 1 = PC SPO 10 = HH SPO 11 = PCI ATP 12 = Printer 13 = Barcode 14 = Modem 21 = Network 31 = Keyboard Command Bit Assignments - 0 = Null Command (just more data in this packet) 1 = Begin Session 10 = End
Session 11 = Abort Session 20 = HH Receiver ready 21 = Resend N Status - Bit Assignments 1 = Ack 0 = Nack 10 = PCI Time-out on IR ( only issued to PC ) 11 = PCI Time-out on PC ( only issued to HH ) 20 = HH Time-out on PCI 21 = PC Time-out on
PCI Length - length of Data Field (usually Zero for Status Packets) Data - variable length The `Application Data` would employ a complete substructure of what is being sent (all receives are presumed to be preauthorized for size constraints). CRC
- of entire packet ______________________________________
Example sessions between a hand held computer HH and a personal computer PC are set out below.
______________________________________ HH to PC transfer: PC - Start Session CMD PCI - Waits for IR CMD HH - Start Session CMD (needed?) PCI - Acks HH if good CRC, else NACK PCI - sends to PC HH - sends data PCI - as it's reading from IR,
begins sending it up to the PC when it's all read in from the IR, and if CRC good, then ack HH (we're still shipping it to the PC) PC to HH transfer: PC - Start Session CMD PCI - Waits for IR CMD HH - HH receiver ready CMD PCI - Acks HH if good
CRC, else NACK PCI - gets from PC, building CRC when done, Start shipping it to the HH HH - receiving data PCI - as it's sending data to the HH, begins getting more from the PC when it's all sent to the IR, waits for Command or Status packet from
HH. Could be CMD packet with ack status & and HH Receiver ready (for more data) or end session. ______________________________________
Specific types of communications packets could be as follows:
______________________________________ EDPKT + < Tabname > + < Subtab name > + < Flags: G-up, G-down > + < # of entries > + < Remote EntryID, Entry Record > + . . . + < Remote EntryID, Entry Record > +
<EOP> ______________________________________
This is the packet that is returned to the HH from the PC, after the HH had issued the REDPKT call for the computer system described in the above referenced application entitled "Computer with Graphic Interfaces". It consists of the Tab and
Subtab names for the top line of the display, ghost flags, indicating whether to ghost the Up and/or Down buttons, the count of entry records in this packet, and the actual Remote Record ID's and Data. The PC only returns those records that can fit on
the HH's display. The Entry data in this packet do reflect the Entry Record structure.
This packet is returned to the HH when a passcode is required to access a Tab, Subtab, or Page display. The HH should put up the passcode gadget, get the user's passcode, stuff it in the request, and re-issue the call.
The HH issues this call after the user has selected the Remote button to get the Tab display of the Remote. The PC will either return a PCRQPKT or the Tab data with a TDPKT.
The HH issues this call after the user has selected a Tab Slot to get the Subtab display of the Remote. The PC will either return a PCRQPKT or the Subtab data with a SDPKT.
The application issues this call when the user has selected a Subtab to open. The PC will either return a PCRQPKT or the form data with a FMPKT. After the application has received the FMPKT, it should issue a REDPKT to get the first page of
data.
The application issues this call when the user has selected a Subtab to open. The PC will either return a PCRQPKT or a page worth's of display data with a EDPKT.
When copying or moving, and after the user has selected where to move/copy the data to, the application should issue this call to actually get the record associated by the Remote ID. To get all of the data associated with a Tab or Subtab, the HH
should walk the chain and request each record separately--the PC is not going to send back more than 1 record at a time. The PC sends the data back with the R4UPKT packet.
The HH uses this call to send a record to the PC. Again, as with the REXPKT call, to send all of the data associated with a Tab or Subtab, the HH should walk the chain and send each record separately--the PC hasn't any knowledge of the HH's
linkages. If the Remote Insert-after ID is zero, then it goes at the beginning of the chain. This field can be a slot number if the HH is on a Tab or Subtab display.
The PC returns this packet with a record in it after the HH has made the REXPKT call. If a passcode is required, the PC will return the PCRQPKT function instead, and the application, after receiving the user's passcode, should re-issue the
REXPKT call.
From the perspective of the HH, since it's the master, these are the calls to the communications system:
This is the packet that is returned to the HH from the PC, after the HH had issued the RTDPKT call. It consists of the Slot Number and Tab Name for each of the allocated Tabs of the remote book. The data in this packet do not reflect the
structure of allocated tabs in the current operating point.
This is the packet that is returned to the HH from the PC, after the HH had issued the RSDPKT call. It consists of the Tabname for the top line of the display, the remote Subtab ID, and the Slot Number and Subtab Name for each of the allocated
Subtabs of the remote book. The data in this packet do not reflect a Subtab record structure.
This is the packet that is returned to the HH from the PC, after the HH had issued the RFMPKT call. It consists of the FormiD of the remote book's form for the slot the user selected on the remote Subtab display, and the form record data. The
data in this packet does reflect the Form record structure, but without any p-code. The application (or RMGR) should check whether the HH already has this form by comparing the form's unique catalog number. If it does have the form, it should ignore
the data.
A detailed description of the preferred embodiment of the receiver in the personal computer interface or other peripheral device is given with reference to the figures.
FIG. 3 shows the overall design of the Infrared communications receiver and signal processor 100. The circuit processes an analog IR signal A1 produced by diode D1 receiving an infrared signal, in such a way as to produce a digital
representation IRIN at output D4 of the infrared signal.
An infrared signal is detected by the IR detector diode D1. This diode D1 generates a series current approximately proportional to
where K is a circuit constant, and DISTANCE is the distance between the source of the IR signal and the IR diode surface. The series current is amplified, compressed, filtered, and converted to a digital signal that appears at output D4. The D4
output signal referred to as IRIN is coupled to the communication controller 59 of FIG. 2. The communication control 59, recovers and processes the digital bit stream from IRIN.
Digital input signal IREN is used to put the receiver 100 circuit into a low power standby mode when not in the process of receiving a valid IR input signal.
FIG. 3 also indicates external circuitry which is connected to the receiver 100. In this respect, external capacitor C1e is connected between pad 4 and analog ground. External capacitor C3e is connected between pad 5 and analog ground.
External capacitor C4c is connected between pads 7 and 8. Pad 9 is connected to diode D1. In turn, diode D1 has a common connection between external capacitor C5c and external resistor R4c. External capacitor C5c is also connected to pad 10, and
external resistor R4c is connected to analog ground. Connected between pad 11 and analog ground is external capacitor C3c. Connected between pad 14 and analog ground is external capacitor C4d. Pads 12, 13, 15, and 19 are all connected. Pad 12 is
connected to a common connection between external capacitor C1c and external resistor R2c. Pad 13 is connected to external resistor R1c, which is, in turn, connected to a common connection between external capacitors C2c and C1c. Pad 15 is connected to
external capacitor C3c, which is, in turn, connected to a common connection between external resistor R3c and external capacitor C2c. Pad 19 is connected to a common connection between external capacitor C2e, external resistor R3c, and external resistor
R2c. External capacitor C2e is then connected to analog ground. Connected in parallel between pad 20 and analog ground are external capacitor C1d and external resistor R1d.
Further connected to receiver 100 are +5 voltage supplies and ground connections. Analog+5 volts is connected to pad 3. Analog ground is connected to pad 6. Digital +5 volts is connected to pad 16. Digital ground is connected to pad 18.
The internal circuitry of receiver 100 consists of power management and biasing 200, and the subcircuits 201-210 set forth in FIG. 4. Power management and biasing 200 and the main subcircuits in FIG. 4 are connected as follows:
The power management and biasing subcircuit 200 establishes internal reference voltages A13a, A13b, VLOG, C1, and E5.
The logarithmic pre-amp 201 receives the noninverted and inverted IR inputs A0 and A1, respectively. The internal reference nodes, A13a and E5 are also connected to pre-amp 201. It is further connected to node D7 from subcircuit 207 discussed
below. The output PA0 of the logarithmic pre-amplifier 201 is connected to highpass filter 202.
This highpass filter 202 is coupled to internal reference node NC1. From the highpass filter 202, the inputs to a balanced bridge compression amplifier 203 are BPI and BPR.
The bridge amplifier 203 is also coupled to internal reference nodes E5, NC1, and A13b, and node D7. The bridge amplifier 203 output pair G5 and G9, is connected to the lowpass filter amplifier 204.
This lowpass filter amplifier 204 is also coupled to reference node E5. Its output BPO is the input to the VCVS highpass filter 205.
This filter is coupled to nodes NC1 and E5. T | | |
