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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for receiving and outputting signals representative of full color containing half-tone, which are used for a color scanner, color CRT, color printer, color copying machine, or the like, and an apparatus
for executing the method. More particularly, the invention relates to a method for transforming color signals in order to reproduce a color faithfully, and an apparatus for executing the method.
2. Description of the Related Art
In the fields of color printing, color television, color copying machine and the like, there are many proposals to transform color signals. In a typical example of those proposals, an input color space, e.g., a BGR coordinate, is directly
transformed into an output color space, e.g., a YMC (K) coordinate by using a table memory. When three color signals in a BGR coordinate, for example, are transformed into digital signals at resolutions of the necessary gray levels, a great amount of
table data is required. To store the data, a table memory with a large memory capacity must be provided. Such a memory is very expensive.
For example, in a case where each of the input colors B, G, and R are expressed by 8 bits, and the output colors Y, M, C, and K are also expressed by 8 bits, the required memory capacity of the table memory is 2.sup.24 .times.4 bytes. It is
impractical to use such a big memory.
Many interpolation basis methods have been proposed for reducing the necessary memory capacity in transforming color signals by using the table memory. In these methods, a color correction memory addressed with the higher bits of the input
signals is used for reducing the necessary memory capacity. The coarsened data is corrected by using an interpolation circuit using the lower bits.
The interpolation basis method disclosed in Published Examined Japanese Patent Application No. Sho. 58-16180 will be described with reference to FIG. 11 and with use of equation (1). ##EQU1##
FIG. 11 is an explanatory diagram showing the process to divide a unit cube. A unit cube as an object to be interpolated is divided, in three planes x=y, y=z, and z=x, into six tetrahedrons denoted as {1} to {6}. The equation (11) is a
mathematical expression of the interpolation for the tetrahedral region {2}. In the equation, x.sub.h, y.sub.h, and z.sub.h represent the higher bits of an input; x.sub.1, y.sub.1, and z.sub.1, the lower bits of the same; X' (x, y, z) indicates a value
of one output in the input (x, y, z).
In the interpolation method, the lower bits at a point to be interpolated are comparatively checked to determine which tetrahedron contains the interpolated point. The output values corresponding to the four vertexes of the tetrahedron
containing the interpolated point are read out of a color correction memory, and are multiplied by four coefficients that are obtained by the subtraction of the lower bits, and the products are added together.
The above publication refers to the method of comparatively checking the lower bits, and the method of reading the output values corresponding to the four vertexes of the tetrahedron from the color correction memory, but does not refer to the
details of the specific methods. However, the technique disclosed in the publication has the following problems as determined from the limited descriptions in the publication.
(1) An address calculation for the memory is complicated, when the output values corresponding to the four vertexes of the tetrahedron are read out of the color correction memory. When the hardware technique is used for the address calculation,
the hardware construction is complicated. When the software technique is used for the same, much time is taken for processing the address calculation.
(2) Data must be regularly arranged in the color correction memory to allow the output values corresponding to the four vertexes of the tetrahedron to be read from the color correction memory. This technique is contradictory to the technique,
proposed by the inventor of the present Patent Application (in Published Unexamined Japanese Patent Application No. Hei. 2-73779), in which the memory portion out of a color reproduction range of the output is removed by irregularly rearranging the
regularly arranged data.
(3) As seen from the equation (1), a total number of required calculations is ten; three calculations for the lower bits, four calculations for multiplying the subtraction result by the outputs corresponding to the four vertexes of the
tetrahedron, and three calculations for the final addition. A complicated hardware must be constructed for the calculations or much time must be taken for performing the calculations when the software is used for the calculations.
(4) When strictly considered, the dividing method of FIG. 11 has difficulty in handling data in the boundary face. For yf and zf, two comparisons must be made: yf>zf and yf.gtoreq.zf.
To solve the problems (1) to (3), the inventor of the present Patent Application has proposed the interpolation method shown in FIG. 12 and mathematically expressed by an equation (2) in Published Unexamined Japanese Patent Application No. Hei.
2-187374. ##EQU2##
In the above equation, X'(x.sub.h, y.sub.h, z.sub.h) indicates a reference value of the output of a unit cube as an object to be interpolated.
a.sub.x (x.sub.h, y.sub.h, z.sub.h), a.sub.y (x.sub.h, y.sub.h, z.sub.h), and a.sub.z (x.sub.h, y.sub.h, z.sub.h) represent interpolation sensitivity signals for the unit cube.
b.sub.x (x.sub.h, y.sub.h, z.sub.h), b.sub.y (x.sub.h, y.sub.h, z.sub.h), and b.sub.z (x.sub.h, y.sub.h, z.sub.h) represent interpolation sensitivity select signals for the unit cube.
c (b.sub.x (x.sub.h, y.sub.h, z.sub.h), x.sub.1), c (b.sub.y (x.sub.h, y.sub.h, z.sub.h), y.sub.1), and c (b.sub.z (x.sub.h, y.sub.h, z.sub.h), z.sub.1) stand for interpolation values.
The interpolation method, as just mentioned, completes with only two steps, viz., one to make an access to the memory without any address calculation and the other to add together the readout data. The hardware to implement the method is simple
in construction.
Further, the regular arrangement of data in the color correction memory is not essential. Accordingly, the technique is compatible with the technique (Published Unexamined Japanese Patent Application No. Hei. 2-73779) which removes the memory
portion out of the color reproduction range of the output by rearranging the regularly arranged data into an irregular arrangement of data.
A modification of the FIG. 12 circuit that can readily be anticipated from the upper half of the equation (2) was also proposed. The modification is as illustrated in FIG. 13. A hardware to implement the modification that is constructed using
the multipliers as in the case of FIG. 11, needs a total of only six calculations: three multiplications for each output and three additions for each output.
The deficiency common for the FIGS. 12 and 13 cases is that the boundary between the adjacent interpolation regions is discontinuous since a hexahedron including eight (8) vertexes, viz., an object to be interpolated of which freedom degree is
eight (8) for each output color, is interpolated with four parameters X' (x.sub.h, y.sub.h, z.sub.h), and a.sub.h (x.sub.h, y.sub.h, z.sub.h), a.sub.y (x.sub.h, y.sub.h, z.sub.h) and a.sub.z (x.sub.h, y.sub.h, z.sub.h). Reduction of the interpolated
regions, viz., increase of the higher bits, will apparently secure the continuity at the boundaries. However, the increase of the higher bits results in an increased memory capacity.
SUMMARY OF THE INVENTION
In view of the described background, the present invention has an object to provide a method for transforming color signals and an apparatus for executing the method, which have the following advantageous features:
(1) Complicated address conversion is not required when the memory is accessed. High speed processing is possible with a simple circuit arrangement.
(2) The regular arrangement in the color correction memory is not essential. The technique of the invention is compatible with the above-mentioned technique, which removes the memory portion out of the color reproduction regions by arranging
irregular the data that are regularly arranged in the memory (Published Unexamined Japanese Patent Application Nos. Hei. 2-73779 and 2-187374).
(3) The number of calculations for each output is reduced to be as small as possible. Accordingly, a high speed processing is realized with a simple circuit construction.
(4) Continuity at the boundary region is secured.
(5) The data at the boundary surfaces when the division/interpolation is carried out is accurately handled, thereby eliminating unnecessary comparing operations.
A method is provided for transforming color signals in which three input signals representative of colors are each divided into the higher bits and the lower bits, the higher bits are combined to form basic data, the lower bits are combined to
form interpolation data, and the basic data and the interpolation data are added to each other, thereby forming output signals, and in which the hexahedron of an object to be interpolated is divided into six tetrahedrons each passing through one of eight
lattice points constituting the hexahedron of the interpolated object, and the different combinations of interpolation data are assigned to the tetrahedrons in one-to-one correspondence manner. ##EQU3##
In the above equation, X' (x.sub.h, y.sub.h, z.sub.h) represents basic data as the combination of the higher bits.
a.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), a.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), a.sub.z (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)), a.sub.x (e.sub.i,i=1,7
(x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)), a.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), and a.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1, z.sub.1))
represent interpolation sensitivity signals.
b.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), c(b.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), c(b.sub.z (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)), b.sub.x
(e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)), b.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), and b.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1,
z.sub.1)) represent interpolation sensitivity select signals.
c(b.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), x.sub.1), c(b.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), y.sub.1), c(b.sub.z (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1,
z.sub.1)), z.sub.1), c(x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1), x.sub.1), c(x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1), y.sub.1), c(x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1), z.sub.1),
c(b.sub.x (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)),x.sub.1), c(b.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), y.sub.1), and c(b.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h,
z.sub.h), d.sub.z (x.sub.1, y.sub.1, z.sub.1)), z.sub.1) represent interpolation data.
d.sub.x (x.sub.1, y.sub.1, z.sub.1), d.sub.y (x.sub.1, y.sub.1, z.sub.1), and d.sub.z ((x.sub.1, y.sub.1, z.sub.1) are interpolation region select signals as the combinations of the lower bits.
e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h) indicates difference data corresponding to seven lattice points as the remaining lattice points when one of the eight lattice points of each of the hexadrons of the interpolated regions as the
combinations of the higher bits, is a reference point.
Specific examples of the dividing method are shown in FIGS. 1 and 2. Interpolation sensitivity signals a.sub.x, a.sub.y, and a.sub.z in the dividing methods are shown in Tables 1 and 2.
In FIGS. 1 and 2, the hexadrons of the interpolated objects are illustrated as cubes; however, those may be cuboids of which the sides are different, or modified hexadrons in the case of the inputs expressed in the polar coordinates.
TABLE 1 __________________________________________________________________________ Unit Hexadron Dividing Method 1 __________________________________________________________________________ Region z.sub.1 > x.sub.1 x.sub.1 > = y.sub.1
y.sub.1 > z.sub.1 No. x.sub.1 > = y.sub.1 y.sub.1 > z.sub.1 z.sub.1 > x.sub.1 x.sub.1 > = y.sub.1 y.sub.1 > z.sub.1 z.sub.1 > x.sub.1 __________________________________________________________________________ {1} (1) 0 0 01 10
00 {2} 1 1 (0) same 11 10 as {1} {3} 1 (0) 1 11 same 01 as {1} {4} 0 0 (1) 10 00 same as {3} {5} 0 {1} 0 00 01 same as {2} {6} (0) 1 1 same same 11 as {4} as {5} __________________________________________________________________________
Region No. a.sub.x .multidot. x.sub.h1 a.sub.y .multidot. y.sub.h1 a.sub.z .multidot. z.sub.h1 __________________________________________________________________________ {1} X'(x.sub.h+1,y.sub.h,z.sub.h) - X'(x.sub.h+1,y.sub.h+1,z.sub.h+1)
X'(x.sub.h+1,y.sub.h,z.sub.h+1) - X'(x.sub.h,y.sub.h,z.sub.h) X'(x.sub.h+1,y.sub.h,z.sub.h) {2} same as {1} X'(x.sub.h+1,y.sub.h+1,z.sub.h) - X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) X'(x.sub.h+1,y.sub.h,z.sub.h) {3} X'(x.sub.h+1,y.sub.h,z.sub.h+1) -
same as {1} X'(x.sub.h,y.sub.h,z.sub.h+1) - X'(x.sub.h,y.sub.h,z.sub.h+1) X'(x.sub.h,y.sub.h,z.sub.h) {4} X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) X'(x.sub.h,y.sub.h+1,z.sub.h+1 ) - same as {3} X'(x.sub.h,y.sub.h,z.sub.h+1) {5}
X'(x.sub.h+1,y.sub.h+1,z.sub.h) - X'(x.sub.h,y.sub.h+1,z.sub.h) - same as {2} X'(x.sub.h,y.sub.h+1,z.sub.h) X'(x.sub.h,y.sub.h,z.sub.h) {6} same as {4} same as {5} X'(x.sub.h,y.sub.h+1,z.sub.h+1) - X'(x.sub.h,y.sub.h+1,z.sub.h)
__________________________________________________________________________ x.sub.h1, y.sub.h1, and z.sub.h1 : Unit length of the object regions to b interpolated
TABLE 2 __________________________________________________________________________ Unit Hexadron Dividing Method 2 __________________________________________________________________________ x.sub.1 > = y.sub.1 y.sub.1 > = z.sub.1
z.sub.1 = > x.sub.1 x.sub.1 - y.sub.1 - z.sub.1 > = 0 Region x.sub.1 > = y.sub.1 > = z.sub.1 > = x.sub.1 - y.sub.1 - x.sub.1 - y.sub.1 + x.sub.1 - y.sub.1 + y.sub.1 > = z.sub.1 No. y.sub.1 z.sub.1 x.sub.1 z.sub.1 > = 0
z.sub.1 > = 0 z.sub.1 > = 0 z.sub.1 > = x.sub.1 __________________________________________________________________________ {1} (1) (.sub.--) (0) 1 (1) 1-011 00 {2} 1 (.sub.--) 0 0 (1) 1-001 10 {3} 1 (0) 1 (0) (1) 1-101 01 {4} 0 0 (1) (0)
(1) 00-01 same as {3} {5} 0 1 (.sub.--) (0) 1 01-01 same as {2} {6} (0) (1) (.sub.--) (0) 0 01-00 11 __________________________________________________________________________ Region No. a.sub.x .multidot. x.sub.h1 a.sub.y .multidot. y.sub.h1
a.sub.z .multidot. z.sub.h1 __________________________________________________________________________ {1} X'(x.sub.h+1,y.sub.h,z.sub.h) - X'(x.sub.h+1,y.sub.h+1,z.sub.h) - X'(x.sub.h+1,y.sub.h,z.sub.h+1) - X'(x.sub.h,y.sub.h,z.sub.h)
X'(x.sub.h+1,y.sub.h,z.sub.h) X'(x.sub.h+1,y.sub.h,z.sub.h) {2} X'(x.sub.h+1,y.sub.h+1,z.sub.h) - X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) - X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) - X'(x.sub.h,y.sub.h,z.sub.h) - X'(x.sub.h+1,y.sub.h,z.sub.h+1)
X'(x.sub.h+1,y.sub.h+1,z.sub.h) X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) + X'(x.sub.h+1,y.sub.h,z.sub.h+1) {3} X'(x.sub.h+1,y.sub.h,z.sub.h+1) - same as {2} X'(x.sub.h,y.sub.h,z.sub.h+1) - X'(x.sub.h,y.sub.h,z.sub.h+1) X'(x.sub.h,y.sub.h,z.sub.h) {4}
X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) - X'(x.sub.h,y.sub.h+1,z.sub.h+1) - same as {3} X'(x.sub.h,y.sub.h+1,z.sub.h+1) X'(x.sub.h,y.sub.h,z.sub.h+1) {5} same as {4} X'(x.sub.h+1,y.sub. h+1,z.sub.h) - same as {2} X'(x.sub.h,y.sub.h,z.sub.h) -
X'(x.sub.h+1,y.sub.h+1,z.sub.h+1) + X'(x.sub.h,y.sub.h+1,z.sub.h+1) {6} X'(x.sub.h+1,y.sub.h+1,z.sub.h) - X'(x.sub.h,y.sub.h+1,z.sub.h) - X'(x.sub.h,y.sub.h+1,z.sub.h+1) - X'(x.sub.h,y.sub.h+1,z.sub.h) X'(x.sub.h,y.sub.h,z.sub.h)
X'(x.sub.h,y.sub.h+1,z.sub.h) __________________________________________________________________________ x.sub.h1, y.sub.h1, and z.sub.h1 : Unit length of the object regions to b interpolated.
An apparatus for executing the color signal transforming method having three input signals (L*, a*, b*) representative of colors being each divided into the lower bits and the higher bits which are combined to form address signals, a color
correction memory (1 in FIGS. 1 through 10), when receiving the address signals, for producing basic data, interpolation data generating means (5, 6, and 7 in FIG. 3, 5, 6, and 8 in FIG. 4; 2, 4, and 8 in FIG. 6; 2 and 8 in FIG. 7; 6, 8, 9, 10, and 11 in
FIG. 8; 2, 8, 9, 10, 11, and 12 in FIG. 9) for generating the combinations of interpolation data in accordance with the combinations of the higher bits and the lower bits, and adder means (3 in FIGS. 3 through 10) for adding the output signal of the
color correction memory and the output signal of the interpolation data generating means, thereby to produce an output signal. In the color signal transforming apparatus, the interpolation data generating means includes means (5 and 7 in FIG. 3; 5 and 8
in FIG. 4; 4 and 7 in FIG. 5; 4 and 8 in FIG. 6; 8 in FIG. 7; 8, 9, 10, and 11 in FIG. 8; 2, 8, 9, 10, 11, and 12 in FIG. 9) for dividing the hexahedron of an object to be interpolated into six tetrahedrons each passing through one of eight lattice
points constituting the hexahedron of the interpolated object, and for assigning the different combinations of interpolation data to the tetrahedrons in one-to-one correspondence manner.
In the color signal transforming apparatus constructed as just mentioned, the interpolation data generating means includes interpolation region select memory means (7 in FIG. 3; 7 in FIG. 5; 7 and FIG. 10) for outputing a plurality of
interpolation region select signals that are fit to the commonness of the interpolation sensitivity signals, with the combination of the lower bits as an address signal, to specify to which of the six tetrahedrons each the input signal belongs.
The interpolation region select signals correspond to d.sub.x (x.sub.1, y.sub.1, z.sub.1), d.sub.y (x.sub.1, y.sub.1, z.sub.1), and d.sub.z ((x.sub.1, y.sub.1, z.sub.1) in the equation (3), and to the signals represented by [z.sub.1 >x.sub.1,
x.sub.1 .gtoreq.y.sub.1 ], [x.sub.1 .gtoreq.y.sub.1, y.sub.1 .gtoreq.z.sub.1 ], [y.sub.1 >z.sub.1, z.sub.1 >x.sub.1 ], [x.sub.1 .gtoreq.y.sub.1, y.sub.1 .gtoreq.z.sub.1 ], z.sub.1 .gtoreq.x.sub.1, x.sub.1 -y.sub.1 -z.sub.1 .gtoreq.0, x.sub.1
-y.sub.1 +z.sub.1 .gtoreq.0] in Tables 1 and 2.
As seen from Tables 1 and 2, the interpolation sensitivity signals a.sub.x, a.sub.y, and a.sub.z of the six tetrahedrons are different from one another, but when observing individually the elements of the signals a.sub.x, a.sub.y, and a.sub.z,
the elements have something in common with one another. The interpolation region select signals are set so as to be fit to the commonality.
In the color signal transforming apparatus, the interpolation data generating means may include, in place of the interpolation region select memory means, a plurality of comparators (8 in FIGS. 4, 6, 7, 8, and 9) for comparing the lower bits of
the three input signals, some shifted lower bits of the three input signals, or the results of the addition/subtraction of them, and means for producing the combinations of the output signals of the comparators in the form of a plurality of interpolation
region select signals that are fit to the commonness of the interpolation sensitivity signals.
The color signal transforming apparatus as just mentioned calculates interpolation region select signals by using the comparators, for example, instead of causing the memory to produce those signals. Why the circuit arrangements of FIGS. 1 and 2
are different will be seen from the interpolation region select signals in Tables 1 and 2.
Where the numbers of the lower bits of the three input signals are different, these are ordered in their places by shift registers before input to the comparators.
The interpolation data generating means may include interpolation sensitivity output memory means (5 in FIGS. 3, 4, and 10) for producing a plurality of interpolation sensitivity signals in response to address signals consisting of the
combination of the higher bits of the three input color signals and some of the interpolation region select signals, and a plurality of interpolation data calculating means (6 in FIGS. 3, 4, and 10) for producing interpolation data by multiplying one of
the output signals of the interpolation sensitivity output memory means by the lower bit of one of the three input color signals.
The plurality of interpolation sensitivity output signals correspond to a.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), a.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)), and a.sub.z (x.sub.h,
y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)) in the equation (3).
Instead of the interpolation sensitivity output memory means and the plurality of interpolation data calculating means, the interpolation data generating means may include interpolation sensitivity select output memory means (4 in FIGS. 5 and 6)
for producing a plurality of interpolation sensitivity signals in response to address signals consisting of the combination of the higher bits of the three input color signals and some of the interpolation region select signals, and a plurality of
interpolation data output memory means (2 in FIG. 5; 6 in FIG. 6) for producing interpolation data in response to an address signal including one of the output signals of the interpolation sensitivity select output memory means and the lower bit of one
of the three input color signals.
The plurality of interpolation sensitivity select output signals correspond to b.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), b.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), and b.sub.z
(x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)) in the equation (3).
The interpolation data output signals correspond to c(b.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), x.sub.1), c(b.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), y.sub.1) and c(b.sub.z (x.sub.h,
y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)) in the equation (3).
In this case, the memory is used in place of the multiplying operation. Accordingly, there is no need of using the interpolation intensities per se. Interpolation sensitivity select output signals to specify the memory addresses where the
corresponding interpolation intensities are stored.
In the color signal transforming apparatus, the interpolation data generating means may include, instead of the interpolation sensitivity output memory means and the interpolation data calculating means for multiplying operation, a plurality of
interpolation data output memory means (7 in FIG. 7) for producing interpolation data in response to address signals consisting of the combination of the higher bits of the three input color signals and some of the interpolation region select signals,
and the lower bit of one of the three input color signals.
The interpolation data output signals correspond to c (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1), x.sub.1), c(x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1), y.sub.1), c(x.sub.h, y.sub.h, z.sub.h, d.sub.z
(x.sub.1, y.sub.1, z.sub.1), z.sub.1) in the equation (3).
Instead of the interpolation sensitivity output memory means, the interpolation data generating means includes interpolation sensitivity output means containing a memory portion (9 in FIG. 8) for producing difference data corresponding to seven
lattice points as the remaining lattice points when one of the eight lattice points of each of the hexadrons of the interpolated regions as the combinations of the higher bits is a reference point in response to an address signal as the combination of
the higher bits of the three input color signals, a plurality of subtractor portions (10 in FIG. 8) for calculating the difference between the difference data, and a portion (11 in FIG. 8) for selecting a plurality of proper interpolation sensitivity
output signals from among the difference data or the subtraction results by using some of the interpolation region select signals; and a plurality of interpolation data output means (6 in FIG. 8) for outputing output data by multiplying one of the output
signals of the interpolation sensitivity output means by the lower bit of one of the three input signals.
The difference data corresponding to seven lattice points as the remaining lattice points when one of the eight lattice points of each of the hexadrons of the interpolated regions is a reference point corresponds to e.sub.i,i=1,7 (x.sub.h,
y.sub.h, z.sub.h) in the equation (3). The interpolation sensitivity output signals correspond to a.sub.x (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.h, y.sub.h, z.sub.h)), a.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y
(x.sub.h, y.sub.h, z.sub.h)), and a.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.h, y.sub.h, z.sub.h)).
Instead of the interpolation sensitivity select output memory means, the interpolation data generating means includes interpolation sensitivity select output means containing a memory portion (9 in FIG. 9) for producing difference data
corresponding to seven lattice points as the remaining lattice points when one of the eight lattice points of each of the hexadrons of the interpolated regions as the combinations of the higher bits is a reference point in response to an address signal
as the combination of the higher bits of the three input color signals, calculating portions (10 in FIG. 9) for forming interpolation sensitivity select output signals from the difference data, portions (11 in FIG. 9) for selecting a plurality of proper
interpolation sensitivity output signals from among the difference data or the subtraction results by using some of the interpolation region select signals, and portions (12 in FIG. 9) for transforming the plurality of selected interpolation sensitivity
output signals into a plurality of interpolation sensitivity select signals; and a plurality of interpolation data output means (2 in FIG. 9) for outputting interpolation data in response to an address signal containing one of the output signals of the
interpolation sensitivity select output means and the lower bit of one of the three input signals.
The interpolation sensitivity select output signals correspond to b.sub.x (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.h, y.sub.h, z.sub.h)), b.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.h, y.sub.h, z.sub.h)),
and b.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.h, y.sub.h, z.sub.h)) in the equation (3). The interpolation output signals correspond to c (b.sub.x (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)),
x.sub.1), c (b.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), y.sub.1, and c (b.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1, z.sub.1)), z.sub.1) in the equation (3).
A color signal transforming apparatus comprises a start address/lower bit generating memory (13 in FIG. 10), when receiving an address signal containing two of three input signals representative of a first colorimetric coordinate, for producing a
start address previously set in consideration of a color reproduction range of an output device and the modified lower bits of the two input signals; maximum/minimum generating means (14 in FIG. 10), when receiving an address signal containing two of the
three input signals, for generating the maximum and minimum values of the remaining one input signal in consideration of the color reproduction range of the output; calculating means (16 and 17 in FIG. 10) for modifying the remaining one input signal
using the maximum and minimum values output from the maximum/minimum generating means; an address adder (15 in FIG. 10) for adding the start address output from the start address/lower bit generating memory and the higher bit of a fixed number of the
remaining one input signal; a basic data color correction memory (1 in FIG. 10) for producing basic data signals representative of colors of a second colorimetric coordinate in response to an address signal as the output signal of the address adder;
interpolation data generating means (7, 5, and 6 in FIG. 10) for generating a set of interpolation data on the basis of the combination of the higher bits output from the address adder and the combination of the modified lower bits of the input signals;
adder means (3 in FIG. 10) for producing output signals representative of colors of the second colorimetric coordinate by adding the output signal of the basic data color correction memory and the output signal of the interpolation data generating means;
and the interpolation data generating means including means (7 and 5 in FIG. 10) for dividing the hexahedron of each object to be interpolated into six tetrahedrons each passing through one of eight lattice points constituting the hexahedron of the
interpolated object, and for assigning different combinations of interpolation data to the tetrahedrons in one-to-one correspondence manner.
In the present invention, three input signals representative of colors are each divided into the higher bits and the lower bits. The color correction memory for basic data is addressed with the combination of the higher bits, so that it produces
basic data corresponding to X' (x.sub.h, y.sub.h, z.sub.h) in the equation (3).
The combination of the higher bits is input as an address signal to the memory means for interpolation region select or is input to the interpolation region select signal output means including comparators, for example, which in turn produces a
plurality of interpolation region select signals corresponding to d.sub.x (x.sub.1, y.sub.1, z.sub.1), d.sub.y (x.sub.1, y.sub.1, z.sub.1), and d.sub.z (x.sub.1, y.sub.1, z.sub.1) in the equation (3).
The combination of the higher bits of the input signals and some of the interpolation region select signals are input to the interpolation sensitivity output memory means, the interpolation sensitivity select output means, interpolation
sensitivity output means, or interpolation sensitivity select output means, so that a plurality of interpolation sensitivity signals corresponding to a.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), a.sub.y (x.sub.h, y.sub.h,
z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)), and a.sub.z (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)) or a.sub.x (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)), a.sub.y (e.sub.i,i=1,7 (x.sub.h,
y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), and a.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1, z.sub.1)) in the equation (3) or a plurality of interpolation sensitivity select signals corresponding to b.sub.x
(x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), b.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), b.sub.z (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)) or b.sub.x (e.sub.i,i=1,7 (x.sub.h,
y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)), b.sub.y (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), b.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1, z.sub.1)) in the equation
(3) are output.
Each of the plurality of interpolation sensitivity output signals is multiplied by one of the lower bits of the input signal or each interpolation sensitivity select output signal and the lower bits of the input signal are input as address
signals to the plurality of interpolation data output memory means, so that plural interpolation data corresponding to c(b.sub.x (x.sub.h, y.sub.h, z.sub.h, d.sub.x (x.sub.1, y.sub.1, z.sub.1)), x.sub.1), c(b.sub.y (x.sub.h, y.sub.h, z.sub.h, d.sub.y
(x.sub.1, y.sub.1, z.sub.1)), y.sub.1), c(b.sub.z (x.sub.h, y.sub.h, z.sub.h, d.sub.z (x.sub.1, y.sub.1, z.sub.1)), z.sub.1), or c(b.sub.x (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)), x.sub.1), c(b.sub.y
(e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.y (x.sub.1, y.sub.1, z.sub.1)), y.sub. 1), c(b.sub.z (e.sub.i,i=1,7 (x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1, z.sub.1)), z.sub.1) in the equation (3) are output.
The combination of the higher bits of the input signals and the interpolation region select signals, the lower bits of the input signal are input as address signals to the plurality of interpolation data output memory means, so that plural
interpolation data corresponding to c((x.sub.h, y.sub.h, z.sub.h), d.sub.x (x.sub.1, y.sub.1, z.sub.1)), x.sub.1), c(x.sub.h, y.sub.h, z.sub.h, d.sub.y (x.sub.1, y.sub.1, z.sub.1)), y.sub.1), c(x.sub.h, y.sub.h, z.sub.h), d.sub.z (x.sub.1, y.sub.1,
z.sub.1)), z.sub.1) in the equation (3) are output.
Finally, the basic data is added to the plural interpolation data, so that an interpolated value corresponding to X' (x, y, z) is output.
In addition to the arrangement of the color signal transforming apparatus including the interpolation data generating means, the color signal transforming apparatus of the invention may take the arrangement including the start address/lower bit
generating memory and the address adder. The latter arrangement of the apparatus has the advantageous effects comparable with those of the former ar | | |
