A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.
Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.
A gate delay calculation apparatus includes an R.sub.s parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continuous time function, an R.sub.s determination portion for selectively extracting the parameter prestored in the R.sub.s parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by R.sub.s determination portion and the output load model.
An on-chip optimization circuitry (105) of a semiconductor device (100) provides a delay value to a delay generator (120) indicating an amount to delay an active signal edge. Based on the delay value, a modified device timing is created. Using the modified device timing, a portion of the semiconductor device (130) is tested using on-chip verification circuitry (110) to determine functionality. Based on functionality, a determination is made whether an optimal delay value has been found (550). If an optimal delay value has not been determined, a new delay value is used to produce a new modified device timing (516) and the sequence of testing and determining functionality is repeated until a optimized value has been determined.
The wire length of an LSI is estimated from a netlist describing connection information of the LSI and a cell library storing information as to cells used in the LSI design, with performing no rough placement and rough wiring by a layout system. Information necessary for wire length estimation is extracted from the netlist and the cell library. A net basic wire length is determined for each fan-out. In a net wire length estimating step, a net wire length for each fan-out is estimated by making reference to the determined net basic wire length and taking into account net expansion due to the cell distribution in a cell placement. Additionally, taking into account a terminal distribution and the aspect ratio of an estimation-target block, a correction on the estimated net wire length is made. From the corrected net wire length, the total wire length of the estimation-target block is estimated.
A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.
