Dynamic random access memory with bit line preamp/driver

Claims

What is claimed is:

1. A random access memory, comprising:

a plurality of single transistor memory cells configured in an array and each having a memory capacitor for storing a logic "0" voltage or a logic "1" voltage;

an inner Bit Line;

an access device for selectively connecting one of said memory cells to said inner Bit Line in response to an external access signal such that said memory capacitor can transfer charge to and from said inner Bit Line;

an outer Bit Line;

a Bit Line preamp/driver circuit for driving said outer Bit Line from a source different from said inner Bit Line as said access device accesses said memory cell, such that said outer Bit Line is not directly coupled to said inner Bit Line, said outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in said accessed memory cell; and

a restore circuit interfaced with said outer Bit Line and operable to sense the logic state on said outer Bit Line and drive the voltage on said outer Bit Line to either a full logic voltage or to a ground voltage, respectively, during a restore operation depending upon whether said logic "1" voltage as said logic "0" voltage is present on said outer Bit Line, said restore circuit operable to drive said inner Bit Line to substantially the same voltage as the outer Bit Line during said restore operation.

2. The memory of claim 1 and further comprising a read circuit for distinguishing between a logic "0" and a logic "1" voltage on said outer Bit Line and converting the voltage on said outer Bit Line to a substantially amplified voltage in response to the logic state determined to be on said outer Bit Line.

3. The memory of claim 1, wherein said restore circuit comprises:

a cross-coupled latch having first and second sense nodes, with one of said first and second sense nodes connected to a reference voltage and the other of said first and second sense nodes connected to said outer Bit Line, said latch operable to distinguish between a logic "1" voltage and a logic "0" voltage on said outer Bit Line and operable to drive said outer Bit Line to substantially full logic levels as a function of the distinguished logic voltage thereon;

a Write device for selectively connecting said outer Bit Line to said inner Bit Line to drive said inner Bit Line from said outer Bit Line; and

a Restore control signal to activate said Write device during a restore operation after said access device has selectively connected one of said memory cells to said inner Bit Line.

4. The memory of claim 1, and further comprising:

a Data Line for being disposed at a logic "1" voltage or a logic "0" voltage;

an interface device for driving said Data Line from a source other than said inner Bit Line or said outer Bit Line, said interface device isolated from said outer Bit Line by said Bit Line preamp/driver circuit;

said interface device controlled by the logic voltage on said inner Bit Line such that the logic voltage on said Data Line corresponds to the logic voltage on said inner Bit Line; and

a Read circuit for distinguishing between a logic "0" and a logic "1" voltage on said Data Line and driving said Data Line to either a full circuit potential or to ground in response to the logic state determined to be on said Data Line.

5. The memory of claim 4 wherein said interface device comprises:

a depletion transistor configured as a source follower having the source/drain path thereof disposed between a source other than said outer or inner Bit Line and said Data Line; and

a current source for being driven by said depletion transistor, the gate of said depletion transistor controlled by the voltage on said inner Bit Line.

6. The memory of claim 1 and further comprising:

a Data Line for being disposed at either a logic "1" voltage or a logic "0" voltage;

an interface device for driving said Data Line from a source other than said outer Bit Line or said inner Bit Line;

said interface device controlled by the logic voltage on said outer Bit Line such that the logic voltage on said Data Line corresponds to the logic voltage on said outer Bit Line; and

a Read circuit for distinguishing between a logic "0" and a logic "1" on said Data Line and driving said Data Line to either a full circuit potential or to ground in response to the logic state determined to be on said Data Line.

7. The memory of claim 6 wherein said interface device comprises:

a depletion transistor configured as a source follower having the source/drain path thereof disposed between a source other than said outer or inner Bit Lines; and

a current source for being driven by said depletion transistor, the gate of said depletion transistor controlled by the voltage on said outer Bit Line.

8. A random access memory, comprising:

a plurality of single transistor memory cells configured in an array and each having a memory capacitor for storing a logic "0" voltage or a logic "1" voltage;

an inner Bit Line;

an access device for selectively connecting one of said memory cells to said inner Bit Line in response to an external access signal such that said memory capacitor can transfer charge to and from said inner Bit Line;

an outer Bit Line;

a Bit Line preamp/driver circuit for driving said outer Bit Line from a source different from said inner Bit Line as said access device accesses said memory cell, such that said outer Bit Line is not directly coupled to said inner Bit Line, said outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in said accessed memory cell; and

a precharge device for precharging said inner Bit Line to a predetermined voltage, said Bit Line preamp/driver circuit operable to shift the voltage on said outer Bit Line to a voltage higher than that on said inner Bit Line for at least one logic state stored in said memory cell.

9. The memory of claim 8, wherein said predetermined voltage is ground.

10. The memory of claim 8, wherein said predetermined voltage is equal to one half of the full supply voltage.

11. The memory of claim 8, wherein said outer Bit Line is precharged to a predetermined voltage.

12. The memory of claim 11, wherein the difference between the voltage on said inner Bit Line and the voltage to which said outer Bit Line is driven by said Bit Line preamp/driver circuit is substantially equal to the voltage to which said outer Bit Line is precharged to.

13. A method for accessing data stored in one of a plurality of single transistor memory cells, each memory cell having a memory capacitor for storing a logic "0" or a logic "1" voltage, comprising the steps of:

providing an inner Bit Line;

accessing one of the single transistor memory cells and connecting the associated memory capacitor to the inner Bit Line such that the memory capacitor can transfer charge to and from the inner Bit Line;

providing an outer Bit Line;

driving the outer Bit Line from a source different than the inner Bit Line as the memory cell is accessed during the step of accessing the memory cell, such that the outer Bit Line is not directly coupled to the inner Bit Line, the outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell; and

sensing the logic state on the outer Bit Line during a step of restoring, and driving the voltage on the outer Bit Line to a full logic voltage or to a ground voltage, respectively, during a Restore operation, and substantially concurrently driving the inner Bit Line to the same voltage that is on the outer Bit Line.

14. The method of claim 13, and further comprising distinguishing between a logic "0" and a logic "1" voltage on the outer Bit Line and driving the outer Bit Line to a substantially amplified voltage in response to the logic states determined to be on the outer Bit Line.

15. The method of claim 13, wherein the step of restoring comprises:

providing a cross-coupled latch having first and second sense nodes;

connecting one of the sense nodes to a reference voltage;

connecting the other sense node to the outer Bit Line;

determining whether the voltage on the other sense node is greater than or less than the reference voltage;

driving the sense node connected to the outer Bit Line to a full logic voltage when the voltage on the outer Bit Line is greater than the reference voltage and to a ground voltage when the voltage on the outer Bit Line is lower than the reference voltage, the reference voltage having a value disposed between that existing on the outer Bit Line, substantially midway between a logic "0" and a logic "1" voltage;

selectively connecting the outer Bit Line to the inner Bit Line to drive the inner Bit Line from the outer Bit Line in response to a restore control signal; and

generating the restore control signal to activate the step of selectively connecting during a restore operation after the step of accessing.

16. The method of claim 13, and further comprising:

providing a Data Line separate from the outer Bit Line and having either a logic "1" or a logic "0" voltage disposed thereon;

interfacing the Data Line with the inner Bit Line such that the Data Line is driven from a source other than the outer Bit Line or the inner Bit Line;

controlling the step of interfacing with the voltage on the inner Bit Line such that the logic voltage on the Data Line corresponds to the logic voltage on the inner Bit Line; and

distinguishing between a logic "0" and a logic "1" voltage on the Data Line and convening the voltage on the Data Line to either a full circuit voltage or to a ground voltage in response to the logic state determined to be on the Data Line.

17. The method of claim 16 wherein the step of interfacing comprises:

providing a depletion source follower transistor having a gate and a source/drain path, the source/drain path connected on one side to a supply voltage and other than the inner or outer Bit Lines;

controlling the gate of the source follower with a voltage corresponding to the voltage on the inner Bit Line; and

driving a current source and the Data Line with the other side of the source/drain path of the source follower transistor.

18. The method of claim 13, and further comprising:

providing a Data Line separate from the inner and outer Bit Lines and having a logic "1" or a logic "0" voltage disposed thereon;

interfacing the Data Line with the outer Bit Line such that the Data Line is driven from a source other than the inner Bit Line or the outer Bit Line; and

controlling the step of interfacing with the voltage on the outer Bit Line such that the logic voltage on the Data Line corresponds to the logic voltage on the outer Bit Line;

distinguishing between a logic "0" and a logic "1" voltage on the Data Line and converting the voltage on the Data Line to either a full circuit voltage or to a ground voltage in response to the logic state determined to be on the Data Line.

19. The method of claim 18 wherein the step of interfacing comprises:

providing a depletion source follower transistor having a gate and a source/drain path, the source/drain path connected on one side to a supply voltage other than the outer or inner Bit Lines;

controlling the gate of the source follower with the voltage on the outer bit line; and

driving a current source and the Data Line with the other side of the source/drain path of the source follower transistor.

20. A method for accessing data stored in one of a plurality of single transistor memory cells, each memory cell having a memory capacitor for storing a logic "0" or a logic "1" voltage, comprising the steps of:

providing an inner Bit Line;

accessing one of the single transistor memory cells and connecting the associated memory capacitor to the inner Bit Line such that the memory capacitor can transfer charge to and from the inner Bit Line;

providing an outer Bit Line;

driving the outer Bit Line from a source different than the inner Bit Line as the memory cell is accessed during the step of accessing the memory cell, such that the outer Bit Line is not directly coupled to the inner Bit Line, the outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell; and

precharging the inner Bit Line to a predetermined voltage, wherein the step of driving the outer Bit Line from a source different from the inner Bit Line comprises shifting the voltage on the outer Bit Line to a voltage higher than that on the inner Bit Line for at least one logic state on the memory cell.

21. The method of claim 20, wherein the step of precharging is operable to precharge the inner Bit Line to substantially ground.

22. The method of claim 20, wherein the step of precharging is operable to precharge the inner Bit Line to a voltage of substantially one half of the full circuit potential.

23. The method of claim 20, and further comprising precharging the outer Bit Line to a predetermined precharge voltage.

24. The method of claim 23, wherein the difference between the voltage to which the outer Bit Line is driven during the step of accessing and the voltage the inner Bit Line for the highest logic potential thereon is substantially equal to the voltage to which the outer Bit Line is precharged.

25. The method of claim 13 wherein the step of driving the outer Bit Line comprises:

providing a depletion device having a negative threshold and connecting the gate thereof to the inner Bit Line;

connecting one side of the source/drain path of the depletion transistor to the gate of an enhancement transistor;

connecting one side of the source/drain path of the depletion transistor to the gate of an enhancement transistor;

connecting one side of the source/drain path of the enhancement transistor to a source voltage and the other side thereof to the outer Bit Line; and

driving the side of the source/drain path thereof opposite to that connected to the gate of the enhancement transistor with a Read control voltage, activation of the Read control voltage operable to drive the outer Bit Line from the inner Bit Line.

TECHNICAL FIELD OF THE INVENTION

The present invention pertains in general to dynamic random access memories, and more particularly, to a preamp for the Bit Line.

BACKGROUND OF THE INVENTION

Dynamic random access memories came to the forefront of technology in the early 1970's with the advent of the 1-T memory cell. In this type of structure, a memory storage capacitor is provided with a switching element associated therewith to allow connection to a Bit Line. A plurality of these memory cells are arranged in an array of rows and columns. The gates of the switching elements associated with each memory cell are arranged in rows and connected to a common Word Line whereas each of the gates in a given column is operable to selectively connect the associated memory cell to a separate Bit Line. Each of the memory cells has the capacity to store one bit of data as either a logic "1" or a logic "0".

When the data stored in a memory cell is accessed, the capacitor is connected to the associated Bit Line which has a predetermined charge level associated therewith. The connection of this memory cell capacitor to the Bit Line causes a change in the charge stored thereon, due to either addition of charge thereto from the memory capacitor or depletion of charge therefrom by the memory capacitor. A sense amp is typically provided for sensing this change in charge to determine whether the bit stored in the memory cell was a logic "1" or a logic "0". However, as the density of a memory array increases, the number of memory cells per Bit Line increases and, due to the size constraints, the size of the memory cell decreases. Therefore, technology has continuously evolved such that the size and the associated capacity of the memory cell has been reduced, and the relative size of the Bit Line has increased. Therefore, the ratio of the Bit Line capacitance to the memory cell capacitance has increased, thus requiring novel techniques to sense very small charge variations in the capacitance change due to access of a memory cell.

One other aspect that exacerbates the sensing operation is that the Bit Line is typically loaded down with a great deal of capacitive overhead. One major contributor to this overhead is the sense amp itself, since it is typically configured of a cross-coupled sense amp wherein the gate of one of the cross-coupled transistors is directly connected to the Bit Line. The only way to reduce this capacitance is to significantly reduce the size of the transistors involved, but this also effects the speed and other operating parameters.

SUMMARY OF THE INVENTION

The present invention, disclosed and claimed herein, comprises a method and apparatus for accessing one of a plurality of memory cells in a Random Access Memory. A plurality of single transistor memory cells configured in an array are provided, each having a memory capacitor for storing a logic "0" or a logic "1" voltage. An inner Bit Line is provided for access thereof by selected ones of the memory cells. When a memory cell is selected, the voltage on the inner Bit Line is driven to a voltage, depending upon the logic state stored in the memory cell capacitor. An outer Bit Line is provided that is isolated from the inner Bit Line. A Bit Line preamp/driver circuit drives the outer Bit Line from the inner Bit Line such that a source different from the inner Bit Line provides the driving current to the outer Bit Line, such that the voltage on the outer Bit Line is not directly coupled to the inner Bit Line and the inner Bit Line does not specifically couple to the outer Bit Line. The outer Bit Line is driven to either a logic " 1" or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell.

In another aspect of the present invention, a Read circuit is provided for distinguishing between a logic "0" and a logic "1" voltage on the outer Bit Line. This voltage is then converted into a full circuit voltage or to a ground voltage, in response to the logic state determined to be on the outer Bit Line. This voltage is utilized to generate the output data signal.

In a further aspect of the present invention, a restore circuit is provided for interfacing with the outer Bit Line. After the access operation, the restore circuit is operable to sense the logic state on the outer Bit Line and drive the voltage on the outer Bit Line to a full logic voltage or to a ground voltage, respectively, during the Restore operation. The Restore circuit is operable to drive the inner Bit Line to substantially the same voltage on the outer Bit Line. The Restore circuitry is comprised of a cross-coupled latch having first and second sense nodes, with one sense node connected to a reference voltage and the other connected to the outer Bit Line. During a Restore operation, the latch is operable to drive the outer Bit Line to a full logic potential if the voltage on the outer Bit Line is greater than the reference voltage, and to ground if the voltage on the outer Bit Line is less than the reference voltage. A Write device is provided for selectively connecting the outer Bit Line to the inner Bit Line during the Restore operation to drive the inner Bit Line from the outer Bit Line.

In a yet further aspect of the present invention, the Bit Line is precharged to a predetermined voltage with the preamp/driver circuit operable to shift the voltage on the outer Bit Line to a voltage higher than that on the inner Bit Line for at least one logic state stored in the accessed memory cell. In the preferred embodiment, the precharge voltage can be either ground or one half of the full circuit potential. The outer Bit Line is also precharged to a predetermined voltage level, with the difference between the voltage on the inner Bit Line and the voltage to which the outer Bit Line is driven to for the highest voltage on the inner Bit Line substantially equal to the precharge voltage on the outer Bit Line.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIG. 1 illustrates a block diagram of a single Bit Line and associated memory cells connected to the preamp/driver;

FIG. 2 illustrates a schematic diagram of the preamp/driver;

FIG. 3 illustrates a timing diagram of the operation of the preamp/driver of FIG. 2;

FIG. 4 illustrates a schematic diagram of one column of memory cells and associated peripheral circuitry for operation thereof;

FIG. 4a illustrates an alternate embodiment of the column select circuit of FIG. 4;

FIG. 5 illustrates a timing diagram for the array of FIG. 4;

FIG. 6 illustrates an alternate embodiment of the array of FIG. 4 illustrating a read operation that is isolated from the restore operation;

FIGS. 7a-7d illustrate alternate embodiments of the preamp/driver and read circuits; and

FIG. 8 illustrates an alternate embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is illustrated a schematic diagram of one Bit Line, its associated memory cells and the preamp/driver of the present invention. A plurality of memory cells are illustrated, each comprising a memory cell capacitor 10 and a switching transistor 12. These utilize conventional construction as that utilized in typical 1-T memory cells. Each of the transistors 12 and associated memory cell capacitors 10 are associated with a single column and, therefore, have one side of the source/drain path thereof connected to a single Bit Line 14. The gates of the transistors 12 are each connected to separate Word Lines WL.sub.0 through WL.sub.N, each associated with a different row of memory cells in the array. A precharge circuit 16 is provided that is operable to provide a precharge voltage to the Bit Line 14 during the precharge cycle and, during the active cycle, a preamp/driver circuit 18 is provided for interfacing with a Data Line 20.

In operation, the memory cell capacitors 10 are typically isolated from the Bit Lines 14 by turning off the associated switching transistors 12 during the non-active cycle. During the active cycle, a read operation is performed which is typically a destructive operation, i.e., the ability to detect the logic level in the cell is destroyed. Therefore, after a read operation, a restore operation is performed to restore the charge in the memory cell capacitor 10 to a full charge when a logic "1" is stored therein, or to a zero charge when a logic "0" is stored therein. After the restore operation, the system is again cycled into the non-active cycle during which precharge operations are performed.

In the system of FIG. 1, the precharge circuit 16 is operable only during the non-active cycle and, during the active cycle, one of the rows of memory cells is selected by activating the appropriate Word Line. At this time, the Bit Line has the selected memory cell capacitor 10 connected thereto and the charge on the Bit Line 14 is affected. The preamp/driver 18 is then placed in the read mode and the voltage on Bit Line 14 is utilized to "drive" the Data Line 20, it being noted that the preamp/driver 18 provides an isolated driving function that maintains the Bit Line 14 isolated from the Data Line 20 and provides a separate drive to Data Line 20. Therefore, as will be described in more detail hereinbelow, the capacitance of the Data Line and all the associated peripheral circuitry is not connected to the Bit Line 14. By isolating the capacitance of the Data Line 20 from the Bit Line 14, the ratio of the Bit Line capacitance to the memory cell capacitance 10 can be reduced. For example, the Bit Line capacitance associated with 64 memory cells on a Bit Line could be as low as 70 femptofarads (fF) with the memory cell capacitor being approximately 35 fF. In conventional systems, this ratio can be as high as five to one or eight to one. The preamp/driver 18 is controlled by a Read operation during the access operation and, during a later restore time, a Write operation allows writing of data from the Data Line 20 back to the Bit Line 14 and the associated memory cell capacitor 10 through the associated switch 12.

Referring now to FIG. 2, there is illustrated a schematic diagram of the preamp/driver 18. The preamp/driver 18 is comprised of a depletion transistor 22 that has the drain thereof connected to the Read signal (RD) and the source thereof connected to a node 24. The gate of the depletion transistor 22 is connected to the Bit Line 14. The node 24 is connected to the gate of an n-channel enhancement transistor 26, the drain thereof connected to V.sub.CC or lower voltage, and the source thereof connected to the Data Line 20. The write operation is controlled by an n-channel enhancement transistor 28,