 |
Description  |
|
|
FIELD OF THE INVENTION
This invention relates to a novel real time data processing system including two or more data processing nodes or units wherein as data is written to a memory in one mode, it is sensed and reflected to memories in the associated nodes.
BACKGROUND OF THE INVENTION
Such systems are known from U.S. Pat. No. 4,991,079, the content of which is here incorporated by reference and from U.S. Ser. No. 07/403,779, filed Sep. 8, 1989, continuation of Ser. No. 06/880,222 filed Jun. 30, 1986, now abandoned, the
content of which is here incorporated by reference, both of which are commonly owned with the present application. Such systems use two ported memories. Although they are successful in reflecting data among a plurality of nodes, these systems have
limitations which will become more readily apparent from the following description.
SUMMARY OF THE INVENTION
The present invention provides a data processing system characterized by an architecture that provides efficient coupling of multiple processor nodes for real-time applications. This architecture allows data to be shared among different
processing nodes in a distributed computing system via a parallel, high speed real-time linkage between the physical memories of the nodes. It also provides the full advantages of the common memory, but without the non-deterministic access latencies
that are found in most traditional multiprocessor systems with shared memories.
Other and further advantages of the present invention will become readily evident from the following description of a preferred embodiment when considered in conjunction with the appended drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram illustrating a system according to the present invention;
FIG. 2 is a schematic diagram illustrating bus interconnection;
FIG. 3 is a schematic diagram showing details of interfaces and controllers used in the present invention;
FIG. 4 is a schematic diagram showing details of the high speed data interface;
FIG. 5 is a detail block diagram of the HSDI;
FIG. 6 is a diagram of global memory organization;
FIG. 7 is a time chart of memory coupling bus grants, all nodes requesting;
FIG. 8 is a time chart of MC bus grants, random requests;
FIG. 9 is a time chart of MC bus continuous node request sequencing;
FIGS. 10 and 11 shown the MC system control/status register map and ID registers; and
FIG. 12 is a schematic diagram showing details of interfaces and controllers used in a modification of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
Referring to FIG. 1, a processing system is shown that comprises a plurality of nodes, only three of which are shown. Node 1 comprises a main processor 20 interconnected by conventional interfaces with a VME bus 22 serving as an I/O bus and a
local bus 24 which could be a SEL bus. Expansion memory 26 is also interconnected to buses 22 and 24. Bus 22 has coupled to it in conventional fashion a plurality of I/O devices or peripherals; shown for illustration are a high speed data interface 28,
Async devices 30, an Ethernet interface 32 and other user options 34. Both buses 22 and 24 are connected to a novel memory coupling system 40 at ports 42 and 44, respectfully, which in turn is coupled to a memory coupling bus 46 at port 48. Bus 46
serves as a data line to couple directly the memories of the several nodes of the processing system to interface the multiple systems to common data, and to create a distributed high-performance uniform address space environment.
Node 2 comprises, for example, a Concept 32/67 processing unit as manufactured and sold by Encore Computer Corporation, Ft. Lauderdale, Fla. Not all of the details are shown. Node 2 includes a SEL bus 54 to which are coupled I/O 50 and a
processor 52. A dual ported memory 56 has one port connected with the SEL bus 54 and its other port is connected with a read sense control 58 which, in turn, is connected to a write sense control 60 which also connects with SEL bus 54 and memory
coupling bus 46. The structure and operation of Node 2 is explained in detail in U.S. Pat. No. 4,991,079 and U.S. Ser. No. 07/403,779, now abandoned filed Sep. 8, 1989, both of which are here incorporated by reference.
Node 3 can be similar to Node 2 or can be in another form, e.g., a processing unit such as a Concept 32/2000 also made and sold by Encore Computer corporation. Additional nodes as described, up to eight in number, can also be connected to memory
coupling bus 46 so that the memories of the nodes are intercoupled by the bus 46 data link to substantially simultaneously update the memories without intervention of the processors (CPU) of the processing units as nodes.
In a specific example of the foregoing, Node 1 is a Model 91 of the Encore 91.TM. series which uses an open systems' architecture for time-critical applications. This symmetric multiprocessor system uses industry-standard hardware platforms,
I/O interfaces, and OS and application software to achieve deterministic real-time capability.
The hardware architecture is based on the Motorola high-performance 88100 25 MHz 32-bit RISC processor. The single-board computer, implemented in the VME 9U form factor, includes two or four 88100 processors with supporting cache memory, 16 or
64 MB of onboard memory, two SCSI ports, an Ethernet port, four synchronous ports, a real-time clock, eight timers (seven of which are programmable), eight directly connected interrupt pairs (in and out), a high-speed Local bus and an enhanced VME bus,
VME-64. This hardware architecture provides an independent memory bus from the VME-64 I/O bus, to ensure a high-performance and deterministic system response regardless of I/O load. The seven programmable timers operate at 4 MHz and are divisible by 2
to 256 to meet a wide range of timing requirements. In addition to the normal system level interrupts, eight directly connected interrupts provide fast system response to external events. Memory may be expanded to as much as 576 MB with optional
external memory boards.
The operating system is Encore's real-time UNIX providing powerful industry-standard software capabilities while handling symmetric multiprocessing. For even more demanding real-time performance, the software architecture can provide guest
real-time kernels that execute independently of the UNIX OS. Various implementations or compliers are available including C, FORTRAN, and Ada. Standard UNIX tools are available for software development. A full complement of CASE tools is also
available including Parasight.TM. for nonintrusive monitoring and debugging of parallel real-time application software. The Encore 91 conforms to IEEE POSIX.TM. 1003.1 and the Binary Compatibility Standard (BCS) of the 88open Consortium, Ltd.
The Encore 91 incorporates as a central processor a single-board CPU comprised of two (dual) or four (quad) tightly coupled 32-bit Motorola 25 MHz 88100 RISC processors. The processor board supports a symmetric multiprocessing arrangement
whereby all processors have equal access to system resources. The 88100 RISC processor provides 51 instructions, most of which execute in 1 clock cycle. The instructions that exceed 1 clock cycle, such as memory reference and floating point, execute in
a pipeline fashion which allows other instructions to execute in parallel.
The CPU supports seven data types including single and double precision IEEE-754 floating point.
The Motorola 88000 Family has two 4 GB dual-mapped logical address spaces. One 4 GB area is user space and the other is operating system space. This segregates user application code from the operating system environment.
The memory resident on the processor board is 16 MB or 64 MB utilizing 1 megabit and 4 megabit DRAM technology, respectively. All processors have uniform access to memory.
Cache coherency is maintained using Motorola's 88200 cache/memory management units (CMMUs) that are tightly coupled with each processor. The CMMUs monitor the Local bus for write cycles to ensure that cache memory is updated with new information
when data in the main memory is changed. A total of 128 KB cache memory is provided on the system equally shared among the processors; half is used for data, and half is used for instructions.
Expansion memory cards can be added in 16 MB, 64 MB or 256 MB increments to a maximum total capacity of 576 MB. Multiple expansion memory cards permit interboard interleaved access to memory between boards of the same capacity. The interleaving
speeds up access time to memory, thereby boosting throughput of the overall system. In addition, expansion memory is dual ported to support simultaneous CPU Local bus and VME I/O accesses to main memory without contention.
Node 1 utilizes high-speed internal and external buses. The Local bus supports communication among all elements on the processor board and expansion memory at a transfer rate of 100 MB per second. This allows communication to external memory
and coupling system 40 independent of VME I/O traffic, thereby increasing determinism of processor memory traffic and overall throughput of the system.
Two principal industry-standard external buses are implemented: the SCSI bus and the VME bus. Dual SCSI buses are used as peripheral buses for disks and tapes. One SCSI bus is single ended for in-cabinet peripherals; the other is a different
bus for longer cabling requirements. Both buses can support asynchronous and synchronous devices. The VME-64 bus 22 allows block mode transfers at sustained speeds in excess of 55 MB per second.
HSD interface 28 is provided for high-speed data input and output. The HSD is typically used to interconnect two systems back-to-back or to act as an interface to digital instrumentation, graphical devices or customer-designed devices. The HSD
provides a 32-bit wide, half-duplex, point-to-point connection. HSD can be inserted into any VME slot in the card cage; up to five may be added.
The memory coupling system interface 40 is used to create larger distributed heterogenous systems consisting of multiple Encore 90 Family and CONCEPT/32 systems. Up to eight systems can be interconnected using a single 26 MB per second memory
coupling bus 46.
System 40 is triported for maximum interconnectability and high performance. One port connects to the Local bus 24, another to the VME bus 22 and the third to the Memory coupling bus 46. The system 40 card can be plugged into any available
slot, although a Local bus connection provides maximum performance. The system 40 can have 4 or 16 MB storage capacity.
The processor board includes four asynchronous ports. Two are reserved for use by the operator's console and a remote diagnostic port. The principal communication connection is over the standard IEEE-802.3 Ethernet port included on the
processor board. User terminals interface to Node 1 using an Encore-supplied Annex.TM. terminal server that resides on the Ethernet local area network. Terminal users communicate over the network using standard TCP/IP protocols and applications.
Node 1 may include industry-standard Network File System (NFS.TM.). This allows access to files on remote systems. Node 1 can act as an NFS server (to provide files to others) or as a client (to use files that reside on other systems). NFS
utilizes the standard Ethernet port.
Node 1 adopts a standardized approach to peripherals by using industry-standard 5-1/4-inch form factor peripherals that mount in a SCSI chassis. These include 300 MB, 500 MB, and 1.0 GB disks, and 1/4-inch cartridge tape drive. The tape drive
uses the industry-defined QIC tape formats. Specifically QIC-320, -150 and -120 formats can be written and read. Tapes recorded to the older QIC-24 standard can be read. Also available is an 8 mm cartridge tape that store 2.3 GB of data. SCSI
chassis-mounted peripherals can be removed from the system without dropping main processor power. In the case of disks, this feature allows removal of private data for secure storage.
As an alternative for cartridge tape storage, a standard nine-track tridensity tape transport can be used. This is a 125 ips transport with front loading access. For cabinet configurations, the tape transport may be mounted in the processor
cabinet or in a peripheral cabinet. For tower configurations, a tabletop tape transport is available.
There are two choices for an operator's console. The entry level device utilizes a low functionality terminal on one of the asynchronous ports on the processor board. Control of multiple networked 91 Series systems from one device can be
obtained using a personal computer style of terminal connected to the Ethernet port.
A 12-page-per-minute laser printer can be included as a peripheral.
Referring now more particularly to coupling system 40 and bus 46, reference is made to FIGS. 2 and 3. Memory Coupling System 40 and bus 46 architecture provides efficient coupling of multiple processor nodes for time-critical applications. This
architecture allows the sharing of data among different processing nodes in a distributed computing system over a parallel, high-speed real-time linkage between the physical memories of the nodes. It also provides the full advantages of common memory,
but without the nondeterministic access latencies found in most traditional multiprocessor systems with shared memory.
The Memory Coupling System 40 is incorporated onto a single board. As a specific example, the board can be a 9U form factor VME board incorporating 4 or 16 Mbytes of on-board memory. The board normally occupies a single Local Bus slot in the
VME chassis. If daisy chaining is required (use of alternate daisy chain cables), a second slot (Local Bus slot or VME slot) is required for the cable adapter. The complete hardware package includes four cables for connecting the boards. The Memory
Coupling bus interface is capable of supporting up to eight nodes. Shielded cables for connections between nodes, such as Encore 91 Series systems, would extend for up to 120 feet.
The MCS 40 board is tri-ported-one port each 44, 42 and 48, respectively, to the Extended Local Bus 24, the VME-64 bus 22 and the Memory Coupling bus 46. The MCS real-time link is the Memory Coupling bus 46 (MC bus). The MC bus contains 28-bit
address and 32-bit data paths with data and address parity and control signals. The MCS board 40 provides the necessary logic to attach the Encore 91 Series node to the MC bus 46. The board contains either 4 or 16 Mbytes of tri-ported DRAM, which acts
as global memory for all nodes in the MCS configuration. The on-board memory eliminates adding expansion memory to minimally configured systems.
The system allows up to eight nodes to maintain a local copy of a common memory area with the data in this area common to all nodes connected by the MC bus 46. Each node processor has unrestricted access to its common memory area since the copy
is maintained in separate, physical memory in each node. Memory write operations to selected or predetermined memory regions or addresses are sensed by the MC bus write controller and reflected to the separate physical memories at each node over the MC
bus 46.
This architecture provides a high-speed, low-latency memory interconnection between the Encore 91 Series node and other Encore 90 Family systems equipped with an MCS; Encore CONCEPT/32 systems equipped with an MCS; and Encore CONCEPT 32/2000
systems equipped with Reflective Memory System (RMS), operating in MCS mode.
FIG. 1 illustrates the memory coupling construction between three such Encore systems, namely, Node 1 is an Encore 91 Series system, Node 2 is an Encore CONCEPT/32 system and Node 3 can be an Encore CONCEPT 32/2000 system all having their ported
memories connected to bus 46 via write/read sensors.
The Memory Coupling System 40 incorporates the following subsystems, see FIGS. 2 and 3.
A local bus interface 60 or local bus slave interface can allow a processor 20 on the local bus 24 to transfer data to the MC bus 46 or to access the MCS on-board global memory 62. Since the local bus 24 is parity-protected, this interface
checks parity on both the address and data lines.
A VMEbus interface 64 or VME slave interface can be a 32-bit interface with extensions to provide a 64-bit-wide data path during block data transfers. This interface allows a processor on the VMEbus to transfer data to the MC bus 46 or to access
the MCS on-board global memory 62. Since the VMEbus 22 does not support parity, the MCS 40 generates parity before storing the data in its on-board RAM.
A Memory Coupling bus interface 66 can perform all MC bus 46 arbitration and control. The MC arbitration logic is active only on the node selected as the arbiter node. In this case, the MCS board 40 controls the MC bus 46 arbitration for all
nodes on the same MC bus. The control logic divides the MC bus time equally among requesting nodes. Assertion of a node's request line indicates that the node needs the MC bus 46. For diagnostic purposes, the MC interface 66 can provide an external
loopback capability.
The MC bus interface 46 contains separate controllers for reading from and writing to the MC bus 66. The MC bus write controller 70 monitors the memory write transaction address and the transmit translation RAM (to offset the transmit address on
the MC bus 46). The write controller 70 generates parity for both address and data. The MC bus read controller 72 monitors traffic on the MC bus and receives translation RAM to offset the receive address. The read controller 72 checks parity on the
address but does not check data parity.
A global memory and control logic 76 including on-board global memory is available in 4- and 16-Mbytes configurations and is accessible through all three bus ports 42, 44 and 48 to the local bus 24, VMEbus 22 and MC bus 46. The control logic
arbitrates the requests by each port. The control logic registers provide control and status information for the MCS board 40 and each of the bus interfaces. These registers are accessible through VME short address (A16) space.
The Local Bus interface 60 can provide the buffer between MCS global memory 62 and the Local Bus 24. The Local Bus interface 62 accepts for example, the following data type transfers: D8 (byte), D16 (word), and D32(longword). The interface also
accepts memory bus (M Bus) read and write (32-bit) burst transfers. Parity is checked on both addresses and data.
The MCS 40 can provide only the VMEbus slave functionality, allowing VMEbus masters to directly access the onboard memory 62. The VMEbus slave interface 64 accepts, for example, the following data type transfers in both standard and extended
modes of transfer: D08(O) (odd byte only), D08(EO):BLT (even and odd byte), D16:BLT, D32:BLT, and D64:BLT. The interface does not support read-modify-write (RMW) data transfer cycles.
The interface 64 can accept VMEbus cycles with 16-bit (short), 24-bit (standard), and 32-bit (extended) addresses. Short addresses access the control/status and configuration registers; standard and extended addresses access the MCS on-board
memory 62.
In the example being described, the MCS hardware 40 can use address modifier codes to identify transfer types and address lengths. The MCS 40 recognizes for example, the following address modifier codes:
______________________________________ Short address (A16) 29, 2D Standard address (A24) 39, 3B, 3D, 3F Extended address (A32) 09, 0B, 0D, 0F VME-64 block transfer mode (VME-64 BLT) 19, 1B, 1D, 1F ______________________________________
The MCS board, in the example, can support both VME32 and VME64 block transfer modes. Block transfer cycles are useful if a VMEbus master accesses several global memory locations in ascending order. The VMEbus master provides a single address,
and then accesses data in that location and subsequent higher locations without providing any additional addresses.
The VMEbus slave interface 64 can accept for example, read/write transfers of D8 (byte), D16 (word), and D32 (longword) data types in VME32 block mode. The interface also accepts read/write transfers of 64-bit data in VME64 block mode in
accordance with the Performance Technologies, Inc., Specification of VME64. If the VMEbus master crosses a 256-byte boundary for either type of transfer, the MCS board 40 generates for example, a BERR response.
Since the VMEbus has separate address and data lines, the VMEbus master can broadcast the address for the next cycle while the data transfer for the previous cycle is still in progress. This is called address pipelining. The MCS VMEbus slave
interface 64 employs, for example, address pipelining in accordance with the VMEbus Specification, Revision C.1 permission 2.8.
The MCS board 40 can generate an interrupt on any one of the seven VME bus interrupt request lines. The MCS VMEbus interrupter can monitor the low-order address lines and the IACKIN/IACKOUT daisy chain to determine if its interrupt is being
acknowledged. The interrupter can respond to 16-bit interrupt acknowledge cycles by providing a status/ID signal on the data lines. The mode of acknowledge that can be employed by the MCS board is release on acknowledge (ROAK)-the interrupt request
line (IRQn) is released when the interrupt handler generates an interrupt acknowledge cycle.
The MC bus interface 66 can provide the buffer between MCS global memory 62 and the MC bus 46. The MC bus interface 66 can include two controllers 70 and 72 that perform read and write functions for the interface with each controller maintaining
a separate FIFO buffer.
The MC write controller 70 detects global memory write transfers in the reflected memory address range, maps transmit addresses, and buffers memory coupling transfers for transmissions over the MC bus 46. The MC read controller 72 recognizes
memory coupling transfers in the global memory address range, maps receive addresses, buffers received memory coupling transfers, and provides status monitoring and notifications for the MCS board 40.
The MC write controller 70 and MC read controller 72 can each consist of 2048 windows with 8-Kbyte granularity. Each window can contain a translation address to modify the upper bits of an incoming address and a single bit to indicate if a
window is open or closed. The controllers can use the upper bits of a memory write or read address to determine if a transmit (write) or receive (read) window is open. If the window is open, the controller replaces the upper address bits with the
translated address.
The MC read controller 72 can generate a VMEbus interrupt and light a status LED if one of these conditions occurs: a parity error on one or more of the MC bus address bytes, an MC bus address reference to a nonexistent memory location, or a
write transfer creating a FIFO buffer overrun condition.
The MC write controller 70 can maintain a transmit FIFO buffer; the MC read controller 72 maintain a receive FIFO buffer. The transmit FIFO buffer can be 64 rows deep by 64 bits wide, with each row storing 32 data bits, 24 address bits, 7 parity
bits, and a byte transfer bit. The receive FIFO buffer can be 64 rows deep by 72 bits wide, with each row storing 32 data bits, 28 address bits, 8 parity bits, and a byte transfer bit.
The transmit FIFO buffer can hold the data and memory addresses from the VMEbus 22 or Local Bus 24 until they can be transferred onto the MC bus 46. The MC write controller 70 can generate parity for each byte of address and data before placing
it in the FIFO buffer. The FIFO buffer can prevent further writes to the reflected memory region whenever the number of FIFO buffer writes is 56 more than the number of FIFO buffer reads (an almost full condition). The FIFO buffer can prevent further
writes by either not acknowledging the transfer (no DTACK signal) on the VMEbus 22 or generating a wait status on the Local Bus.
The receive FIFO buffer can hold the data and memory addresses from the MC bus 46 before they can be transferred into the global memory. Each address and data byte on the MC bus 46 can have a parity bit. The MC read controller 72 can check the
address parity before placing the address in the FIFO buffer and store the data in the FIFO buffer without checking its parity bit. If the MC read controller 72 detects an address parity error, it can inhibit the transfer of both the address and data to
the FIFO buffer. The FIFO buffer can prevent further MC bus writes to the memory coupling region whenever the number of FIFO buffer writes is 56 more than the number of FIFO Buffer reads. The FIFO buffer can prevent further transfers on the MC bus 46
by driving the MC bus busy signal, thus preventing a FIFO buffer overflow.
The MCS board 40 can contain 4 Mbytes or 16 Mbytes of parity-protected global memory with separate ports to the Local Bus, VMEbus and MC bus. This memory may be divided into three regions: private memory, transmit reflected memory, and receive
reflected memory. Data written to the transmit reflected memory region can be or is reflected on the MC bus 46 thus forming a single common memory space for all processors on the MC bus 46 (though it remains a separate physical memory). Any data
received by the MC port 42 is stored in the receive reflected memory region. The global memory base addresses for the Local Bus and VME bus address spaces can be software-programmable; the global memory base address of MC bus address space is preferably
always 0.
For example, the 4-Mbyte MCS board 40 can use 1-Mbit 80-nanosecond DRAMs arranged as 256K.times.4; the 16-Mbyte MCS board 40 can use 4-Mbit, 80-nanosecond DRAMs arranged as 1M.times.4. The DRAM is divided into two banks with each 2-Mbyte bank
providing a 64-bit-wide data path. This allows the storage of 64-bit data in one cycle during the VME64 block transfer mode. Each bank also has 8 bits of parity information, one of each byte, stored separately in a 1M.times.1 DRAM. Using page mode
DRAMs reduces the read and write cycle times for the second through nth accesses during VMEbus block transfer and Local Bus burst transfer modes.
The MCS board 40 can use a prioritized arbitration scheme to resolve simultaneous read/write accesses of memory. During a burst transfer, only the port performing the transfer is allowed to access the global memory-the MCS board 40 does not
grant access to either of the other two ports.
Referring now to FIT. 3 in detail, VMEbus 22 is connected via port 42 with VMEbus interface 64. Data, control and address transceivers including registers 80 monitor bus 22. Parity generator and check 82 is connected to the data portion of
registers 80, the data output of which is connected to Data XBAR 84 in the shared memory/multiplexer 76. The control section or registers 80 is connected to the VME address decoding and arbiter 86. The address section of registers 80 is connected in
common to VME short address decoder 88 and BLT counter 90 and also in common to MUX 92 in MCS write controller 70 and VME address decoding 86 and to shared memory address MUX 94, the output of which is connected to the Memory 96. Data XBAR 84 also is
connected with Memory 96. VME base address 98 is connected to VME address decoding 86 to provide address range control.
Memory 96 is connected to Byte Alignment 100 in controller 70 which in turn is connected to Transmit Data FIFO 102. MUX 92 connects with Transmit Address FIFO 104 via parity generator 106 and Transmit Window 108 is connected with MUX 92 and in
turn connects with Transmit control 110, parity generator 106 and Transmit Address FIFO 104. Control 110 is also connected to FIFO 104. FIFOs 102 and 104 and control 110 are connected, respectively with the appropriate sections of output registers 112
in the MC bus interface 66 and output via port 48 to MC bus 46.
Local bus 24 is connected via port 44 with registers 120, having address, control and data sections, in interface 60. The address section is connected to Parity checker 122 and the local bus address decoding section of Arbiter 86. The control
section is also connected to Arbiter 86 to which is also connected local bus address 124, to provide address range control. The data section of registers 120 is connected to Data XBar 84 via Parity checker 126. Shared memory address MUX 94 is connected
in common with the address section of registers 120 and the local bus address decoding of Arbiter 86.
Read controller 72 takes as its input the output of MC bus 46 monitoring registers 112. The address section of registers 112 are connected in common to Receive Window 130, Receive address FIFO 132 and Parity checker 134. The data section of
registers 112 are connected to Byte Alignment 136 which in turn connects with Receive Data FIFO 138. Receive Window 130 connects with Receive Control 140 which connects with Interrupt Status Reg. 142 and Arbiter 86. The control section of registers
112 connects with Receive Control 140. Receive window 130 connects with Receive address FIFO 132. The operation of the apparatus has been described above.
From the above it will be evident that I/O can feed via the VMEbus 22 and port 42 directly to the memory on the Memory Coupling system board 40 and then out via port 48 onto the Memory Coupling bus 46 to any node coupled to bus 46. This allows
data, e.g. a data base on disc or network or other communication devices, to be reflected into a preselected memory in any node. The VMEbus 22, as explained, is formatted by address (memory mapped) and therefore, I/O input on Node 1 can be addressed to
either processor 20 or Memory Coupling System 40. Since each system 40 can have its global memory or receive window 130 (see FIG. 3) initialized with an address range which can be set by processor 20, I/O input can be directed to any node X. Port 44 is
used to input and output data from system 40.
Referring now to FIG. 4, a known high speed data interface 28 is coupled on VMEbus 22 as described. Data on VMEbus 22 is passed via HSD 28 to a similar HSD 200 coupled on another VMEbus or SEL bus 202 to transfer data from one system, as
portrayed in FIG. 1 to another such system. Coupled to bus 202 are a processor 204, I/O controllers 206 and other peripheral devices, representatively indicated by block 208.
HSD 28 can be a 32-bit parallel High-Speed Data interface (HSD) and acts as a VME-based high-performance DMA interface. The HSD 28 connects two systems back-to-back or acts as an interface to digital instrumentation, graphical devices, or I/O
front-end devices. The HSD 28 can provide a 32-bit-wide, half-duplex, point-to-point connection.
A typical complete HSD 28 package can include a 6U form factor VME board on a 9U VME adapter card and the appropriate software drivers. The HSD board would occupy a single Local Bus or VME-only slot in the VME card cage. The HSD can use two
50-pin connectors, one each for data and control signals, with the cables exiting from the front of the board. The HSD hardware adheres to the VME Specification Rev. C. Extender cables, available in lengths of 50 and 100 feet, can be used if desired.
The HSD 28 can provide External Function (EF) and Inter Bus Link (IBL) modes of operation with software controlling the switching of modes. Typical IBL connections would include two or more Encore 91 Series or CONCEPT/32 systems (see FIG. 4). A
single Encore 91 Series system can concurrently support up to five HSD devices using available slots in the VME card cage.
For VMEbus-to-VMEbus links, a processor must support 32-bit transfers into short I/O address space. While the Encore 91 Series MC88100 processors support this requirement, some processors may not.
Referring to FIG. 5, the HSD 28 incorporates a DMA controller 210, a bus interrupter 212, and a VME bus address modifiers 214, each of which is programmable. The HSD 28 uses the VME short I/O address space for on-board register addressing.
The output of the bus interrupter 212 provides the usual HSD control signals and interrupter 212 is coupled to the address modifiers 214 and Controller 210. The HSD data is output from Controller 210 with address modification as required to be
compatible with the other system's HSD.
The HSDI is memory mapped, that is, address mapped and not I/O mapped. It requires specific address commands from the processor to operate or to set a range of addresses comparator. The HSDI operates in different modes; it constitutes a 32-bit
interface that passes data plus address or just data passing or taken off in parallel. It operates in different modes as set by the processor.
The following is a further elaboration of the system of the present invention with special emphasis on the functional aspects. As mentioned, board 40 contains four megabytes expandable to 16 MB of parity protected global memory. This global
memory has three ports: local bus port 44, VMEbus port 42 and MC Bus port 48. This allows all of the processors direct access to global memory. The base address of global memory on local and VMEbus address space is programmable via software. The base
address of memory on MC Bus address space is always zero. The memory may be divided into three regions, private memory, transmit reflected memory and receive reflected memory. Data written to transmit reflected memory region is reflected on MC bus,
thus forming one common memory space to all the CPU's even though it is actually a separate physical memory. Any data received by the MC port is stored into receive reflected memory region.
The board 40 can use one megabit (256K.times.4) 80 ns dynamic RAM to implement 4 MBytes of global memory. The board 40 design can allow the global memory to be expanded to 16 MBytes by using 1M.times.4 DRAMs. The DRAM is divided into two banks,
each bank consisting of 2 Mbytes of memory. Each bank has 64-bits wide data path. This allows the 64 bits of data to be stored into the memory in one cycle during VME64 block transfer mode. Each bank also has 8 bits of parity information, one for each
byte. The parity bit is stored separately on 1M.times.1 DRAM. Memory organization is shown in FIG. 6.
By using page mode DRAMs, the read and write cycle times for the second through nth are reduced during VMEbus block transfer and Local bus burst transfer mode.
Since global memory is tri-ported, the system 40 can use a prioritized arbitration scheme to resolve the simultaneous read/write access of the memory. In the selected priority scheme the VME bus 22 would be assigned the lowest priority. The
local and MC bus priority are dynamic. The local bus 24 would have the higher priority than MC bus 46 for as long as the MC bus receive FIFO's are less than half full, but whenever the MC bus receive FIFO's are half or more than half full the MC bus
would have higher priority than the local bus.
During burst transfer the global memory accesses are not granted to the other two ports until the burst transfer requirement of the port currently accessing global memory is satisfied.
MC write controller 70 functions include:
Detection of global memory write transfers in the reflected memory address range;
Mapping of transmit address;
Buffering of reflected memory transfer for transmission over the MC bus 46.
The transmit buffering FIFO 102, 104 provides buffering of data a | | |
