A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.

A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an amorphous semiconductor thin film which are separated from each other by a gate insulating film, heating the gate electrode by subjecting it to light rays, and applying a laser beam to the amorphous semiconductor thin film so that the portion of the semiconductor thin film adjacent the metallic gate electrode is heated by both the laser beam and the heat of the gate electrode to cause a crystallization of a portion of the amorphous thin film and then processing the remaining amorphous portions of the thin film to form the transistor structure.

A large-area electronic device, such as an AMLCD, has switching TFTs (T.sub.p) in a matrix and circuit TFTs (T.sub.s) in a peripheral drive circuit. Both the TFTs (T.sub.p, T.sub.s) comprise a field-relief region (130) which has a lower doping concentration (N-) than their drain region (113) and which is present between their channel region (111) and the drain region (113). This field-relief region (130), at least over most of its length, overlaps with the gate (121) in the circuit TFTs (T.sub.s) so as to reduce series resistance in the field-relief region (130) by conductivity modulation with the gate (121). However, the drain region (113) in the switching TFTs (T.sub.p) is offset from overlap with their gate (121) by at least most of the length of their field-relief region (130). This field-relief offset permits the switching TFTs (T.sub.p) to have a lower leakage current than the circuit TFTs (T.sub.s).

On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions are included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.

A process of fabricating a thin film semiconductor device includes the steps of: forming a semiconducting thin film on an insulating substrate; annealing the semiconducting thin film by irradiating a laser beam thereon, thereby crystallizing the semiconducting thin film; and integratedly forming thin film transistors, each including the semiconducting thin film as an active layer, with a specific arrangement pitch. In the laser annealing step, a pulsed laser beam formed in a band-shape is intermittently irradiated onto the insulating substrate and it is simultaneously moved relative to the insulating substrate in the lateral direction with a specific movement pitch to form partially overlapping regions irradiated with the laser beam between the irradiated regions. In this case, the movement pitch of the laser beam is set at a value equal to an arrangement pitch of the thin film transistors or at a value larger by a factor of an integer than the arrangement pitch, and the insulating substrate is previously positioned such that any one of the boundaries of the partially overlapped regions irradiated with the laser beam is not overlapped on a channel region of each thin film transistor.