Memory device - Patent Review 5477486

Claims

We claim:

1. A memory device formed on an IC chip, comprising:

dynamic random access memory means for effecting data read write operations, and having input means, output means, and a plurality of storage locations for storing data;

first and second data terminals, said terminals being formed on the IC chip to receive data from an external side of the IC chip, said first data terminal being to be connected to data bus, and said second data terminal being to be connected to lines other than said data bus; and

control means having an output connected to said input means of said dynamic random access memory means, a first data input connected to said first data terminal to receive first data, a second input connected to receive second data read from a selected part of said storage locations via said output means of said dynamic random access memory means, a third data input connected to said second data terminal to receive a function mode signal, and operation means for executing operations between said first data provided from said first data input and said second data provided from said second input, said operation means including function setting means responsive to said function mode signal for setting a function indicated by said function mode signal prior to receipt of said first data, wherein said second data is read out of said selected part of said storage locations, the operation corresponding to the function set by said function setting means is executed for said first and second data, and the result of said execution is written into said selected part of said storage locations via said input means of said dynamic random access memory means during one memory cycle of said dynamic random access memory means.

2. A memory device according to claim 1, wherein said operations executed by said operation means are logic operations between said first data and said second data.

3. A memory device according to claim 1, wherein said operations executed by said operation means are arithmetic operations between said first data and said second data.

4. A memory device according to claim 2, wherein one of said logic operations is an operation to pass said first data as said result to said input means of said dynamic random access memory means.

5. A memory device according to claim 1, wherein said dynamic random access memory means is used for storing graphic data as the data.

6. A memory device with operation function, formed on one chip as an integrated device, comprising:

dynamic random access memory means for storing data;

first and second data terminals, said terminals being formed on the chip in order to receive data from an external side of the integrated device, said first data terminal being to be connected to data bus, and said second data terminal to be connected to lines other than said data bus; and

means for executing an operation between data provided through said first data terminal and data read from said dynamic random access memory means, the result of said operation being stored in said dynamic random access memory means, including function setting means responsive to a function mode signal provided through said second data terminal for setting a function indicated by said function mode signal prior to receipt of data through said first data terminal, whereby the operation of said executing means is preset in accordance with the function set by said function setting means prior to receipt of said data through said first data terminal, and wherein the reading out of data from said dynamic random access memory means, the execution of said operation on said data by said execution means and the storing of the result of the execution is effected during one memory cycle of said random access memory means.

7. A memory device according to claim 6, wherein said operations executed by said execution means are logic operations between said data provided through said first data terminal and said data read from said dynamic random access memory means.

8. A memory device according to claim 6, wherein said operations executed by said execution means are arithmetic operations between said data provided through said first data terminal and said data read from said dynamic access memory means.

9. A memory device according to claim 6, wherein one of said operations executed by said executing means is an operation to pass said data provided through said first data terminal as said result to said dynamic random access memory means.

10. A memory device according to claim 6, wherein said dynamic random access memory means stores graphic data as the data.

11. A memory device formed on an IC chip, comprising:

dynamic random access memory means for effecting data read and write operations, and having input means, output means, and a plurality of storage locations for storing data;

first and second data terminals, said terminals being formed on the IC chip to receive data from an external side of the IC chip, said first data terminal being to be connected to data bus, and said second data terminal being to be connected to address bus; and

control means having an output connected to said input means of said dynamic random access memory means, a first data input connected to said first data terminal to receive first data, a second input connected to receive second data read from a selected part of said storage locations via said output means of said dynamic random access memory means, a third data input connected to said second data terminal to receive a function mode signal, and operation means for executing operations between said first data provided from said first data input and said second data provided from said second input, said operation means including function setting means responsive to said function mode signal for setting a function indicated by said function mode signal prior to receipt of said first data, wherein said second data is read out of said selected part of said storage locations, the operation corresponding to the function set by said function setting means is executed for said first and second data, and the result of said execution is written into said selected part of said storage locations via said input means of said dynamic random access memory means during one memory cycle of said dynamic random access memory means.

12. A memory device according to claim 11, wherein said operations executed by said operation means are logic operations between said first data and said second data.

13. A memory device according to claim 11, wherein said operations executed by said operation means are arithmetic operations between said first data and said second data.

14. A memory device according to claim 12, wherein one of said logic operations is an operation to pass said first data as said result to said input means of said dynamic random access memory means.

15. A memory device according to claim 11, wherein said dynamic random access memory means is used for storing graphic data as the data.

16. A memory device with operation function, formed on one chip as an integrated device, comprising:

dynamic random access memory means for storing data;

first and second data terminals, said terminals being formed on the chip in order to receive data from an external side of the integrated device, said first data terminal being to be connected to data bus, and said second data terminal to be connected to address bus; and

means for executing an operation between data provided through said first data terminal and data read from said dynamic random access memory means, the result of said operation being stored in said dynamic random access memory means, including function setting means responsive to a function mode signal provided through said second data terminal for setting a function indicated by said function mode signal prior to receipt of data through said first data terminal, whereby the operation of said executing means is preset in accordance with the function set by said function setting means prior to receipt of said data through said first data terminal, and wherein the reading out of data from said dynamic random access memory means, the execution of said operation on said data by said executing means and the storing of the result of the execution is effected during one memory cycle of said random access memory means.

17. A memory device according to claim 16, wherein said operations executed by said execution means are logic operations between said data provided through said first data terminal and said data read from said dynamic random access memory means.

18. A memory device according to claim 16, wherein said operations executed by said execution means are arithmetic operations between said data provided through said first data terminal and said data read from said dynamic access memory means.

19. A memory device according to claim 16, wherein one of said operations executed by said executing means is an operation to pass said data provided through said first data terminal as said result to said dynamic random access memory means.

20. A memory device according to claim 16, wherein said dynamic random access memory means stores graphic data as the data.

21. A memory device on an IC chip responsive to an access from an external side of the IC chip, comprising:

dynamic memory means for effecting data read and write operations and having a plurality of memory locations;

a first path connected to said dynamic memory means for transferring data read out from one of said memory locations designated by an access address provided from the external side during a first duration of one memory cycle of said dynamic memory means;

control means having output means, first data input means connected to receive data provided via a data bus from the external side, second data input means connected to said first path for receiving said data read from said dynamic memory means, third data input means connected to receive a function mode signal supplied via address but from the external side prior to said first duration, and operation means for executing one of a plurality of operations selected in response to said function mode signal between said data received by said first data input means and said data received by said second data input means during a second duration of said one memory cycle following said first duration; and

a second path connecting said output means of said control means to said memory means for transferring a result of the execution of said selected operation, said result being stored in said designated location of said memory means during a third duration of said one memory cycle following said second duration.

22. A memory device according to claim 21, wherein said operation means repeats said selected operation within a plurality of memory cycles after receiving said function mode signal.

23. A memory device according to claim 21, wherein said operations are logic operations between said data received by said first data input means and said data received by said second data input means.

24. A memory device according to claim 21, wherein said operations are arithmetic operations between said data received by said first data input means and said data received by second data input means.

25. A memory device according to claim 21, wherein said selected operation is an operation to pass said data received by said first data input means.

26. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element having a plurality of storage locations for reading, writing and storing data from, to and in said storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal in accordance with an operation mode signal and outputting result data; and

an operation mode setting means for setting said operation mode signal of said operation means with receiving said operation mode signal supplied through said address terminal.

27. A memory device on an IC chip according to claim 26, wherein said operation mode setting means receives said operation mode signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

28. A memory device on an IC chip according to claim 26, wherein said result data outputted from said operation means is written to said memory element.

29. A memory device on an IC chip according to claim 26, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

30. A memory device on an IC chip according to claim 26, wherein said memory element stores graphic data as said data.

31. A memory device on an IC chip according to claim 26, wherein one of said control signals supplied through said control terminal is a decoded signal produced by decoding said address signals.

32. A memory device on an IC chip according to claim 26, wherein said operation means executes logical operations to said read data and said first data.

33. A memory device on an IC chip according to claim 32, wherein one of said logical operations is an operation to pass said first data as said result data to said memory element.

34. A memory device on an IC chip according to claim 26, wherein said operation means executes arithmetic operations to said read data and said first data.

35. A memory device on an IC chip according to claim 26, wherein said operation mode setting means receives said operation mode signal as lower bits of said address signals through said address terminal.

36. A memory device on an IC chip according to claim 26, wherein said memory element has a serial output port for outputting said data in serial.

37. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element having a plurality of storage locations for reading, writing, and storing data from, to, and in said storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal to output result data in accordance with an operation mode signal; and

an operation mode setting means for receiving said operation mode signal supplied through said address terminal, and setting said operation mode signal to said operation means, said operation mode setting means including a plurality of operation mode register means respectively storing said operation mode signal and a first selector means for selecting one of a plurality of said operation mode register means to supply said operation mode signal to said operation means.

38. A memory device on an IC chip according to claim 37, wherein said operation mode setting means receives said operation mode signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

39. A memory device on an IC chip according to claim 37, wherein said result data outputted from said operation means is written to said memory element.

40. A memory device on an IC chip according to claim 37, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

41. A memory device on an IC chip according to claim 37, wherein said memory element is used for storing graphic data as said data.

42. A memory device on an IC chip according to claim 37, wherein one of said control signals supplied through said control terminal is a decoded signal produced by decoding said address signals.

43. A memory device on an IC chip according to claim 37, wherein said operation means executes logical operations to said read data and said first data.

44. A memory device on an IC chip according to claim 43, wherein one of said logical operations is an operation to pass said first data as said result data to said memory element.

45. A memory device on an IC chip according to claim 37, wherein said operation mode setting means receives said operation mode signal as lower bits of said address signals through said address terminal.

46. A memory device on an IC chip according to claim 37, wherein said first selecting means selects said one of said operation mode register means in response to said control signals provided through said control terminal.

47. A memory device on an IC chip according to claim 37, wherein said memory element has a serial output port for outputting said data in serial.

48. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element for reading, writing and storing data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal in accordance with an operation mode signal and outputting result data;

an operation mode setting means for setting said operation mode signal with receiving said operation mode signal supplied through said address terminal; and

a write control means for outputting a write control signal in a bit unit to said memory element in accordance with second data supplied through said data terminal.

49. A memory device on an IC chip according to claim 48, wherein said operation mode setting means receives said operation mode signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

50. A memory device on an IC chip according to claim 48, wherein said memory element is used for storing said result data outputted from said operation means.

51. A memory device on an IC chip according to claim 48, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

52. A memory device on an IC chip according to claim 48, wherein one of said control signals supplied through said control terminal is a decoded signal produced by decoding said address signals.

53. A memory device on an IC chip according to claim 48, wherein said operation means executes logical operations to said read data and said first data.

54. A memory device on an IC chip according to claim 53, wherein one of said logical operations is an operation to pass said first data as said result data to said memory element.

55. A memory device on an IC chip according to claim 48, wherein said operation mode setting means receives said operation mode signal as lower bits of said address signals through said address terminal.

56. A memory device on an IC chip according to claim 48, wherein said write control means receives said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

57. A memory device on an IC chip according to claim 48, wherein said operation mode setting means and said write control means respectively receive said operation mode signal through said address terminal and said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

58. A memory device on an IC chip according to claim 48, wherein said memory element has a serial output port for outputting said data in serial.

59. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element for reading, writing, and storing data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal to output result data in accordance with an operation mode control signal;

an operation mode setting means for receiving said operation mode control signal supplied through said address terminal, and setting said operation mode control signal to said operation means, said operation mode setting means including a plurality of operation mode register means respectively storing said operation mode control signal and a first selector means for selecting one of a plurality of said operation mode register means to supply said operation mode control signal to said operation means; and

a write control means for outputting a write control signal in a bit unit to said memory element in accordance with second data supplied from said data terminal, said write control means including a plurality of write control register means respectively storing said write control signal and a second selector means for selecting one of said write control register means to supply said write control signal to said memory element.

60. A memory device on an IC chip according to claim 59, wherein said operation mode setting means receives said operation mode control signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

61. A memory device on an IC chip according to claim 59, wherein said memory element is used for storing said result data outputted from said operation means in accordance with said second data supplied from said write control means.

62. A memory device on an IC chip according to claim 59, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

63. A memory device on an IC chip according to claim 59, wherein said memory element stores graphic data as said data.

64. A memory device on an IC chip according to claim 59, wherein said operation means executes logical operations to said read data and said first data.

65. A memory device on an IC chip according to claim 64, wherein one of said logical operations is an operation to pass said first data as result data as to said memory element.

66. A memory device on an IC chip according to claim 59, wherein said operation mode setting means receives said operation mode control signal as lower bits of said address signals through said address terminal.

67. A memory device on an IC chip according to claim 59, wherein said first selector means selects said one of said operation mode register means in response to said control signals provided through said control terminal.

68. A memory device on an IC chip according to claim 59, wherein said write control means receives said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

69. A memory device on an IC chip according to claim 59, wherein said operation mode setting means and said write control means respectively receive said operation mode signal through said address terminal and said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

70. A memory device on an IC chip according to claim 59, wherein said second selector means selects said one of said write control means in response to said control signals provided through said control terminal.

71. A memory device on an IC chip according to claim 59, wherein said first selector means and second selector means respectively select said one of said operation mode register means and said one of said write control register means in response to said control signals provided through said control terminal.

72. A memory device on an IC chip according to claim 59, wherein said memory element has a serial output port for outputting said data in serial.

BACKGROUND OF THE INVENTION

The present invention relates to a memory device, and in particular, to a memory device suitable for a graphic memory to be utilized in high-speed image processing.

The prior art technique will be described by referring to graphic processing depicted as an example in FIGS. 1-2. For example, the system of FIG. 1 comprises a graphic area M1 having a one-to-one correspondence with a cathode ray tube (CRT) screen, a store area M2 storing graphic data to be combined, and a modify section FC for combining the data in the graphic area M1 with the data in the store area M2. In FIG. 2, a processing flowchart includes a processing step S1 for reading data from the graphic area M1, a processing step S2 for reading data from the store area M2, a processing step S3 for combining the data read from the graphic area M1 and the data read from the store area M2, and a processing step S4 for writing the composite data generated in the step S3 in the graphic area M1.

In the graphic processing example, the processing step S3 of FIG. 2 performs a logical OR operation only to combine the data of the graphic area M1 with that of the store area M2.

On the other hand, the graphic area M1 to be subjected to the graphic processing must have a large memory capacity ranging from 100 kilobytes to several megabytes in ordinary cases. Consequently, in a series of graphic processing steps as shown in FIG. 2, the number of processing iterations to be executed is on the order of 10.sup.6 or greater even if the processing is conducted on each byte one at a time.

Similarly referring to FIGS. 2-3, graphic processing will be described in which the areas M1 and M2 store multivalued data such as color data for which a pixel is represented by the use of a plurality of bits.

Referring now to FIG. 3, a graphic processing arrangement comprises a memory area M1 for storing original multivalued graphic data and a memory area M2 containing multivalued graphic data to be combined therewith.

For the processing of multivalued graphic data shown in FIG. 3, addition is adopted as the operation to ordinarily generate composite graphic data. As a result, the values of data in the overlapped portion become larger, and hence a thicker picture is displayed as indicated by the crosshatching. In this case, the memory area must have a large memory capacity. The number of iterations of processing from the step S1 to the step S4 becomes on the order of 10.sup.6 or greater, as depicted in FIG. 2. Due to the large iteration count, most of the graphic data processing time is occupied by the processing time to be elapsed to process the loop of FIG. 2. In graphic data processing, therefore, the period of time utilized for the memory access becomes greater than the time elapsed for the data processing. Among the steps S1-S4 of FIG. 2, three steps S1, S2, and S4 are associated with the memory access. As described above, in such processing as graphic data processing in which memory having a large capacity is accessed, even if the operation speed is improved, the memory access time becomes a bottleneck of the processing, which restricts the processing speed and does not permit improving the effective processing speed of the graphic data processing system.

In the prior art examples, the following disadvantages take place.

(1) In the graphic processing as shown by use of the flowchart of FIG. 2, most of the processing is occupied by the steps S1, S2, and S4 which use a bus for memory read/write operations, consequently, the bus utilization ratio is increased and a higher load is imposed on the bus.

(2) The graphic processing time is further increased, for example, because the bus has a low transfer speed, or the overhead becomes greater due to the operation such as the bus control to dedicatedly allocate the bus to CRT display operation and to memory access.

(3) Moreover, although the flowchart of FIG. 2 includes only four static processing steps, a quite large volume of data must be processed as described before. That is, the number of dynamic processing steps which may elapse the effective processing time becomes very large, and hence a considerably long processing time is necessary.

Consequently, it is desirable to implement a graphic processing by use of a lower number of processing steps.

A memory circuit for executing the processing described above is found in the Japanese Patent Unexamined Publication No. 55-129387, for example.

Recent enhanced resolution of graphic display units is now demanding a large-capacity memory for use as a frame buffer for holding display information. In displaying a frame of graphic data, a large number of access operations to a capacious frame buffer take place, and therefore high-speed memory read/write operations are required. A conventional method for coping with this requirement is the distribution of processings.

An example of the distributed process is to carry out part of the process with a frame buffer. FIG. 26 shows, as an example, the arrangement of the frame buffer memory circuit, used in the method. The circuit includes an operation unit 1, a memory 2, an operational function control register 23, and a write mask register 26. The frame buffer writes data in bit units regardless of the word length of the memory device. On this account, the frame buffer writing process necessitates to implement operation and writing both in bit units. In the example of FIG. 26, bit operation is implemented by the operation unit 1 and operational function control register 23, while bit writing is implemented by the mask register 6 only to bits effective for writing. This frame buffer is designed to implement the memory read-modify-write operation in the write cycle for data D from the data processor, eliminating the need for the reading of data D0 out of the memory, which the usual memory necessitates in such operation, whereby speedup of the frame buffer operation is made possible.

FIG. 27 shows another example of distributed processing which is applied to a graphic display system consisting of two data processors 20 and 20' linked through a common bus 21 with a frame buffer memory 9". The frame buffer memory 9" is divided into two areas a and b which are operated for display by the data processors 20 and 20', respectively. FIG. 28 shows an example of a display made by this graphic system. The content of the frame buffer memory 9" is displayed on the CRT screen, which is divided into upper and lower sections in correspondence with the divided memory areas a and b as shown in FIG. 28. When it is intended to set up the memory 9" for displaying a circle, for example, the data processor 20 produces an arc .alpha..alpha.'.alpha." and the data processor 20' produces a remaining arc .beta..beta.'.beta." concurrently. The circular display process falls into two major processings of calculating the coordinates of the circle and writing the result into the frame buffer. In case the calculation process takes a longer time than the writing process, the use of the two processors 20 and 20' for the process is effective for the speedup of display. If, on the other hand, the writing process takes a longer time, the two processors conflict over the access to the frame buffer memory 9", resulting in a limited effectiveness of the dual processor system. The recent advanced LSI technology has significantly reduced the computation time of data processors relative to the memory write access time, which foster