Inter-LAN connection equipment - Patent Review 5477547

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an inter-LAN connection equipment for packet forward among LANs (local area network) and, in particular, to an inter-LAN connection equipment as a bridge equipment which can effectively forward or discard a packet after learning of an MAC address (media access control address).

2. Description of the Related Art

Conventionally, an inter-LAN connection equipment (or a bridge equipment) for internal learning of a MAC address receives all packets sent from LANs and discards, out of all the packets, a packet whose destination is directed to a node on the same LAN, that is, discards it without being forwarded. The reason for this is that it is not necessary to forward the packet if it is sent to a given node on the same LAN. If being forwarded, the packet involved causes a lowering in the forward efficiency of a forward-destination LAN. For this reason, the packet, being directed to the given node on the same LAN, has normally been discarded by a microprocessor without being forwarded. In this case, the microprocessor determines whether or not a packet should be discarded in accordance with a control program.

Determining whether the packet supplied from the given LAN should be forwarded or discarded has been done in the program processing by the microprocessor. In the conventional inter-LAN connection equipment, however, communication is often carried out on the same LAN and it takes more time to perform discard processing than an ordinary forward processing. Even if use is made of any high-speed microprocessor, it has been difficult to improve the performance of the inter-LAN connection equipment.

In the conventional inter-LAN connection equipment, a packet sent from the LAN is stored in a buffer memory. Then in the case where the packet is to be forwarded or passed, after it has been fully received from its start portion to its end portion, the transmission of the packet to the forward-side LAN is started. For this reason, more time delay occurs in the transmission of the packet than in the absence of any inter-LAN connection equipment. Therefore, the terminal-to-terminal (LAN-to-LAN) communication performance has been markedly lowered in comparison with the communication performance on the same LAN, thus presenting a problem.

A more high-performance inter-LAN connection equipment has been proposed as shown in KOKAI H-4-237232. In this proposal, control is made so as to prevent reception of any packet not requiring any forward, that is, any packet to be communicated on the same LAN. In this case, control is made on an external hardware.

The description of KOKAI H-4-237232 suggests a practical applicability of the packet discard determination technique to the packet forward determination technique, but there is no suggestion as to achieving a high-speed packet forward. Therefore, there is a demand for achieving a high-speed packet forward unit.

SUMMARY OF THE INVENTION

It is accordingly the object of the present invention to provide an inter-LAN connection equipment which can fastly start the forward of a packet to be passed and enhance a communication performance among terminals.

According to a first aspect of the present invention, an inter-LAN connection equipment connected to at least two LANs is provided, comprising:

address learning means, provided in each LAN, for receiving a packet sent from a given LAN and for generating address information having a transmit-source address in the packet and a port address for distinguishing the given LAN;

table memory address generating means, provided in each LAN, for compressing the transmit-source address in the packet and for generating a table memory address;

a shared table memory for allowing the address information which is generated from the address learning means to be registered in an entry designated with the table memory address generated from the table memory address generating means;

a first in--first out memory, provided in each LAN, for allowing any packet which is sent from any of LANs to be stored therein;

first comparing means, provided in each LAN, for receiving the packet sent from the LAN, for extracting a destination address in the received packet, for taking out the address information from the shared table memory at the corresponding entry and for comparing the destination address with the transmit-source address in the address information;

second comparing means, provided at each LAN, for taking out the address information from the shared table memory at the corresponding entry and for comparing the port address of that LAN corresponding to the transmit-source of the packet with the port address in the address information;

discarding means, provided in each LAN, for discarding the packet when a result of comparison by the first and second comparing means represents a coincidence; and

forward means, provided at each LAN, for allowing the packet which is stored in the first in--first out memory to be sent to that LAN corresponding to the port address of the read address information when a result of comparison by the first comparing means shows a coincidence and a result of comparison by the second comparing means shows a noncoincidence.

According to a second aspect of the present invention, an inter-LAN connection equipment is provided in which the forward means includes means for, when the destination address of the packet corresponds to a multicast address, effecting such control as to transmit the packet to all the other LAN sides irrespective of the results of comparison by the first and second comparing means.

By so doing, the FIFO memory earlier allows the delivery of the packet as an output and the switching network performs such control as to connect the output of the FIFO memory to a port of the LAN at a transmit-destination side. It is, therefore, possible to start the forward of a packet, to be passed, to the transmit-destination LAN side, whereby it is possible to perform a forward operation with the same performance as in the communication among the same LAN.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a block diagram showing an arrangement of an inter-LAN connection equipment according to a first embodiment of the present invention.

FIG. 2 is a schematic view showing a relationship of a connection between an inter-LAN connection equipment and a plurality of LANs shown in FIG. 1;

FIG. 3 is a view showing a packet format of a packet used in the first embodiment shown in FIG. 1;

FIG. 4 is a circuit arrangement for handling on a generation polynomial used in the first embodiment shown in FIG. 1;

FIG. 5 is a format of address information registered in an FAT memory shown in FIG. 1;

FIG. 6 is a detail block diagram showing an interface section between inter-LAN connection equipment and LAN 10; equipment and LAN 10;

FIGS. 7A and 7B are diagrams showing a delay time involved when a packet is forwarded; and

FIG. 8 is a block diagram showing an inter-LAN connection equipment according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an arrangement of an inter-LAN connection equipment according to a first embodiment of the present invention. In FIG. 1, the arrangement of a connection interface section on the side of one of a plurality of LANs is principally shown. The inter-LAN connection equipment 40 is connected to LANs 10, 20 and 30. That is, the inter-LAN connection equipment 40 is comprised of a bridge equipment for passing a packet among LANs 10, 20 and 30. In the present embodiment, LANs are of a bus type. Nodes (terminals) 11, 12, 13, . . . are connected to LAN 10; nodes (terminals) 21, 22, 23, . . . , to LAN 20 and nodes (terminals) 31, 32, 33, . . . , to LAN 30.

The interior of the inter-LAN connection equipment corresponding to LAN 10 of the three LANs are principally dealt with. Various operations of the inter-LAN connection equipment are controlled under a microprocessor 56. LAN 10 and received at a connection interface (serial interface), not shown, in the inter-LAN connection equipment.

The connection interface sends the received packet to a LAN controller 52, address learning circuit 57, DA (destination address) holding register 45 and FIFO (first in--first out memory) 421.

The packet packet format, shown in FIG. 3, comprises a PA (preamble), SFD (start packet delimiter), DA (Destination address), SA (source address), DATA (data), TR (trailer) and FG (packet gap), followed by PA (Preamble), . . . , in the next packet.

A LAN controller 52 makes packet forward control between LAN 10 and another LAN and includes a serial/parallel conversion function for conversion of a signal to a serial or parallel one, etc. The LAN controller 52 receives a packet from LAN 10 and stores it in a buffer 521. The LAN controller 52 discards the packet involved, as required, as will be set out below.

The FIFO memory 421 can hold, for example, a one-bit wide serial data. The FIFO memory 421 receives serial data from LAN 10 and holds it until it receives an instruction of whether or not the packet should be forwarded. Further, the FIFO memory 421 delivers the packet, in accordance with an instruction of forwarding. For this reason, from the reception of header data of the packet until the reception of an instruction of whether or not the packet should be forwarded, the FIFO memory 421 has a memory capacity for holding intervening data. If it is determined that the packet be forwarded, there is sometimes the case where a transmit-side LAN port (for example, a port on the LAN 20 side) is now in service. Taking such a case into consideration, an FIFO memory is adopted which has the ability to receive one packet length. The output operation of the FIFO memory 421 is started responsive to a forward start signal S1 from a packet forward control circuit 55 as will be set out below.

In the inter-LAN connection equipment 40, a 1-bit wide FIFO 422 is provided on the LAN 20 side to receive a packet (serial data). Similarly, for example, a 1-bit wide FIFO memory 423 is provided on the LAN 30 side to receive a packet (serial data). The output operation of the FIFO memory 422 is started responsive to a forward start signal S2 from a packet forward control circuit (not shown) on the LAN 20 side. Similarly, the output operation of the FIFO memory 423 is started responsive to a forward start signal S3 from a packet forward control circuit (not shown) on the LAN 30 side.

The address learning circuit 57 has the function of learning which node (terminal) is connected to LAN 10. That is, the address learning circuit 57 is responsive to a packet from LAN 10 to learn based on a transmit-source address SA in that packet. In other words, the address learning circuit 57 extracts, as a terminal address, the transmit-source address SA (48 bits) in the packet and sends it to an FAT (Filtering Address table) memory address generating circuit 44. In accordance with an FAT memory address generated from the FAT memory address generating circuit, the address learning circuit 57 writes, in the FAT memory 43 at a predetermined location, address information containing a LAN port address, terminal address and V bit. The LAN port address in this case is sent from a later-described LAN port address setting circuit 41 and indicates that the address information corresponds to the LAN 10 side.

On the other hand, the DA (Destination address) holding register 45 receives the destination address DA (48 bits), in a serial way, in the packet from LAN 10 and holds it.

The FAT memory address generating circuit 44 compresses the terminal address (transmit-source address SA) from the address learning circuit 57 or destination address DA held in the DA holding register 45 to generate the FAT memory address (entry address). The FAT memory address generating circuit 44 includes a CRC (cyclic redundancy check) circuit as shown in FIG. 4. The CRC circuit compresses a 48-bit terminal address on the basis of a generation polynomial (data for compression) set by the microprocessor 56 as will be later described and generates an FAT memory address as a CRC code. It is to be noted that C0, C1, . . . , Cn-3, Cn-2, Cn-1 represent data of the generation polynomial entered, that I0, I1, . . . , In-3, In-2 and In-1 represent data based on the terminal addresses entered, and that A1, A2, A3, . . . , An-2, An-1 and An represent output CRC codes.

The FAT memory address generating circuit 44 sends the FAT memory address to the FAT memory 43. The FAT memory address designates an entry position in the FAT memory where the address information above is written.

The FAT memory 43 serves as a common memory where not only the address information from the LAN 10 side but also address information from the LANs 20 and 30 sides are stored. The FAT memory 43 has a plurality of entries for registering address information containing the terminal address and LAN address. The entry address in the FAT memory 43 corresponds to the terminal address of the address information registered at the entry. The entry address is represented by the CRC code generated based on the terminal address and generation polynomial. If any duplication of the address information occurs in the FAT memory, the microprocessor 56 has the ability to eliminate such duplication through the rewriting of the generation polynomial for use in the FAT memory address circuit 44. By so doing it is possible to enhance the utilization efficiency of the FAT memory.

The format of the address information registered in the FAT memory 43 will be explained below with reference to FIG. 5. The address information is comprised of, as shown in FIG. 5, 48-bit terminal address (or node address, MAC address), LAN port address representing the type of LAN connected to the terminal designated with the terminal address, and V bit (validity/invalidity bit) representing whether or not the address information is valid.

Referring back to FIG. 1, the LAN port address setting circuit 41 holds a LAN port address for distinguishing the LAN 10 and delivers the LAN port address as an output when the address information from the address learning circuit 57 is written into the FAT memory 43.

A LAN port address comparing circuit 46 compares the LAN port address (here the port address of LAN 10) from the LAN port address setting circuit 41 with the LAN port address of the address information read out of the FAT memory 43 and delivers a coincidence signal when these addresses coincides with each other and a noncoincidence signal when these signals do not coincide with each other. On the other hand, a terminal address comparing circuit 47 compares the destination address DA held in the DA holding register 48 with the terminal address of the address information read out of the FAT memory 43 and delivers a coincidence signal when there occurs a coincidence between these addresses. As a result, through a combination of the LAN port address comparing circuit 46 and terminal address comparing circuit 47, it is possible to determine whether or not the terminal, that is, the terminal having the same address (terminal address) as the destination address DA held in the DA holding register 45, is connected to the same LAN (here, LAN 10) as the transmit-source terminal.

A packet discard instructing circuit 48 performs a discard instruction when the condition is met. That is, the packet discard instructing circuit 48 receives a V of in the address information from the FAT memory and delivers a packet discard signal 49 representing the discarding of the packet both when the V bit shows a valid display state (ON state) and when the circuit 48 detects these coincidence signals from the comparing circuits 46 and 47. It is to be noted that the packet discard instruction circuit 48 is comprised of, for example, an AND gate.

The LAN controller 52 receives a packet discard signal 49 from the packet discard instruction circuit 48 and performs that packet discard processing.

A packet forward instruction circuit 50 implements a discard instruction when the condition is met. That is, the packet forward instruction circuit 50 receives the V bit of the address information from the FAT memory and delivers a packet forward signal 51 showing the forward of the packet both when the V bit represents a valid display state (ON state) and when the circuit 50 detects a noncoincidence and coincidence signal from the comparing circuits 46 and 47, respectively. It is to be noted that the instruction circuit 50 is comprised of, for example, an AND gate.

A switching network 53 connects the port of the receive-side LAN of LANs 10, 20 and 30 to that of the transmit-side LAN. The switching network 53 selectively connects the outputs of the FIFO memories 421, 422 and 423 which correspond to LANs 10, 20 and 30 to the LAN port to be forwarded. In this case, the LAN port to be forwarded is the same as the LAN port designated with the LAN port address in the received packet.

The decoder 54 decodes the LAN port address of the address information from the FAT memory 43. If LAN 20 is designated with the LAN port address, the decoder 54 delivers a LAN port select signal 542 showing that LAN 20 has been selected. If, on the other hand, LAN 30 is designated with the LAN port address, the decoder 54 delivers a LAN port select signal 543 showing that LAN 30 has been selected.

A packet forward control circuit 55 controls the FIFO memory 421 and switching network 53 so as to selectively connect the output of the FIFO memory 421 to the port of LAN 20 or 30. The control circuit 55 is comprised of AND gates 552 and 553 and OR gate 554.

The AND gate 552 delivers a signal to the switching network 53 and OR gate 554 when it detects a LAN port select signal 542 from the decoder 54, a packet forward signal 51 from the packet instruction circuit 50 and a ready signal R2 from a LAN controller, not shown. Here, the ready signal R2 is sent from a controller, not shown, for LAN 20 in a connection interface section on the LAN 20 side in the inter-LAN connection equipment 40. The controller for LAN 20 delivers the ready signal R2 when a packet is ready for reception from the LAN 10 side.

The AND gate 553 delivers a signal to the switching network 53 and OR gate 554 when it detects a LAN port select signal 543 from the decoder 54, a packet forward signal 51 from the packet forward instruction circuit 50 and a ready signal R3 from a LAN controller, not shown. Here, the ready signal R3 is sent from a controller, not shown, for LAN 30 which is provided at a connection interface section on the LAN 30 side of the inter-LAN connection equipment 40. The controller for LAN 30 delivers a ready signal R3 when a packet is ready for reception from the LAN 10 side.

The OR gate 554 delivers a forward start signal S1 to the FIFO memory 421 when it detects the outputs from the AND gates 552 and 553. The forward start signal S1 represents an instruction for the starting of the delivery of the packet to the FIFO memory 421.

Responsive to a forward start signal S1 from the OR gate 554, the FIFO memory 421 sends its held packet to the switching circuit 53.

Upon detecting a signal from the AND gate 552, the switching network 53 connects the port on the LAN 10 side to that on the LAN 20 side so that a corresponding packet is sent from the FIFO memory 421 to the LAN 20 side. Upon detecting a signal from the AND gate 553, on the other hand, the switching network 53 connects the port on the LAN 10 side to that on the LAN 30 side so that a corresponding packet is sent from the FIFO memory 421 to the LAN 30 side.

Though not shown in FIG. 1, the inter-LAN connection equipment 40 includes, at the connection interface to LANs 20 and 30, the same constituent elements as a LAN port address setting circuit 41, FAT memory address generating circuit 44, DA holding register 45, comparing circuits 46, 47, packet discard instruction circuit 48, packet forward instructing circuit 50, LAN controller 52, decoder 54 and packet forward control circuit 55.

Now the operation of the first embodiment will be explained below.

The inter-LAN connection equipment 40 is controlled by the microprocessor 56. At an initial state, the microprocessor sets the contents of each entry in the FAT memory 43 all to an invalid state. In this case, the microprocessor 56 renders the V bit in each entry in the OFF state.

With the LAN controller 52 set to a promiscuous mode, the microprocessor 56 enables the inter-LAN connection equipment to function as a bridge. A serial packet from LAN 10 is received at the connection interface to the inter-LAN connection equipment 40. The packet, received at the LAN controller 52, is temporarily stored in the buffer 521.

In the full receive mode, while the packet is being stored in the buffer 521, the address learning circuit 57 extracts, as a terminal address, a 48-bit transmit-source address SA in the received packet.

The address learning circuit 57 supplies the extracted address (transmit-source address SA) to the FAT memory address generating circuit 44. Then in the FAT memory address generating circuit 44, the terminal address is compressed through the utilization of a given generation polynomial and an FAT memory address (write address) is generated.

Into the FAT memory entry designated with the generation FAT memory address the address learning circuit 57 writes address information containing a LAN port address, terminal address and V bit. The LAN port address of the address information which is written into the FAT memory 43 shows a value representing LAN 10 set in the LAN port address setting circuit 41. Further, the terminal address in the address information corresponds to the extracted transmit-source address SA. Here the V bit is set to an ON (V=1) state.

The above is an explanation on the address learning by the address learning circuit 57. After the above address learning has been implemented, a packet of those packets received from LAN 10, that is, a packet having a destination address of the same value as that of the terminal address registered in the FAT memory 43 through the address learning, ceases to be received by the LAN controller 52 because, as will be set out below, a packet discard signal 49 is output from the packet discard instructing circuit 48 to the LAN controller 52.

It is to be noted that the address learning is normally made through the address learning circuit 57. Further, when the address learning circuit 57 receives, from the LAN 10 side, packet having a transmit-source address SA not registered in the FAT memory, it registers the address SA as a terminal address in a form to be contained in address information.

The operation following the address learning will be explained below. Here, reference is made to FIGS. 6 and 1 conjointly in supporting the following explanation.

A transmit packet from the LAN 10 side is received via a serial interface, not shown. The packet (received serial data) thus received is fed to the FIFO memory 421, DA holding register 45, LAN controller 52 and address learning circuit 57. By so doing, the received serial data is stored in the 1-bit data wide FIFO memory 421 sequentially with its header side ahead and held there, while it is shift-input bit by bit in the DA holding register 45 of a 48-bit configuration. The serial data is received by the LAN controller 52 to allow it to be converted to parallel data and is sequentially stored in the buffer 52. It is to be noted that the contents in the FIFO memory 421 and in the buffer 521 are cleared at a start of inputting and holding one received packet.

In accordance with a predetermined packet format a destination address detecting circuit (DA detecting circuit) 61 at a connection interface section of the LAN 10 side (see FIG. 6) detects a 48-bit destination address DA from the packet received via the serial interface. When the destination address detecting circuit 61 detects a final bit of the destination address DA, it regards this as "the reception of DA is complete", informing this effect to a timing generating circuit 62 at the connection interface section of LAN 10.

The timing generating circuit 62 instructs the DA holding register 45 to stop the shift operation in accordance with a DA detecting timing. At the same time, the timing generating circuit 62 requests an access arbitrating circuit 63 to make an arbitration for access to the FAT memory 43. The reason for the access arbitration thus required is as will be set out below. That is, even at LANs 20 and 30, a timing generating circuit is provided which is similar to the timing generating circuit 62 on the connection interface to LAN 10. The respective timing generating circuit gains access to not only the microprocessor 56 but also the FAT memory 43. It is, therefore, necessary to arbitrate each access.

When access is granted by the access arbitrating circuit to the FAT memory, the timing generating circuit 62 gives an FAT memory address generation instruction corresponding to the contents in the DA holding register 45 to the FAT memory address generating circuit 44, a memory access signal to the FAT memory 43 for address information readout, and a compare operation instruction to the comparing circuits 46 and 47.

The shift operation of the DA holding circuit 45 is stopped at a time in which an instruction is made from the timing generating circuit 62 to stop the shift operation. At this time, the DA holding register 45 holds a 48-bit destination address DA in the received packet.

The FAT memory address generating circuit 44 compresses the destination address DA in the DA holding register 45 by a given generation polynomial (compression data initially set in the microprocessor) in an address generation instruction timing from the timing generating circuit 62 to generate a FAT memory address. Here, a CRC signal (about 8 to 16 bits) of the 48-bit destination address DA is generated with the FAT memory address.

The FAT memory address of the FAT memory address generating circuit 44 is supplied to the FAT memory 43 as shown in FIG. 1. By so doing, a given entry of the FAT memory addressed from the FAT memory address generating circuit 44 is accessed in a memory access timing from the timing generating circuit 62 so that address information in the corresponding entry is read out.

The terminal address of the address information read from the FAT memory 43, together with the destination address DA in the DA holding register 45, is supplied to the terminal address comparing circuit 47 where comparison is made between the terminal address and the destination address DA in accordance with a comparison operation instruction from the timing generating circuit. The comparing circuit 47 delivers a result of comparison as an output corresponding to a coincidence or a lack of a coincidence.

A LAN port address of the address information read out of the FAT memory, together with a LAN port address (address characteristic of LAN 10) set in the LAN port address setting circuit 41, is supplied to the LAN port address comparing circuit 46. The comparing circuit 46 compares both the LAN port addresses based on a compare operation instruction from the timing generating circuit 62 and delivers a result of comparison as an output representing a coincidence or a lack of a coincidence.

The results of comparison from the comparing circuits 46, 47 are supplied to the packet discard instruction circuit 48. The V bit of the address information read out of the FAT memory 43 is also supplied to the packet discard instruction circuit 48.

The packet discard instruction circuit 48 delivers a packet discard signal 49 when the results of comparison by the comparing circuits 46 and 47 represent a coincidence and V bit is ON (V=1). That is, when the V bit is ON (ON: the address information read from the FAT memory 43 is valid), the contents (destination address DA) of the DA holding register 45 coincides with the terminal address (address of an earlier learned node) read from the FAT memory 43 and LAN port addresses coincide with each other, then the source and the destination terminal exist on the same LAN. For this reason, the packet discard instructing circuit 48 regards this as there being no need to pass the packet and delivers a packet discard signal 49.

The results of comparison by the comparing circuit 46 for noncoincidence detection and result of comparison by the comparing circuit 47 for coincidence detection are supplied to the packet forward instructing circuit 50. The V bit of the address information read out of the FAT memory 43 is also supplied to the packet forward instructing circuit 50.

The packet forward instructing circuit 50 delivers a packet forward signal 51 when a noncoincidence is obtained upon comparison by the comparing circuit 46, coincidence is obtained upon comparison by the comparing circuit 47 and V bit is ON. That is, when, in the packet forward instructing circuit 50, the V bit is ON (ON: the address information read out of the FAT memory 43 is found valid), contents (destination address DA) of the DA holding register 45 coincides with the terminal address read out of the FAT memory 43 and LAN port addresses do not coincide with each other, the packet transmit source and destination terminal do not exist on the same LAN. For this reason, the packet forward instructing circuit 50 regards this as there being a need to pass the packet and delivers a packet forward signal 51.

The packet discard signal 49 from the packet discard instructing circuit 48 is supplied to the LAN controller 52. When the packet discard signal 49 is output from the packet discard instructing circuit 48, the LAN controller 52 stops receipt of the packet at that time, being in readiness for the next packet reception (or transmission). At this time, the data now being received is left in the FIFO memory 421 and buffer 521. When a new packet is next received from the LAN 10 side, the FIFO memory 421 and buffer 521 are cleared. The contents in the memory FIFO memory 421 and buffer 521 can be cleared in accordance with the packet discard signal 49.

On the other hand, the packet forward signal 51 from the packet forward instructing circuit 50 is supplied to the packet forward control circuit 55 and hence simultaneously to the AND gates 552 and 553 in the packet forward control circuit 55. The AND gate 552 receives a LAN port select signal 542 from the decoder 54 and ready signal R2 from the LAN controller on the LAN 20 side. The AND gate 553 receives a LAN port select signal 543 from the decoder 54 and ready signal R3 from the LAN controller on the LAN 30 side. The LAN port select signal 542 is enabled (logic level=1) when the LAN port address from FAT memory shows LAN 20. A LAN port select signal 543 is enabled (logic level=1) when the LAN port address read from the FAT memory shows LAN 30. Further, the ready signal R2 is enabled (logic level=1) when the port of LAN 20 is put in an available state (a ready state) and disabled (logic level=0) when in use (in a busy state). The ready signal R3 is enabled (logic level=1) when the port of LAN 30 is placed in an available state (ready state) and disabled (logic level=0) when in use (in the busy state).

When the packet forward signal 51 from the packet forward instructing circuit 50, LAN port select signal 542 from the decoder 54 and ready signal R2 from the LAN controller are enabled (logic level=1), then the AND gate 552 delivers a logic 1 signal to the switching network 53 so that the output of the FIFO memory 421 may be connected to the port of LAN 20.

On the other hand, when the packet forward signal 51 from the packet forward instructing circuit 50, LAN port select signal 543 from the decoder 54 and ready signal R3 from the LAN controller on the LAN 30 side are enabled (logic level=1), then the AND gate 553 delivers a logic 1 signal to the switching network 53 so that the output of the FIFO memory 421 may be connected to the port of LAN 30.

Both signals of the AND gates 552 and 553 are input to the OR gate 554. When any of the signals from the AND gates 552 and 553 is or are enabled (logic level=1), the OR gate 554 delivers a forward starting signal S1 to the FIFO memory 421.

When any enable (logic lever 1) signal is received from the AND gate 552 or AND gate 553, the switching network 53 connects the output of the FIFO memory 421 selectively to LAN 20 or LAN 30. That is, a switching operation is carried out.

At this time, the forward starting signal S1 from the OR gate 554 in the packet forward control circuit 55 is fed to the FIFO memory 421. By so doing, the FIFO memory 421, effecting a continuous sequential inputting/holding of the packet (received serial data) received from the LAN 10 side via the serial interface, delivers the inputted/held packet as an output in a sequential way.

The packet from the FIFO memory 421 is passed, via the switching network 53, to a transmit side (LAN 20 or LAN 30 side) designated with the LAN port address of the address information read out of the FAT memory 43.

The inter-LAN connection equipment 40 as shown in FIG. 2 receives, via a serial interface, the packet which is transmitted from the LAN 10 side. Thereafter, a somewhat small delay occurs until the packet forward signal 51 is generated by the packet forward instructing circuit 50 and hence the forward start signal S1 is generated by the packet forward control circuit 55. Immediately after the somewhat small time delay, it is possible to start the forward of the packet received from the LAN 10 side via the serial interface to the LAN port on the transmit side via the FIFO memory 421 and switching network 53. In the case where the LAN port on the transmit side is available particularly at a point of time in which the packet forward signal 51 is generated by the packet forward instructing circuit 50, that is, the packet forward is determined, then it is possible to start an immediate forward operation and, even if communication is made relative to a terminal connected to a different LAN, achieve nearly the same performance as in an inter-LAN communication. Since the packet (received serial data) can be forwarded straight through the 1-bit wide FIFO memory 421 and switching network 53 without forwarding the data after it has been received by the LAN controller 52 and subjected to a serial/parallel conversion, less number of signal lines can be achieved as signal lines required for packet forward.

FIGS. 7A and 7B shows a time relation from the reception of a packet to its forward in the inter-LAN connection equipment 40. FIG. 7A shows a forward state of a packet in the inter-LAN connection equipment 40, while FIG. 7B shows a forward state of a packet in the conventional inter-LAN connection equipment. It may be considered that, in the case shown in FIGS. 7A and 7B, the destination is, for example, at the terminal 21 on the LAN 20 and its transmit source is, for example, at the terminal 11 on LAN 10.