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Claims  |
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What is claimed is:
1. A semiconductor processing method of forming an electrically conductive
projection outwardly extending from a substrate, the method comprising the
following steps:
providing a substrate having a projecting pillar, the substrate having an
outer surface, the pillar projecting outwardly from the substrate outer
surface to a first distance;
providing a base layer of photoresist over the substrate outer surface to a
first maximum thickness which is less than the first distance to provide
the pillar projecting outwardly of the base photoresist layer;
providing a base layer of electrically conductive material over the pillar
and base layer of photoresist;
lifting off the base photoresist layer and overlying base layer of
electrically conductive material thereby providing the pillar with an
electrically isolated cap of base layer electrically conductive material,
the cap having top and side portions;
providing an interconnecting layer of electrically conductive material over
the substrate and pillar cap to a second maximum thickness, the
interconnecting electrically conductive material being selectively
etchable relative to the base electrically conductive material;
providing a masking layer of photoresist over the interconnecting layer to
a third maximum thickness, the second thickness and third thickness having
a sum which is greater than the first thickness;
patterning the photoresist masking layer for formation of an
interconnecting material conductive line extending from the pillar cap;
and
after patterning, etching exposed interconnecting material from the cap and
substrate to define a conductive line electrically engaging the side
portion of the conductive cap.
2. The semiconductor processing method of claim 1 wherein the third
thickness is less than the first distance.
3. The semiconductor processing method of claim 1 wherein the steps of
patterning and etching provide the conductive line to engage the
conductive cap on its side portion and not on its top portion.
4. The semiconductor processing method of claim 1 wherein the third
thickness is less than the first distance, and the steps of patterning and
etching provide the conductive line to engage the conductive cap on its
side portion and not on its top portion.
5. The semiconductor processing method of claim 1 wherein the pillar is
formed of the same material as the substrate.
6. The semiconductor processing method of claim 1 wherein the base
electrically conductive material is metal.
7. The semiconductor processing method of claim 1 wherein the
interconnecting electrically conductive material is metal.
8. The semiconductor processing method of claim 1 wherein the base
electrically conductive material is metal, and the interconnecting
electrically conductive material is metal.
9. The semiconductor processing method of claim 1 wherein the substrate and
pillar comprise silicon and the base electrically conductive material is
metal, the method further comprising annealing the substrate to form a
metal silicide at an interface of the cap and pillar.
10. The semiconductor processing method of claim 1 wherein,
the pillar is formed of the same material as the substrate;
the third thickness is less than the first distance;
the steps of patterning and etching provide the conductive line to engage
the conductive cap on its side portion and not on its top portion; and
the base electrically conductive material is metal, and the interconnecting
electrically conductive material is metal.
11. The semiconductor processing method of claim 1 wherein the photoresist
of the base layer and the photoresist of the masking layer comprise
different photoresists, the photoresist of the masking layer having a
higher viscosity than that of the base photoresist layer.
12. A semiconductor processing method of providing an electrical
interconnection between adjacent different elevation areas on a substrate,
the method comprising the following steps:
providing a substrate having a base surface and an adjacent elevated
surface, the elevated surface being spaced from the base surface by a
first distance thereby defining a step having a step wall;
providing a base layer of photoresist over the substrate base surface to a
first maximum thickness which is less than the first distance and
providing the elevated surface free of base photoresist;
providing a base layer of electrically conductive material over the
elevated surface, step wall and base layer of photoresist;
lifting off the base photoresist layer and overlying base layer of
electrically conductive material thereby providing the elevated surface
with a capping layer of base electrically conductive material which is
electrically isolated from the adjacent substrate base surface, the
capping layer having a side portion and a top portion, the side portion
extending downwardly along the step wall from the top portion and elevated
surface toward but not to the substrate base surface;
providing an interconnecting layer of electrically conductive material over
the substrate and capping layer to a second maximum thickness, the
interconnecting electrically conductive material being selectively
etchable relative to the base electrically conductive material;
providing a masking layer of photoresist over the interconnecting layer to
a third maximum thickness, the second thickness and third thickness having
a sum which is greater than the first thickness;
patterning the photoresist masking layer for formation of an
interconnecting material conductive line extending from the capping layer;
and
after patterning, etching exposed interconnecting material from the capping
layer and substrate to define a conductive line electrically engaging the
side portion of the capping layer.
13. The semiconductor processing method of claim 12 wherein the third
thickness is less than the first distance.
14. The semiconductor processing method of claim 12 wherein the steps of
patterning and etching provide the conductive line to engage the
conductive capping layer on its side portion and not on its top portion.
15. The semiconductor processing method of claim 12 wherein the third
thickness is less than the first distance, and the steps of patterning and
etching provide the conductive line to engage the conductive capping layer
on its side portion and not on its top portion.
16. The semiconductor processing method of claim 12 wherein the base
electrically conductive material is metal.
17. The semiconductor processing method of claim 12 wherein the
interconnecting electrically conductive material is metal.
18. The semiconductor processing method of claim 12 wherein the base
electrically conductive material is metal, and the interconnecting
electrically conductive material is metal.
19. The semiconductor processing method of claim 12 wherein,
the third thickness is less than the first distance;
the steps of patterning and etching provide the conductive line to engage
the conductive capping layer on its side portion and not on its top
portion; and
the base electrically conductive material is metal, and the interconnecting
electrically conductive material is metal.
20. The semiconductor processing method of claim 12 wherein the photoresist
of the base layer and the photoresist of the masking layer comprise
different photoresists, the photoresist of the masking layer having a
higher viscosity than that of the base photoresist layer. |
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Claims |
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Description |
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TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming an
electrically conductive projection outwardly extending from a substrate,
to semiconductor processing methods of providing an electrical
interconnection between adjacent different elevation areas on a substrate,
and to electrically conductive apparatus. This invention also relates to
methods for testing semiconductor circuitry for operability, and to
constructions and methods of testing apparatus for operability of
semiconductor circuitry.
BACKGROUND OF THE INVENTION
This invention relates to subject matter of our U.S. patent application
Ser. No. 08/116,394, filed on Sep. 3, 1993, and entitled "Method and
Apparatus for Testing Semiconductor Circuitry for Operability and Method
of Forming Apparatus for Testing Semiconductor Circuitry for Operability",
which is now U.S. Pat. No. 5,326,428. This '394 application and patent is
hereby fully incorporated into this document by reference.
Aspects of the related disclosure grew out of the needs and problems
associated with multichip modules. Considerable advancement has occurred
in the last fifty years in electronic development and packaging.
Integrated circuit density has and continues to increase at a significant
rate. However by the 1980's, the increase in density in integrated
circuitry was not being matched with a corresponding increase in density
of the interconnecting circuitry external of circuitry formed within a
chip. Many new packaging technologies have emerged, including that of
"multichip module" technology.
In many cases, multichip modules can be fabricated faster and more cheaply
than by designing new substrate integrated circuitry. Multichip module
technology is advantageous because of the density increase. With increased
density comes equivalent improvements in signal propagation speed and
overall device weight unmatched by other means. Current multichip module
construction typically consists of a printed circuit board substrate to
which a series of integrated circuit components are directly adhered.
Many semiconductor chip fabrication methods package individual dies in a
protecting, encapsulating material. Electrical connections are made by
wire bond or tape to external pin leads adapted for plugging into sockets
on a circuit board. However, with multichip module constructions,
non-encapsulated chips or dies are secured to a substrate, typically using
adhesive, and have outwardly exposed bonding pads. Wire or other bonding
is then made between the bonding pads on the unpackaged chips and
electrical leads on the substrate.
Much of the integrity/reliability testing of multichip module dies is not
conducted until the chip is substantially complete in its construction.
Considerable reliability testing must be conducted prior to shipment. In
one aspect, existing technology provides temporary wire bonds to the wire
pads on the die for performing the various required tests. However this is
a low-volume operation, and further requires the test bond wire to
ultimately be removed. This can lead to irreparable damage, thus
effectively destroying the chip.
Another prior art test technique uses a series of pointed probes which are
aligned to physically engage the various bonding pads on a chip. One probe
is provided for engaging each bonding pad for providing a desired
electrical connection. One drawback with such testing is that the pins
undesirably on occasion penetrate completely through the bonding pads, or
scratch the bonding pads possibly leading to chip ruin.
The invention described below was motivated in the desire to develop
improved electrical interconnection techniques associated with the
invention of the related '394 application. It is, however, recognized that
the invention disclosed herein is further applicable to methods and
constructions beyond that disclosed in the related '394 disclosure. This
invention, therefore, is limited only by the accompanying claims
appropriately interpreted in accordance with the Doctrine of Equivalents.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described below with reference
to the following accompanying drawings.
FIG. 1 is a diagrammatic representation of a fragment of a substrate
processed in accordance with the invention.
FIG. 2 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 1.
FIG. 3 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 2.
FIG. 4 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 3.
FIG. 5 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 4.
FIG. 6 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 5.
FIG. 7 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 6.
FIG. 8 is a view of the FIG. 1 substrate fragment at a processing step
subsequent to that shown by FIG. 7.
FIG. 9 is a perspective view of the FIG. 8 substrate fragment.
FIG. 10 is a diagrammatic representation of an alternate fragment of a
substrate processed in accordance with the invention.
FIG. 11 is a view of the FIG. 10 substrate fragment at a processing step
subsequent to that shown by FIG. 10.
FIG. 12 is a view of the FIG. 10 substrate fragment at a processing step
subsequent to that shown by FIG. 11.
FIG. 13 is a view of the FIG. 10 substrate fragment at a processing step
subsequent to that shown by FIG. 12.
FIG. 14 is a view of the FIG. 10 substrate fragment at a processing step
subsequent to that shown by FIG. 13.
FIG. 15 is a view of the FIG. 10 substrate fragment at a processing step
subsequent to that shown by FIG. 14.
FIG. 16 is a view of the FIG. 10 substrate fragment at a processing step
subsequent to that shown by FIG. 15.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
This disclosure of the invention is submitted in furtherance of the
constitutional purposes of the U.S. Patent Laws "to promote the progress
of science and useful arts" (Article 1, Section 8).
In accordance with one aspect of the invention, a semiconductor processing
method of forming an electrically conductive projection outwardly
extending from a substrate comprises the following steps:
providing a substrate having a projecting pillar, the substrate having an
outer surface, the pillar projecting outwardly from the substrate outer
surface to a first distance;
providing a base layer of photoresist over the substrate outer surface to a
first maximum thickness which is less than the first distance to provide
the pillar projecting outwardly of the base photoresist layer;
providing a base layer of electrically conductive material over the pillar
and base layer of photoresist;
lifting off the base photoresist layer and overlying base layer of
electrically conductive material thereby providing the pillar with an
electrically isolated cap of base layer electrically conductive material,
the cap having top and side portions;
providing an interconnecting layer of electrically conductive material over
the substrate and pillar cap to a second maximum thickness, the
interconnecting electrically conductive material being selectively
etchable relative to the base electrically conductive material;
providing a masking layer of photoresist over the interconnecting layer to
a third maximum thickness, the second thickness and third thickness having
a sum which is greater than the first thickness;
patterning the photoresist masking layer for formation of an
interconnecting material conductive line extending from the pillar cap;
and
after patterning, etching exposed interconnecting material from the cap and
substrate to define a conductive line electrically engaging the side
portion of the conductive cap.
In accordance with another aspect of the invention, an electrically
conductive apparatus comprises:
an electrically non-conducting substrate;
a pillar outwardly projecting from the substrate, the pillar having a top
surface and having side surfaces extending to the substrate;
a cap of first electrically conductive material coating the pillar
outermost top surface and only portions of the pillar side surfaces
outwardly of the substrate, the cap having outer top and outer side
portions; and
a conductive trace of second electrically conductive material which is
different from the first electrically conductive material; the conductive
trace overlying the substrate, portions of the pillar side surfaces not
covered by the cap, and the outer side portions of the cap.
In accordance with still a further aspect of the invention, a semiconductor
processing method of providing an electrical interconnection between
adjacent different elevation areas on a substrate, the method comprising
the following steps:
providing a substrate having a base surface and an adjacent elevated
surface, the elevated surface being spaced from the base surface by a
first distance thereby defining a step having a step wall;
providing a base layer of photoresist over the substrate base surface to a
first maximum thickness which is less than the first distance and
providing the elevated surface free of base photoresist;
providing a base layer of electrically conductive material over the
elevated surface, step wall and base layer of photoresist;
lifting off the base photoresist layer and overlying base layer of
electrically conductive material thereby providing the elevated surface
with a capping layer of base electrically conductive material which is
electrically isolated from the adjacent substrate base surface, the
capping layer having a side portion and a top portion, the side portion
extending downwardly along the step wall from the top portion and elevated
surface toward but not to the substrate base surface;
providing an interconnecting layer of electrically conductive material over
the substrate and capping layer to a second maximum thickness, the
interconnecting electrically conductive material being selectively
etchable relative to the base electrically conductive material;
providing a masking layer of photoresist over the interconnecting layer to
a third maximum thickness, the second thickness and third thickness having
a sum which is greater than the first thickness;
patterning the photoresist masking layer for formation of an
interconnecting material conductive line extending from the capping layer;
and
after patterning, etching exposed interconnecting material from the capping
layer and substrate to define a conductive line electrically engaging the
side portion of the capping layer.
More specifically and first with reference to FIGS. 1-9, a semiconductor
wafer fragment is indicated generally by reference numeral 10. Such is
comprised of a bulk substrate 12, preferably composed of monocrystalline
silicon, and an overlying layer 13 of an insulating material. Layer 13
preferably comprises an oxide or nitride, such as silicon dioxide or
silicon nitride, with 2000 Angstroms being an example thickness. In
combination, bulk substrate 12 and insulating layer 13 define an
electrically non-conducting substrate 15. A pillar 14 projects from
substrate 15. Pillar 14 can comprise the same material of substrate 15.
Accordingly, such can be formed from bulk substrate 12 in a manner
described in the related Serial No. '394 disclosure. A series of apexes
16, 18, 20 and 22 are provided atop pillar 14 in a manner and for reasons
also disclosed in the related '394 disclosure. Thereafter, layer 13 would
be deposited. Substrate 15 has an outer surface 24, and pillar 14 has a
general outer surface 26. Accordingly, pillar 14 projects outwardly from
substrate outer surface 24 to a first distance designated as "A". For
purposes of the continuing discussion, pillar 14 also includes side
surfaces 28 extending between top surface 26 and substrate outer surface
24.
A base layer 30 of photoresist is provided over substrate outer surface 24
to a first maximum thickness "B", which is less than first distance "A".
The preferred photoresist is one of low viscosity, such as somewhere
between 20 cp and 50 cp, and is typically spun onto the wafer. Such will
provide pillar 14 projecting outwardly of base photoresist layer 30. It is
desirable that no photoresist remain on any of the pillar side or top
surfaces. An optional exposure of the pillar using the same mask utilized
to produce pillar 14 from substrate 12 could be utilized to remove any
undesired photoresist adhering to pillar 14 above the plane of layer 30.
By way of example only, an example dimension "A" would be 75 microns,
while an example dimension "B" would be 2 to 3 microns.
Referring to FIG. 2, a base layer 32 of electrically conductive material is
provided over pillar 14 and base photoresist layer 30. Such preferably
comprises metal, with elemental platinum being but one preferred example.
An example thickness for layer 32 would be 500 Angstroms to 2000
Angstroms.
Referring to FIG. 3, a conventional photoresist lift-off technique is
employed to remove base photoresist layer 30 and overlying conductive base
layer 32. Such provides pillar 14 with an electrically isolated cap 34 of
base layer electrically conductive material. In the illustrated preferred
embodiment, cap 34 completely coats pillar outermost top surface 26 and
only portions of pillar side surfaces 28 outwardly of substrate 12. For
purposes of the continuing discussion, cap 34 itself includes an outer top
portion 36 and side portions 38. One example lift-off solution usable to
produce the construction of FIG. 3 from that of FIG. 2 is ST22 photoresist
stripper solution available from Advanced Chemical Systems International
of Milipitas, Calif.
Where material of cap 34 comprises metal and material of pillar 14
comprises silicon, it might be desirable to conduct a conventional high
temperature anneal step to cause a reaction between the materials of cap
34 and pillar 14 at the interface of the cap and pillar. Such might be
desirable to promote adhesion of cap 34 relative to pillar 14.
Referring to FIG. 4, an interconnecting layer 40 of electrically conductive
material is provided over the underlying substrate and pillar cap 34 to a
second thickness "C". Material of layer 40 is selected to be selectively
etchable relative to material of cap 34. Preferably, layer 40 is composed
of metal, with a preferred example being aluminum.
Referring to FIG. 5, a masking layer 42 of photoresist is provided over
interconnecting layer 40 to a third maximum thickness "D". Second
photoresist layer 42 is preferably comprised of a higher viscosity
photoresist than the first photoresist layer 30 to maximize the
elevational encroachment relative to pillar 14, as shown. To enhance this
encroachment, the photoresist is spun on at low speeds after which the
wafer is vibrated to enhance the photoresist to flow down from the tip
towards the base. An example preferred viscosity range for this higher
viscosity photoresist layer 42 is 100 to 300 cp. In the
reduction-to-practice method, the photoresist of layer 30 had a viscosity
of 30 cp, while the photoresist used for layer 42 had a viscosity of 130
cp. The relative thicknesses are chosen such that second thickness "C" and
third thickness "D" have a sum thickness "E" which is greater than first
thickness "B" of first photoresist layer 30.
Referring to FIG. 6, photoresist layer 42 is patterned for formation of an
interconnecting material conductive line which will extend from pillar cap
34, as shown. After such patterning and referring to FIG. 7, exposed
interconnecting material overlying cap 34 and the underlying substrate are
etched selectively relative thereto, which defines a conductive line or
trace 44 which electrically engages a side portion 38 of conductive cap
34. In the preferred embodiment as shown, conductive trace 44 overlies
bulk substrate 12, portions of pillar side surfaces 28 not covered by cap
34, and outer side portions 38 of cap 34, but not on top portion 36 of cap
34. Photoresist 42 is subsequently removed to produce the construction
illustrated by FIGS. 8 and 9.
Third thickness "D" is also preferably less than first distance "A" of
pillar 14 at its point of deposition. Alternately, but less preferred, an
extremely thick layer of photoresist (e.g., of a thickness "A") might be
provided and subsequently etched back (e.g., to a thickness "D").
The above described use of an insulating oxide or nitride layer 13 atop
bulk substrate 12 provides an effective insulating isolation between the
electrically conductive tips and their interconnects regardless of the
conductive nature of bulk substrate 12. For example, monocrystalline
silicon is insulative below 100.degree. C. and becomes conductive above
100.degree. C. Accordingly where the construction is used above
100.degree. C., a projection whose underlying substrate is entirely formed
of silicon loses its electrical isolation. Coating the projection with an
insulating layer as described above eliminates this potential problem.
Aspects of the invention are also believed applicable in providing
electrical interconnection over a step in semiconductor processing
regardless of the presence of a pillar. This is described with reference
to FIGS. 10-16. Referring first to FIG. 10, a wafer fragment processed in
accordance with this aspect of the invention is indicated generally by
reference numeral 50. Such includes a substrate 51, a step 52 defining a
base substrate surface 54 and an adjacent elevated surface 56, and a step
wall 53. Elevated surface 56 is spaced from base surface 54 by a first
distance "F". A base layer 58 of photoresist of the same preferred
properties of the photoresist of layer 30 in the first described
embodiment is provided over substrate base surface 54 to a first thickness
"G", with "G" being less than "F". Such preferably leaves elevated surface
56 free of photoresist.
Refereeing to FIG. 11, a base layer 60 of electrically conductive material
is provided over elevated surface 56, step wall 53 and base photoresist
layer 58. Layer 60 preferably comprises metal.
Referring to FIG. 12, base photoresist layer 58 is removed by a
conventional lift-off technique which also removes portions of conductive
layer 60 overlying photoresist layer 58. The resulting process leaves
elevated surface 56 covered with a capping layer 62 of base electrically
conductive material which is electrically isolated from adjacent substrate
base surface 54. Cap 62 has a top portion 64 and a side portion 66, with
side portion 66 extending downwardly along step wall 53 toward but not to
substrate base surface 54.
Referring to FIG. 13, an interconnecting layer 68 of electrically
conductive material is provided over the underlying substrate and capping
layer 62 to a second maximum thickness "H". Material of layer 68
preferably comprises metal, and is chosen to be selectively etchable
relative to conductive material of base electrically conductive cap 62.
Referring to FIG. 14, a masking layer 70 of photoresist is provided over
interconnecting layer 68 to a third maximum thickness "I". Second
thickness "H" and third thickness "I" have a sum thickness "J" which is
greater than first thickness "G". Again, the photoresist of layer 70 is
preferably of a higher viscosity than the photoresist of layer 58.
Photoresist layer 70 would then be patterned for formation of an
interconnecting material conductive line which extends from side portions
of capping layer 62. After such patterning, exposed interconnecting
material from layer 68 would be etched from capping layer 62 and
underlying substrate, as shown in FIG. 15, to define a conductive line 72
which electrically engages side portion 66 of capping layer 62.
Photoresist would subsequently be removed, as shown in FIG. 16.
In compliance with the statute, the invention has been described in
language more or less specific as to structural and methodical features.
It is to be understood, however, that the invention is not limited to the
specific features shown and described, since the means herein disclosed
comprise preferred forms of putting the invention into effect. The
invention is, therefore, claimed in any of its forms or modifications
within the proper scope of the appended claims appropriately interpreted
in accordance with the doctrine of equivalents.
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