A zigzag scanning address generator includes a row address generator for generating a row address signal which stops, increases or decreases a present state in response to an enabling signal, and a column address generator for generating a column address signal which stops, increases or decreases a present state in response to the enabling signal. Therefore, the zigzag scanning address generator can generate zigzag scanning addresses according to a zigzag scanning method, simplifying the circuit configuration needed for generating the address signals corresponding to the zigzag scanning pattern.
A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
In an apparatus for displaying image data created by a computer according to the random-scan system, until the created display data is read out and displayed, in the time of buffering a buffer memory for temporarily storing the display data, the data is divided into plural blocks based on the display coordinate information added to the display data and is thus stored. When reading the data, the data is read out and displayed in sequence from blocks adjacent to each other.
Methods and systems for generating alternate and zigzag address scans in a reconfigured two-dimensional map under the MPEG-1 and MPEG-2 are provided. In one embodiment, a control signal generator determines the subsequent alternate address based on the present alternate address. In another embodiment, the control signal generator determines the subsequent zigzag address based on the present zigzag address. The subsequent address is generated by incrementing, decrementing, or resetting a pair of up/down counters that are coupled to the inputs of the control signal generator.
A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
A photographic and video image system for transforming an image on a frame of a photographic film includes a structure in the overall form of a photographic printer having an image transformation element that transforms an optical image from the film into a video signal, a frame position indicator, which can be a hole or an optical or magnetic signal, is recorded on the film along with aspect information relating to the size of the frame exposed on the film. The frame position indicator and aspect information are detected and used to control a film feeding operation and the optical image to video signal transformation operation. The user of the system can record order information on the film that is used to specify the aspect of the resultant photographic print, as well as the quantity of prints to be made. Such order information can be superimposed as a menu on a displayed video signal at the time the video signal is reviewed prior to producing a photographic print.
