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Microprocessor with an external command mode for diagnosis and debugging    
United States Patent5479652   
Link to this pagehttp://www.wikipatents.com/5479652.html
Inventor(s)Dreyer; Robert S. (Sunnyvale, CA); Alpert; Donald B. (Santa Clara, CA); Modi; Nimish H. (San Jose, CA); Tripp; Mike J. (Forest Grove, OR)
AbstractA microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-driven instruction path. A multiplexer is provided that selects which of the instruction paths is actually supplied to the execution unit. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents. Any instruction executable by the execution unit is executable in the external command mode. Because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. The present invention is implemented with a conventional test access port designed in accordance with the IEEE 1149.1 boundary scan standard, with modification to include an instruction register, a data register, and control logic. The external command mode is applicable to single and multiple pipeline processors. The circuit described herein includes several selectors for selecting between the probe mode and the processor-driven mode of operation, including an external pin, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin is provided to indicate when the execution unit is ready to accept an instruction in the probe model.
   














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Drawing from US Patent 5479652
Microprocessor with an external command mode for diagnosis and debugging - US Patent 5479652 Drawing
Microprocessor with an external command mode for diagnosis and debugging
Inventor     Dreyer; Robert S. (Sunnyvale, CA); Alpert; Donald B. (Santa Clara, CA); Modi; Nimish H. (San Jose, CA); Tripp; Mike J. (Forest Grove, OR)
Owner/Assignee     Intel Corporation (Santa Clara, CA)
Patent assignment
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Publication Date     December 26, 1995
Application Number     08/327,229
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     October 21, 1994
US Classification     714/30 712/43 712/227 714/32
Int'l Classification     G06F 011/34
Examiner     Beausoliel Jr.; Robert W.
Assistant Examiner     Decady; Albert
Attorney/Law Firm     Blakely, Sokoloff, Taylor & Zafman
Address
Parent Case     This is a continuation of application Ser. No. 07/874,642, filed Apr. 27, 1992 now abandoned.
Priority Data    
USPTO Field of Search     371/15.1 371/16.1 371/19 371/22.1 364/265.6 364/267.91 395/575
Patent Tags     microprocessor external command mode diagnosis debugging
   
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 Technical Review Submit all comments and votes
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What is claimed is:

1. A computer circuit for operating in a processor-driven mode responsive to a series of stored macroinstructions from a computer memory, and also for operating in an external command mode responsive to an externally supplied microinstruction and an externally supplied command, comprising:

a mode selection unit for selecting the external command mode or the processor-driven mode;

an execution unit for executing microinstructions;

a microinstruction multiplexer for providing a selected microinstruction to the execution unit;

a processor-driven instruction path including a decoder for receiving and decoding said stored macroinstructions and decoding them into microinstructions which are then supplied to a first input of the microinstruction multiplexer;

an external instruction path for supplying an externally supplied microinstruction to a second input of the microinstruction multiplexer; and

a control circuit responsive to the mode selection unit for controlling the microinstruction multiplexer to select

during processor-driven operation, a microinstruction resulting from a decoded macroinstruction from the processor-driven instruction path, and

during external command mode operation, an externally supplied microinstruction from the external instruction path.

2. The computer circuit of claim 1 wherein the processor-driven instruction path comprises a decoder that updates the macroinstruction pointer coincident with decoding a macroinstruction.

3. The computer circuit of claim 1 wherein the external instruction path comprises an instruction register coupled to the microinstruction multiplexer, said instruction register for storing an externally supplied microinstruction.

4. The computer circuit of claim 1 wherein the mode selection unit includes a run/stop pin that, when asserted, halts operation of the processor-driven instruction path.

5. The computer circuit of claim 1 wherein the mode selection unit includes control logic, responsive to an externally supplied command, for halting operation of the processor-driven instruction path.

6. The computer circuit of claim 1 wherein the mode selection unit includes a probe mode control register that includes a