Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit

Claims

What is claimed is:

1. A circuit for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output capacitor coupled thereto for supplying current at a regulated voltage to a load, the control circuit comprising:

a first circuit for monitoring a signal from the output terminal to generate a first feedback signal;

a second circuit for generating a first control signal during a first state of circuit operation, the first control signal being responsive to the first feedback signal to vary the duty cycle of the switching transistors to maintain the output terminal at the regulated voltage; and

a third circuit for generating a second control signal during a second state of circuit operation to cause both switching transistors to be simultaneously OFF for a period of time if a sensed condition of the regulator indicates that the current supplied to the load falls below a threshold fraction of maximum rated output current for the regulator, whereby operating efficiency of the regulator at low output current levels is improved.

2. The circuit of claim 1 wherein the second control signal is generated in response to the first feedback signal.

3. The circuit of claim 2 wherein the circuit changes from the second to the first state of operation in response to the magnitude of the first feedback signal falling below a first threshold level.

4. The circuit of claim 3 wherein the circuit changes from the first to the second state of operation in response to the magnitude of the first feedback signal exceeding a second threshold level greater than the first threshold level.

5. The circuit of claim 4, wherein the first feedback signal is a voltage feedback signal and the third circuit includes a voltage comparator having hysteresis.

6. The circuit of claim 5, wherein the current consumed by the switching voltage regulator is reduced during the second state of operation.

7. The circuit of claim 1, wherein the second circuit includes:

a one-shot circuit for generating first and second levels of the first control signal during a switch cycle, wherein the first level causes the switch circuit to couple the input voltage to a node of the output circuit, and the second level causes the switch circuit to couple the node of the output circuit to ground.

8. The circuit of claim 7, wherein the second level is generated for a predetermined time period.

9. The circuit of claim 8, wherein the second circuit includes a fourth circuit for monitoring the current supplied to the output terminal to generate a current feedback signal.

10. The circuit of claim 9, wherein the switch is adapted to be coupled to an inductor and the fourth circuit monitors the inductor current to generate the current feedback signal.

11. The circuit of claim 10, wherein the fourth circuit compares the current feedback signal to a reference current value and triggers the one-shot circuit when the current feedback signal exceeds the reference current value.

12. The circuit of claim 11, wherein the fourth circuit includes a current comparator for triggering the one-shot circuit, the current comparator having a first input coupled to receive the current feedback signal and a second input coupled to a current source for providing the reference current value.

13. The circuit of claim 12, wherein the current source includes:

a transconductance amplifier supplying a current substantially proportional to the difference in voltage between the first feedback signal and a constant voltage; and

a constant current source coupled in parallel with the transconductance amplifier.

14. The circuit of claim 7, wherein second level is generated for a time period dependent upon the input voltage.

15. The circuit of claim 14, wherein the switch is coupled to an inductor, and wherein the second level is generated for a time period that is decreased in response to a decrease in the input voltage, whereby the oscillation frequency of the ripple current through said inductor is increased from an audible frequency to one that does not generate substantial user noise.

16. The circuit of claim 7, wherein the second level is generated for a time period that is dependent upon the voltage at the load.

17. The circuit of claim 16, wherein the switch is coupled to an inductor, and wherein the second level is generated for a time period that is increased in response to a decrease in the voltage at the load, whereby the total decrease in current through said inductor during the time period the second level is generated remains substantially constant.

18. The circuit of claim 7, wherein the one-shot circuit is maintained substantially OFF during the second state of operation, whereby the efficiency of the switching regulator circuit is increased as the circuit changes from the first to the second state of operation.

19. The circuit of claim 12, wherein the current comparator is maintained substantially OFF during the second state of operation, whereby the efficiency of the switching regulator circuit is increased as the circuit changes from the first to the second state of operation.

20. The circuit of claim 1, wherein the third circuit includes a user-activated switch and wherein the second control signal is generated in response to activation of the user switch.

21. The circuit of claim 20, wherein:

the second circuit includes a transconductance amplifier supplying a current substantially proportional to the difference in voltage between the feedback signal and a constant voltage during the first state of operation; and

wherein activation of the user switch introduces hysteresis into the transconductance amplifier.

22. The circuit of claim 20, wherein the second circuit includes:

a one-shot circuit for generating first and second levels of the first control signal during a switch cycle, wherein the first level causes the switch circuit to couple the input voltage to a node of the output circuit, and the second level causes the switch circuit to couple the node of the output circuit to ground.

23. The circuit of claim 22, wherein the second level is generated for a predetermined time period.

24. The circuit of claim 23, wherein the second circuit includes a fourth circuit for monitoring the current supplied to the output terminal to generate a current feedback signal.

25. The circuit of claim 24, wherein the fourth circuit compares the current feedback signal to a reference current value and triggers the one-shot circuit when the current feedback signal exceeds the reference current value.

26. The circuit of claim 22, wherein the second level is generated for a time period that is dependent upon the input voltage.

27. The circuit of claim 26, wherein the switch is coupled to an inductor, and wherein the second period of time is decreased in response to a decrease in the input voltage, whereby the oscillation frequency of the ripple current through said inductor is increased from an audible frequency to one that does not generate substantial user noise.

28. The circuit of claim 22, wherein the second level is generated for a time period that is dependent upon the voltage at the load.

29. The circuit of claim 28, wherein the switch is coupled to an inductor, and wherein the second level is generated for a time period that is increased in response to a decrease in the voltage at the load, whereby the total decrease in current through said inductor during the time period the second level is generated remains substantially constant.

30. The circuit of claim 22, wherein the one-shot circuit is maintained substantially OFF during the second state of operation, whereby the efficiency of the switching regulator circuit is increased as the circuit changes from the first to the second state of operation.

31. The circuit of claim 1, wherein the circuit is adapted for controlling a switching voltage regulator circuit having first and second switching transistors coupled in series between an input voltage and ground, wherein the first and second switching transistors are commonly coupled to the output circuit, and wherein the input voltage is higher than the voltage at the load, whereby the switching voltage regulator is a step-down voltage regulator.

32. The circuit of claim 1, wherein the circuit is adapted for controlling a switching voltage regulator circuit wherein the input voltage is lower than the voltage at the load, whereby the switching voltage regulator is a step-up voltage regulator.

33. The circuit of claim 1, wherein the circuit is adapted for controlling a switching voltage regulator circuit wherein the input voltage has an opposite polarity than the voltage at the load, whereby the switching voltage regulator is a polarity-inversing voltage regulator.

34. A circuit for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output capacitor coupled thereto for supplying current at a regulated voltage to a load, the control circuit comprising:

a first means for generating a voltage feedback signal indicative of the voltage at the output;

a second means for generating a first control signal during a first state of circuit operation, the first control signal being responsive to the voltage feedback signal to vary the duty cycle of the switching transistors to maintain the output terminal at the regulated voltage; and

a third means for generating a second control signal during a second state of circuit operation to cause both switching transistors to be simultaneously OFF for a period of time if a sensed condition of the regulator indicates that the current supplied to the load falls below a threshold fraction of maximum rated output current for the regulator, the period of time having a duration which is a function of the current supplied to the load by the regulator.

35. The circuit of claim 34, wherein the third means includes a voltage comparator having hysteresis.

36. The circuit of claim 34, wherein the second means includes:

a one-shot circuit for generating first and second levels of the first control signal during a switch cycle, wherein the first level causes the switch circuit to couple the input voltage to a node of the output circuit, and the second level causes the switch circuit to couple the node of the output circuit to ground.

37. The circuit of claim 36, wherein the second means includes a fourth means for monitoring the current supplied to the output terminal to generate a current feedback signal.

38. The circuit of claim 37, wherein the fourth means compares the current feedback signal to a reference current value and triggers the one-shot circuit when the current feedback signal exceeds the reference current value.

39. The circuit of claim 38, wherein the fourth means includes a current comparator for triggering the one-shot circuit, the current comparator having a first input coupled to receive the current feedback signal and a second input coupled to a current source for providing the reference current value.

40. The circuit of claim 39, wherein the current source includes:

a transconductance amplifier supplying a current substantially proportional to the difference in voltage between the feedback signal and a constant voltage; and

a constant current source coupled in parallel with the transconductance amplifier.

41. A method for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output capacitor coupled thereto for supplying current at a regulated voltage to a load, the method comprising the steps of:

(a) monitoring a signal from the output terminal to generate a first feedback signal;

(b) varying the duty cycle of the switching transistors in response to the first feedback signal to maintain the output terminal at the regulated voltage during a first state of circuit operation;

(c) turning both switching transistors simultaneously OFF for a period of time during a second state of circuit operation following the first state of circuit operation, so as to allow the output capacitor to maintain the output substantially at the regulated voltage by discharging during the second state of circuit operation, the period of time beginning when the current supplied to the load falls below a threshold fraction of maximum rated output current for the regulator, and having a duration which is a function of the current supplied to the load by the regulator; and

(d) turning at least one of said switching transistors ON to recharge the output capacitor following the second state of circuit operation.

42. The method of claim 41, wherein the switching voltage regulator includes a one-shot circuit for varying the duty cycle of the switching transistors and wherein step (c) includes the step of maintaining the one-shot circuit substantially OFF during the second state of operation.

43. The method of claim 2, wherein the switching voltage regulator includes a current comparator for triggering the one-shot circuit and wherein step (c) includes the step of maintaining the current comparator substantially OFF during the second state of operation.

44. A circuit for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output inductor coupled thereto for supplying current at a regulated voltage to a load, the circuit comprising:

a first circuit for monitoring a signal from the output terminal to generate a first feedback signal;

a second circuit for generating a first control signal during a first state of circuit operation, the first control signal being responsive to the first feedback signal to vary the duty cycle of the switching transistors to maintain the output terminal at the regulated voltage; and

a third circuit for monitoring the current to the output terminal to generate a second control signal during a second state of circuit operation when the monitored current compares in a predetermined manner to a threshold indicative of a polarity reversal condition in the output inductor, said second state causing one of said switching transistors to be maintained OFF, such that the switch circuit is prevented from coupling the output circuit to ground.

45. The circuit of claim 44 wherein the third circuit monitors the current through the inductor to generate the second control signal when the magnitude of the inductor current falls below the current threshold.

46. The circuit of claim 44 wherein the third circuit prevents reversals in polarity of the current through the inductor.

47. The circuit of claim 46, wherein the first feedback signal is a voltage feedback signal and the third circuit includes a current comparator for comparing the monitored current to the current threshold.

48. The circuit of claim 47, wherein the current consumed by the switching voltage regulator is reduced during the second state of operation.

49. The circuit of claim 44, wherein the second circuit includes:

a one-shot circuit for generating first and second levels of the first control signal during a switch cycle, wherein the first level causes the switch circuit to couple the input voltage to a node of the output circuit, and the second level causes the switch circuit to couple the node of the output circuit to ground.

50. The circuit of claim 49, wherein the second level is generated for a predetermined time period.

51. A method for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output inductor coupled thereto for supplying current at a regulated voltage to a load, the method comprising the steps of:

(a) monitoring a signal from the output terminal to generate a first feedback signal;

(b) varying the duty cycle of the switching transistors in response to the first feedback signal to maintain the output terminal at the regulated voltage during a first state of circuit operation, wherein the current to the load has a polarity; and

(c) maintaining one of said switching transistors OFF for a period of time following the first state of circuit operation to de-couple the output circuit from ground during the period of time so as to prevent the current to the load from reversing polarity.

52. The method of claim 51 wherein step (c) includes step (d) of monitoring the current to the output terminal and detecting when the current falls below a current threshold.

53. The method of claim 52 wherein step (d) includes monitoring the current through the inductor.

54. The circuit of claim 53, wherein the current consumed by the switching voltage regulator is reduced during the second state of operation.

55. A circuit for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output capacitor coupled thereto for supplying current at a regulated voltage to a load, the control circuit comprising:

drive circuitry for the pair of synchronously switched switching transistor;

feedback circuitry, coupled to the drive circuitry to control the duty cycle of the pair of synchronously switched switching transistors, the feedback circuitry forming a feedback path in the regulator between the output circuit and the drive circuitry by which feedback information indicative of the current supplied to the load by the regulator conditions the duty cycle of the pair of synchronously switched switching transistors; and

logic circuitry, coupled to the feedback circuitry and the drive circuitry, which prevents the drive circuitry from turning on either of the pair of synchronously switched switching transistors if the feedback information indicates that the current supplied to the load by the regulator falls below selected sleep mode current level, wherein the synchronously switched switching transistors are prevented from being turned on for a period of time that is a function of the current supplied to the load by the regulator.

56. The circuit of claim 55 wherein:

the output circuit includes an inductor coupled to the pair of synchronously switched switching transistors and the output terminal;

the feedback information includes a first feedback signal derived by sensing current conducted between the inductor and the output terminal and a second feedback signal derived by sensing voltage at the output terminal; and

the feedback circuitry includes a comparator circuit that compares the first feedback signal to an error signal generated from the second feedback signal to control switching between the pair of synchronously switched switching transistors, and a threshold circuit that sets a minimum inductor current value at which the drive circuitry switches between transistors.

57. An improved circuit for controlling a switching voltage regulator, the regulator having (1) a switch circuit coupled to receive an input voltage and including a pair of synchronously switched switching transistors and (2) an output circuit including an output terminal and an output capacitor coupled thereto for supplying current at a regulated voltage to a load, and wherein the control circuit varies the duty cycle of the switching transistors to maintain the output terminal at the regulated voltage, the improvement comprising:

circuitry incorporated in the control circuit for detecting a condition in the output circuit indicative of the current supplied to the load falling below a threshold fraction of maximum rated output current for the regulator and for turning off both switching transistors simultaneously for a period of time if the supplied current falls below the threshold, the period of time having a duration which is a function of the current supplied to the load by the regulator.

BACKGROUND OF THE INVENTION

The present invention relates to a switching regulator circuit. More particularly, the present invention relates to a control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit.

The purpose of a voltage regulator is to provide a predetermined and constant output voltage to a load from a poorly-specified and fluctuating input voltage source. Generally, there are two different types of regulators: series regulators and switching regulators.

The series regulator employs a pass element (e.g., a power transistor) coupled in series with a load and controls the voltage drop across the pass element in order to regulate the voltage which appears at the load. In contrast, the switching regulator employs a switch (e.g., a power transistor) coupled either in series or parallel with the load. The regulator controls the turning ON and turning OFF of the switch in order to regulate the flow of power to the load. The switching regulator employs inductive energy storage elements to convert the switched current pulses into a steady load current. Thus, power in a switching regulator is transmitted across the switch in discrete current pulses, whereas in a series regulator, power is transmitted across the pass element as a steady current flow.

In order to generate a stream of current pulses, switching regulators typically include control circuitry to turn the switch on and off. The switch duty cycle, which controls the flow of power to the load, can be varied by a variety of methods. For example, the duty cycle can be varied by either (1) fixing the pulse stream frequency and varying the ON or OFF time of each pulse, or (2) fixing the ON or OFF time of each pulse and varying the pulse stream frequency.

Which ever method is used to control the duty cycle, switching regulators are generally more efficient than series regulators. In series regulators, the pass element is generally operated in its linear region where the pass element conducts current continuously. This results in the continuous dissipation of power in the pass transistor. In contrast, in switching regulators, the switch is either OFF, where no power is dissipated by the switch, or ON in a low impedance state, where a small amount of power is dissipated by the switch. This difference in operation generally results in reduced amounts of average power dissipation in switching regulators.

The above difference in efficiency can be more apparent when there is a high input-output voltage difference across the regulator. For example, it would not be unusual for a series regulator to have an efficiency of less than 25 percent when a switching regulator could perform an equivalent function with an efficiency of greater than 75 percent.

Because of their improved efficiency over series regulators, switching regulators are typically employed in battery-operated systems such as portable and laptop computers and hand-held instruments. In such systems, when the switching regulator is supplying close to the rated output current (e.g., when a disk or hard drive is ON in a portable or laptop computer), the efficiency of the overall circuit can be high. However, the efficiency is generally a function of output current and typically decreases at low output current. This reduction in efficiency is generally attributable to the losses associated with operating the switching regulator. These losses include, among others, quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses and inductor/transformer winding and core losses.

The reduction in efficiency of a switching regulator at low output current can become important in battery-operated systems where maximizing battery lifetime is desirable.

In view of the foregoing, it would be desirable to provide a high efficiency switching regulator.

It would also be desireable to provide a control circuit and method for maintaining high efficiency over broad current ranges, including low output currents, in a switching regulator circuit.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a high efficiency switching regulator.

It is also an object of the present invention to provide a control circuit and method for maintaining high efficiency over broad current ranges, including low output currents, in a switching regulator circuit.

In accordance with these and other objects of the invention, there is provided a circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn the one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor (e.g., during low output currents). During such periods of time, the load does not consume power from the input power source. Therefore, the regulator efficiency is increased. If desired, other components in the switching regulator, in addition to switching transistors, can also be intentionally held OFF to conserve additional power. This additional feature of the present invention can further increase the efficiency of the overall regulator circuit.

The circuit and method of the present invention can be used to control various types of switches in switching regulator circuits, including switches that use either one or more power transistors. Additionally, the circuit and method can be used to control switches in various types of switching regulator configurations, including voltage step-down, voltage step-up and polarity-inversing configurations.

Additionally, the circuit and method of the present invention can vary the OFF time of the switching transistor in response to the input and output voltages of the switching regulator. This feature of the present invention reduces the emission of audible noise from the switching regulator during low input voltage conditions. It also reduces the potential for current runaway during short circuits in the output voltage for some regulator configurations.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is a schematic block diagram of a typical prior art switching regulator circuit employing a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 2 is a schematic block diagram of a switching regulator circuit incorporating a first embodiment of the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 3 is a schematic block diagram of a switching regulator circuit incorporating a second embodiment of the high-efficiency control circuit of the present invention to drive a switch including a switching MOSFET and a switching diode in a step-down configuration;

FIG. 4 is a schematic block diagram of a switching regulator circuit incorporating a "user-activated" embodiment of the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 5 is a schematic block diagram of a switching regulator circuit incorporating the variable OFF-time control circuit of the present invention;

FIG. 6 is a detailed schematic diagram of an embodiment of the variable OFF-time control circuit of FIG. 5;

FIG. 7 is a detailed schematic block diagram of an exemplary switching regulator circuit incorporating both the variable OFF-time feature and the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 8 is a schematic block diagram of a switching regulator circuit incorporating a circuit of the present invention for preventing reversals in the polarity of the current in the output inductor of the regulator from drawing power from the load;

FIG. 9 is a schematic block diagram of a switching regulator circuit incorporating the high-efficiency control circuit of the present invention in a step-up configuration; and

FIG. 10 is a schematic block diagram of a switching regulator circuit incorporating the high-efficiency control circuit of the present invention in a polarity-reversing configuration.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of a typical prior art switching regulator circuit employing a push-pull switch in a step-down configuration.

Referring to FIG. 1, circuit 10 is used to provide a regulated DC output voltage V.sub.OUT at terminal 12 (e.g., 5 volts) for driving load 14 which, for example, may be a portable or laptop computer or other battery-operated system. Circuit 10 operates from an unregulated supply voltage V.sub.IN coupled to terminal 14 (e.g., a 12 volt battery). Circuit 10 includes push-pull switch 15, driver circuit 20, output circuit 30 and control circuit 35.

Driver circuit 20 is used to drive push-pull switch 15 which includes two synchronously-switched power MOSFETS 16 (p-channel) and 17 (n-channel) stacked in series between supply rail V.sub.IN and ground. Push-pull switch 15 in conjunction with driver circuit 20 is typically referred to as a "half-bridge" configuration. MOSFETS 16 and 17 are used to alternately supply current to output circuit 30 which includes inductor 32 (L1) and output capacitor 34 (C.sub.OUT). Output circuit 30 smooths the alternating supply of current so that load 12 is provided a regulated voltage V.sub.OUT. In order to supply the alternating current, MOSFETS 16 and 17 are respectively driven by P-channel driver 26 and N-channel driver 27, which in turn are both controlled by control circuit 35.

Control circuit 35 includes one-shot circuit 25 which provides an OFF pulse of constant duration (e.g., 2 to 10 microseconds) during which time MOSFET 16 is held OFF and MOSFET 17 is held ON by drivers 26 and 27, respectively. Otherwise, one-shot circuit 25 provides an ON pulse during which time MOSFET 16 is held ON and MOSFET 17 is held OFF. Therefore, one-shot circuit 25 alternately turns MOSFETS 16 and 17 ON and OFF to provide an alternating supply of current to (output circuit 30. The duty cycle of the one-shot circuit 35 is in turn controlled by current amplifier 39.

Control circuit 35 monitors the output voltage V.sub.OUT through resistor-divider network R.sub.1 /R.sub.2 (36A/36B) to provide a feedback voltage V.sub.FB proportional to the output voltage V.sub.OUT. Control circuit 35 also monitors the current I.sub.L through inductor L1 to provide a feedback current I.sub.FB proportional to inductor current I.sub.L. Circuit 10 operates by controlling inductor current I.sub.L so that the feedback voltage V.sub.FB is regulated to be substantially equal to a reference voltage V.sub.REF provided by reference circuit 37. With feedback voltage V.sub.FB being regulated, the output voltage V.sub.OUT is in turn regulated to a higher voltage by the ratio of (R.sub.1 +R.sub.2) to R.sub.2.

Transconductance amplifier 38 is used to compare the feedback voltage V.sub.FB to a reference voltage V.sub.REF. Circuit 10 regulates the output voltage V.sub.OUT as follows. During each cycle when switch 15 is "ON", P-MOSFET 16 is turned ON and the current I.sub.L in inductor L1 ramps up at a rate dependent on V.sub.IN -V.sub.OUT. When I.sub.L ramps up to a threshold level set by output 38A of transconductance amplifier 38, current comparator 39 trips and triggers the one-shot OFF pulse, initiating the "OFF" cycle of switch 15. During the "OFF" cycle, one-shot circuit 25 holds P-MOSFET 16 OFF and turns N-MOSFET 17 ON. This in turn causes the current I.sub.L in inductor L1 to ramp down at a rate dependent on V.sub.OUT. Thus, the duty cycle of the periodic turning OFF of switch 15 is controlled so the current I.sub.L produces a regulated output voltage V.sub.OUT at terminal 12.

As the output load current increases, the voltage drop across R.sub.2 resistor 36B will decrease. This translates into a small error voltage at input 38B of transconductance amplifier 38 that will cause output 38A to increase, thus setting a higher threshold for current comparator 39. Consequently, current I.sub.L in inductor L1 is increased to the level required to support the load current.

Since the OFF time (t.sub.OFF) of one-shot circuit 25 is constant, switching regulator circuit 10 has a constant ripple current in inductor L1 (for constant output voltage V.sub.OUT), but has a frequency which varies with V.sub.IN. The ripple oscillation frequency is given by the equation:

f.sub.RIP =(1/t.sub.OFF) [1-(V.sub.OUT /V.sub.IN)]

One disadvantage of circuit 10 in FIG. 1 is that the ripple oscillation frequency f.sub.RIP may decrease to an audible level with low input voltages V.sub.IN. This could occur, for example, when a battery powering the switching regulator circuit is nearly discharged. Inductor L1 may then generate and emit noise that can be objectionable to a user of the device employing the regulator circuit.

An additional disadvantage of prior art circuit 10 is that the inductor current I.sub.L is not well controlled when the output voltage V.sub.OUT is shorted to ground. The basic relationship between inductor current and voltage is given by the equation di/dt=V/L. This means that the rate at which current I.sub.L in inductor L1 decays during the OFF-time depends on the voltage across inductor L1, which is the sum of V.sub.OUT and the drain to source voltage, V.sub.DS, of N-MOSFET 17. During a short, V.sub.OUT approaches zero while V.sub.DS is also very low, resulting in very little decay of current I.sub.L in inductor L1 during t.sub.OFF. However, following each OFF cycle, P-MOSFET 16 is turned back ON until current comparator 39 again trips one-shot constant OFF time control circuit 25. Even for the minimum time that P-MOSFET 16 is ON, the current I.sub.L in inductor L1 may increase by more than it can decrease during t.sub.OFF. This may result in a runaway condition in which the short circuit current may reach destructive levels.

A further disadvantage of prior art circuit 10 results from the constant ripple current in inductor L1. During t.sub.OFF, current I.sub.L in inductor L1 always ramps down by the same amount regardless of the output current of the regulator. At low output currents this can cause the current in inductor L1 to reverse polarity and, thus, pull power from the load. During the following ON cycle, this current again ramps positive such that the average inductor current equals the load current. Losses associated with this constant ripple current, along with switching losses due to the charging and discharging of switch 15's MOSFET gates, can produce large reductions in efficiency at low output currents. This will be especially the case if the current in inductor L1 reverses and power is pulled from the load to ground through N-MOSFET 17.

A still further disadvantage of prior art circuit 10 concerns the gate drives to P-MOSFET 16 and N-MOSFET 17. Delays are generally incorporated into drivers 26 and 27 to ensure that one power MOSFET turns OFF before the other turns ON. If there is insufficient deadtime between the conduction of the two MOSFETs (due to, for example, device, circuit processing, or temperature variations), current will be passed directly from input supply V.sub.IN to ground. This "shoot-through" effect can dramatically reduce efficiency, and in some circumstances, can overheat and destroy the power MOSFETs.

FIG. 2 is a schematic block diagram of a switching regulator circuit incorporating a first embodiment of the high-efficiency control circuit of the present invention for driving a switch including a pair of synchronously-switched MOSFETs in a step-down configuration.

Switching regulator circuit 50 includes push-pull switch 15, driver circuit 20 and output circuit 30 similar to those of FIG. 1. Circuit 50 also includes an embodiment 70 of the high-efficiency control circuit of the present invention.

Control circuit 70 includes one-shot circuit 25, current comparator 39 and amplifier 38 similar to those of FIG. 1. However, in addition to those components, control circuit 70 also includes constant current source I.sub.1 72 and hysteretic comparator 74 for providing high efficiency operation at low average current levels.

As will be discussed in greater detail below, constant current source I.sub.1 72 and comparator 74 allow push-pull switch 15 to go into a state of operation where both MOSFETS 16 and 17 are simultaneously OFF under conditions where the output voltage V.sub.OUT can be maintained substantially at the regulated voltage V.sub.REG by output capacitor C.sub.OUT. This state of operation is referred to herein as a "sleep mode." The ability of push-pull switch 15 to go into such a sleep mode is in contrast to the regulator circuit of FIG. 1 where one of the two MOSFETs 16 and 17 is substantially ON at all times. This feature of the present invention reduces the regulator circuit power consumption since push-pull switch 15 does not dissipate power or allow power to be pulled from load R.sub.L to ground in sleep mode.

Furthermore, if desired, while push-pull switch 15 is in the above-described sleep mode, the regulator circuit can turn OFF other circuit components which are not needed while the regulator is in sleep mode. For example, for the embodiment of the present invention shown in FIG. 2, one-shot circuit 25, current comparator 39, current source I.sub.1 72 and amplifier 38 can also be turned OFF in sleep mode. This feature of the present invention allows the regulator circuit to operate at even higher efficiencies than otherwise possible if only push-pull switch 15 were maintained in a sleep mode.

At high load current levels (e.g., greater than 20 percent of the maximum rated output current) control circuit 70 operates similar to control circuit 35 of FIG. 1. In FIG. 2, the current feedback I.sub.FB is again provided to the non-inverting input of current comparator 39. Offset V.sub.OS 76, which preferably is built into amplifier 38, level-shifts feedback voltage V.sub.FB slightly below reference voltage V.sub.REF, thus keeping the output of hysteretic comparator 74 high during high current conditions. When the feedback current I.sub.FB exceeds the current supplied to the inverting input of current comparator 39, the output of comparator 39 goes HIGH so as to initiate the switch "OFF" cycle.

During the "OFF" cycle, output 25A of one-shot circuit 25 is HIGH, which turns P-MOSFET 16 OFF and N-MOSFET 17 ON. After a constant time set by one-shot circuit 25, output 25A goes LOW, thus initiating the next "ON" cycle where P-MOSFET 16 ON and N-MOSFET 17 OFF.

In accordance with the present invention, regulator circuit 50 goes into sleep mode at low output current levels as follows. Hysteretic comparator 74 monitors the feedback voltage V.sub.FB and goes LOW when V.sub.FB exceeds a predetermined voltage value in excess of the reference voltage V.sub.REF. Such a condition is indicative of the output voltage V.sub.OUT exceeding a predetermined voltage value in excess of the regulated voltage V.sub.REG. This over voltage condition is intentionally induced at low average output currents by providing a constant current source I.sub.1 72 coupled in parallel with amplifier 38. During the over voltage condition both MOSFETS 16 and 17 are maintained OFF by way of AND gate 66 and NAND gate 68.

Constant current source I.sub.1 sets a minimum feedback current threshold for current comparator 39. This sets a minimum current required in inductor L1 during each ON cycle to trip comparator 39. In accordance with the present invention, current comparator 39 is intentionally forced t