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Claims  |
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I claim:
1. A multi-level electrical assembly for coupling at least one integrated
circuit having a plurality of electrically conductive leads to at least
one attachment area of a circuit board comprising:
(a) an electrically insulating pin holder having a plurality of
electrically conductive receiving devices configured to receive leads of
an integrated circuit;
(b) a plurality of electrically conductive pins held by the pin holder
parallel to each other, perpendicular with the pin holder, and in a
pattern predetermined so as to align with receptacles of a circuit board,
each of which pins is attached to a receiving device;
(c) an interconnect board disposed generally parallel to the pin holder,
including an electrically insulating substrate having a top surface, a
flat bottom surface, and at least one buried intermediate surface and
having an array of holes arranged in the same predetermined pattern, which
interconnect board is removable from the pins when the pins are not
attached to the receptacles;
(d) an electrical component mounted on the interconnect board;
(e) a metallized surface formed on one of the surfaces of the substrate
that is nearly completely covered with a layer of metal;
(f) wherein surfaces inside selected of the holes are covered with metal so
as to form electrical contacts with pins extending through those selected
holes;
(g) wherein a subset of the in-hole electrical contacts are electrically
connected to the metallized surface; and
(h) a plurality of electrically conductive pathways, at least in part
passing through the metallized surface, at least some of which pathways
electrically couple the electrical component to at least some of the
receiving devices.
2. The assembly of claim 1 wherein the receiving devices comprise a socket
having a plurality of electrically conducting receptacles sized and
positioned to hold pins of an integrated circuit.
3. The assembly of claim 1 wherein the electrical component comprises a
voltage regulator.
4. The assembly of claim 1 wherein the pin holder is comprised of a plastic
material.
5. The assembly of claim 1 wherein at least some of the pathways couple the
electrical component to the majority of receiving devices.
6. The assembly of claim 1 wherein the interconnect board comprises three
cores, and wherein four electrically conductive patterns are present on
(a) the top surface of the board, (b) the bottom surface of the board, and
(c) two intermediate surfaces of the board.
7. The assembly of claim 1 wherein the interconnect board further comprises
a plurality of conductive vias connecting conductive material of at least
two layers.
8. The assembly of claim 1 further comprising a second electrical component
physically coupled to a surface of the interconnect board and electrically
coupled to the receptacles.
9. The assembly of claim 8 wherein the further electrical component
comprises an integrated circuit.
10. The assembly of claim 8 wherein the further electrical component
comprises a passive component.
11. The assembly of claim 10 wherein the further electrical component
comprises a capacitor.
12. The assembly of claim 1 further comprising a metallized area adjacent
to an edge of at least one of the layers so as to form a heat dissipation
structure.
13. The assembly of claim 1 further comprising at least one other pin held
by the pin holder parallel to the other pins, perpendicular with the pin
holder, and in alignment with a receptacle of a circuit board, but not
attached to a receiving device.
14. The assembly of claim 1 further comprising a plurality of shorter pins
held by the pin holder parallel to the other pins and perpendicular with
the pin holder, wherein the shorter pins each extend between a receiving
device and the top surface of the interconnect board.
15. The assembly of claim 1 further comprising a non-conducting pin carrier
supported adjacent to and parallel to the bottom surface of the
interconnect board and supporting a plurality of pins that terminate at
the bottom surface and are electrically coupled to pads on the bottom
surface.
16. The assembly of claim 1 further comprising a second metallized surface
formed on another of the surfaces of the substrate that is nearly
completely covered with a layer of metal.
17. The assembly of claim 16 wherein the electrical component has an input
and an output, wherein the input is connected to one of the metallized
surfaces, and wherein the output is connected to the other metallized
surface.
18. The assembly of claim 17 wherein one of the metallized surfaces defines
a high-voltage plane and the other metallized surface defines a
low-voltage plane.
19. The assembly of claim 18 wherein:
(a) the electrical component comprises a voltage regulator;
(b) at least some of the pathways couple the voltage regulator to the
majority of receiving devices, which pathways pass through the low-voltage
plane; and
(c) the interconnect board further comprises a plurality of conductive vias
connecting conductive material of at least two layers.
20. The assembly of claim 19 further comprising a third metallized area
defining a ground plane.
21. The assembly of claim 20 further comprising a fourth metallized area
adjacent to an edge of at least one of the layers so as to form a heat
dissipation structure.
22. The assembly of claim 19 further comprising a capacitor physically
coupled to a surface of the interconnect board and electrically coupled to
the voltage regulator and wherein:
(a) the receiving devices comprise a socket having a plurality of
electrically conducting receptacles sized and positioned to hold pins of
an integrated circuit;
(b) the pin holder is comprised of a plastic material; and
(c) the interconnect board comprises three cores, and wherein four
electrically conductive patterns including both metallized surfaces are
present on (i) the top surface of the board, (ii) the bottom surface of
the board, and (iii) two intermediate surfaces of the board.
23. The assembly of claim 19 further comprising at least one other pin held
by the pin holder parallel to the other pins, perpendicular with the pin
holder, and in alignment with a receptacle of a circuit board, but not
attached to a receiving device, wherein said other pin is connected to the
high-voltage plane but not the low-voltage plane.
24. The assembly of claim 19 further comprising a plurality of shorter pins
held by the pin holder parallel to the other pins and perpendicular with
the pin holder, wherein the shorter pins each extend between a receiving
device and the top surface of the interconnect board, and wherein the
low-voltage plane is on the top surface of the interconnect board.
25. The assembly of claim 19 further comprising a non-conducting pin
carrier supported adjacent to and parallel to the bottom surface of the
interconnect board and supporting a plurality of pins that terminate at
the bottom surface and are electrically coupled to pads on the bottom
surface, and wherein the high-voltage plane is on the bottom surface of
the interconnect board.
26. A multi-level electrical assembly for coupling at least one integrated
circuit to a circuit board comprising:
(a) pin carrier means for electrically and mechanically coupling the
assembly to an attachment area of a circuit board, including a plurality
of electrically conductive pins held in predetermined relative position by
an electrically insulating carrier;
(b) receiving means located on the top layer of the carrier for
electrically and mechanically coupling an integrated circuit to the pins;
and
(c) a multi-layer interconnect board positioned with a plurality of the
pins passing through it, including means for converting high-voltage power
on an input to lower-voltage power for the integrated circuit.
27. The assembly of claim 26 wherein the interconnect board contains at
least two metallized surfaces, one defining a high-voltage plane and the
other defining a low-voltage plane.
28. A method of coupling a low-voltage powered integrated circuit to an
attachment area of a circuit board designed for a higher-voltage powered
integrated circuit comprising:
(a) forming a pin carrier having a socket on one side and a plurality of
pins held perpendicularly to the pin carrier and extending from the other
side, wherein the socket is shaped so as to receive the lower-voltage
powered integrated circuit and electrically connected so as to conduct
leads of the circuit to the pins;
(b) forming a multi-layer interconnect board having a plurality of holes
positioned so as to permit a plurality of the pins to pass through the
interconnect board and having at least two mostly metallized areas on
different layers, one of which areas defines a low-voltage plane and a
second of which areas defines a high-voltage plane;
(c) forming electrical connections between each of the two planes and
selected of the pins extending through the interconnect board;
(d) mounting on the interconnect board a voltage regulator having an input
and an output, and electrically connecting the input of the voltage
regulator to the higher-voltage plane and the output of the voltage
regulator to the lower-voltage plane;
(e) placing the interconnect board over the pins and fastening the
interconnect board and the pin carrier together; and
(f) soldering the pins passing through the interconnect board to the
interconnect board.
29. The method of claim 28 wherein selected of the pins do not pass through
the interconnect board, wherein the surface of the interconnect board
nearest to the pin carrier includes the low-voltage plane, and further
comprising the act of soldering the pins that do not pass through the
interconnect board to the surface of the interconnect board nearest to the
pin carrier. |
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Claims |
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Description |
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NOTICE OF COPYRIGHT
A portion the disclosure this patent document contains material that is
subject to copyright protection. The copyright owner has no objection to
the facsimile reproduction by anyone the patent disclosure, as it appears
in the Patent and Trademark Office patent files or records, but otherwise
reserves all copyright rights.
BACKGROUND OF THE INVENTION
This invention relates to systems and methods for connecting integrated
circuits to circuit boards in a flexible and dense manner.
In a variety of situations, economic or functional considerations make it
desirable to alter the set of integrated circuits used on a circuit board,
such as in a personal or other computer. For example, it may become useful
to add a new integrated circuit or to replace or alter the packaging of an
existing integrated circuit. However, such changes are often difficult to
achieve, because computer circuit boards are typically pre-designed for a
particular set of integrated circuits. Thus, altering the set of
integrated circuits often requires a board redesign, which can result in
significant added costs, delays, or compatibility problems. Consequently,
manufacturers often forego changes to the chip set, even if they would
result in improved performance or reduce costs.
One particular instance in which it is desirable to use a different chip
set but in which the difficulties of redesigning the board stand as
obstacles, is the decision to alter the packaging of prepackaged,
mass-produced integrated circuits. During the lifetime of such a chip,
there may be several phases of packaging, and the best choice may also
change over time, as detailed below.
Mass-market prepackaged semiconductor chips often use pin grid array
("PGA") packages, which have metal leads extending from the bottom surface
of the package as rows of pins. The array of pins in PGA packages permits
a large number of leads, which is essential for complex circuits with high
input-output requirements. PGA packages typically allow more leads than
alternatives such as dual in-line packages (which have two rows of pins
along the edge of the package). A variety of PGA packages are described in
my U.S. Pat. No. 4,750,092, which is hereby incorporated by reference.
High-volume, complex, prepackaged semiconductor chips, such as
microprocessors, are typically introduced in a ceramic PGA package, even
though that package type is relatively costly. Although ceramics have
certain other advantages, such as good hermetic sealing, chip makers are
principally willing to suffer the cost penalty of ceramics in early stages
of chip sales because the packaged chip can be assembled onto circuit
boards by virtually all board designers.
As chip volumes increase and chip manufacturing costs drop, chip makers
generally look for ways to reduce the package cost. Often, they will begin
offering a packaging option of plastic surface-mounted geometry, such as
the plastic leaded chip carrier ("PLCC") or the plastic quad flat package
("PQFP"). Those surface-mounted packaging options can reduce the cost of
the package by perhaps 30-70%, which can result in a packaged circuit,
such as a microprocessor, that sells for 10-50% less than the
ceramic-PGA-packaged version.
Unfortunately, not all chip purchasers have the capability and desire to
take advantage of the lower-priced, plastic, surface-mounted packages.
Some lack the surface-mounting equipment or technical knowledge to use a
surface-mounted package. Others cannot or would not find it cost-effective
to redesign their circuit board to accommodate the different "footprint"
required by a surface-mounted package. Still others are discouraged by the
disadvantages of surface-mounting using surface-mount packages, such as
the cost of a fine-pitch socket (to which the surface-mounted package
might need to be attached), the complications that can arise in board
assembly when using surface-mounting for some circuits (as opposed to the
ease of through-hole mounting of PGA packages), or the difficulty in
testing installed surface-mounted circuits and replacing faulty ones.
No previously existing devices or methods exist to install the lower-cost
surface-mounted chips on a circuit board without altering the board layout
or increasing the difficulty of the installation and testing process from
that common to the use of PGAs. Previous packaging techniques, therefore,
have forced users incapable of surface mounting themselves to pay for the
higher-cost PGA-packaged semiconductors.
Another problem with previous packaging techniques has been the difficulty
in reliably assembling the package and affixing it to the circuit board,
and with inspecting the connections. It would be desirable to be able to
inspect the assembled device separately, before the circuit board is
completed. Those goals are difficult with surface-mount techniques,
because the packaged chip must be soldered directly to the circuit board,
which can be difficult both to accomplish and to inspect electrically
until the board is completed. PGA packages are easier to install because
they simply plug in the board, and they can be tested before installation
by plugging them into a test board. It has been difficult heretofore to
make and inspect, however, the contact between each pin and the conductive
pattern bonded out from the semiconductor chip.
Another instance in which it is desirable to use a different chip set but
in which the difficulties of redesigning the board stand as obstacles, is
the decision to add a coprocessor circuit, or another circuit that can be
used with an integrated circuit such as additional memory, to the existing
chip set. The optimal choice may change across a customer base or over
time, as described below.
It has been common to place the circuitry to perform certain functions in a
computer's CPU--typically functions that are not "core" ones or that may
be needed at varying levels of performance--on separate chips from the
microprocessor. Such chip, called "coprocessors," have commonly included
mathematical coprocessors or graphical coprocessors. Often, the end user
is permitted to purchase the coprocessor separately, if accelerated
performance or added functions are needed. It is not uncommon for some
users to select the coprocessor upon purchasing the computer, for others
to purchase and have it installed after purchase, and for yet others to
skip it entirely.
Such flexibility results in increased cost and trouble for the board
designer, though. If any subset of customers will demand the coprocessor,
the board designer must include a board location (typically a socket) for
it in the design of the circuit board. Designing in a socket is costly in
board space, particularly for a feature that only certain customers,
perhaps even a minority, will use. If some customers will demand the
coprocessor later on, it is not even possible to use two different board
designs, one with the coprocessor and the other without, but even if that
option were possible, it is costly. No current packaging or design
techniques permit a single design for both types of systems, those with
and those without coprocessors.
Another example of an instance in which it is desirable but difficult to
alter the chip set, is the desirability of providing sockets or circuit
board locations that are suitable for any of an interchangeable set of
components. For example, some boards can be upgraded to a higher-powered
microprocessor in a series merely by unplugging the old one and replacing
it with a new one. Previous techniques for achieving such compatibility,
however, have depended on the use by the chip maker of a common "pinout,"
where the pins on each of the interchangeable chips perform the same
function. A truly flexible interchangeable system would permit
compatibility with a wide variety of components, even ones with different
pinouts.
Yet another example of an instance in which it is desirable but difficult
to alter the chip set, is when an integrated circuit is replaced with an
equivalent component drawing lower power. Lower-power upgrades are
desirable because they create less heat, are less costly, and can run
faster. However, to date, switching to a lower-powered circuit has
required complete redesign of the circuit board, because associated
components must be redesigned to work with the lower power, too, and
because the changed circuit will not work in the originally designed
board. It would be desirable to create a system that permitted
lower-powered upgrades of an integrated circuit to be plug-compatible.
In addition, the invention has application in general circuit board design,
in which the problem is not increased flexibility, but increased circuit
density. Previous attempts to increase circuit board density by creating
circuit board modules supporting chip sets or multi-level circuit boards
have failed to produce reasonable-cost results. Common problems have
included the failure of such techniques to use standardized components or
the need for special materials or fabrication techniques. Furthermore,
none of the previous packaging methods including PGA and surface-mount
technology, have addressed the need to pack chips on the circuit board
closer together without giving up the cost advantages of prepackaged,
generally available, or standard chip components. Improved packing
techniques can also lead to certain collateral benefits, including
improving testing and manufacturability of the board assembly.
SUMMARY OF THE INVENTION
It is an object of the invention, therefore, to provide new and improved
devices and methods for permitting increased flexibility in circuit board
design.
It is another object of the invention to provide new and improved devices
and methods for improving the interchangeability of integrated circuits.
It is another object of the invention to provide new and improved devices
and methods for allowing the installation of circuits that can be used
with an existing integrated circuit, such as coprocessors, without
requiring added board space.
It is another object of the invention to provide new and improved devices
and methods for installing a surface-mount packaged semiconductor chip in
a circuit board designed for a PGA package of the same chip.
It is another object of the invention to provide new and improved devices
and methods for using low-cost, surface-mounted, prepackaged chips in a
variety of new applications for which they were previously unsuitable.
It is another object of the invention to provide new and improved devices
and methods for mounting prepackaged components on circuit boards.
It is another object of the invention to provide new and improved devices
and methods for reducing the difficulty and cost of installing and testing
a surface-mounted prepackaged chip.
It is another object of the invention to provide new and improved devices
and methods for improving the inspectability and reliability of pin
contacts on PGA packages.
It is another object of the invention to provide new and improved devices
and methods for permitting reduced overall cost of purchasing, installing,
and testing complex prepackaged semiconductor integrated circuits.
It is another object of the invention to provide new and improved devices
and methods for reducing the circuit-board area required to mount
prepackaged chips.
It is another object of the invention to provide new and improved devices
and methods for improving the interchangeability of prepackaged components
in a single board location.
It is another object of the invention to provide new and improved devices
and methods for improving the interchangeability of prepackaged components
having different power demands.
It is another object of the invention to provide new and improved devices
and methods for mounting and testing chip sets.
It is another object of the invention to provide new and improved devices
and methods for manufacturing and utilizing low-cost, multi-level circuit
boards.
It is another object of the invention to provide new and improved devices
and methods for mating a pin set and pads on a connecting circuit board.
It is another object of the invention to provide new and improved devices
and methods for translating the leads from a circuit to the socket of a
circuit board.
The above and other objects are achieved in the devices and methods of the
invention by the use of a multi-level electrical assembly for coupling one
or more integrated circuits to a socket or other attachment area of a
circuit board. The assembly includes at least one interconnect board,
which may be double-sided or multi-layered, and a pin carrier holding an
array of electrically conductive pins aligned with the socket. Sets of
contacts, pathways, and receiving means form a plurality of electrical
connections from the pins to the integrated circuit, passing through the
board.
In one form, the interconnect board has a top surface on which is located a
series of pads for surface-mounting one or more prepackaged integrated
circuits, and on the bottom surface of which is located pin contacts in a
grid array. Conductive leads along the surfaces or in intermediate layers,
and conductive vias between the layers, connect each pad with one or more
pin contact. Such an interconnect board serves as a translation device,
connecting the pads and the contacts in any desired fashion.
The connections can pass through "power planes," in which each layer (or
portion of layer) of the circuit has an assigned voltage, allowing for
connection of a lower-powered circuit to a socket previously designed for
a higher-powered one, without altering the circuit board design.
In another form, an interconnect board is placed between | | |
