 |
Description  |
|
|
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission apparatus for
transmitting (including recording and/or reproducing) code data applicable
to a digital video tape recorder (VTR), for example, where digital video
signals are encoded by block encoding to compress the amount of data and
the digital video signal are divided into small blocks and are processed
block by block.
The present invention also relates to a data transmission apparatus for
transmitting digital data exhibiting relatively good correlation such as
video signals and for correcting data having errors without using an error
correction code.
When digital video signals are recorded on a recording medium such as a
magnetic tape, it is convention to compress the digital video signals by
high-efficient encoding in order to make the transmission rate low enough
to record/reproduce. Because the amount of data of the digital video
signals is large, block encoding such as ADRC (Adaptive Dynamic Range
Coding) and DCT (Discrete Cosine Transform), both of which divide digital
video signals into small blocks and encode them block by block, has been
known as a high-efficient encoding technique.
ADRC is a high-efficient encoding technique which calculates the dynamic
range defined by maximum and minimum levels of pixel data among plural
pixels included in a two-dimensional block, and encodes the pixel data in
accordance with the dynamic range, as described in Japanese Laid-open
patent 61-144989. DCT operates to cosine-transform pixels in a block, to
re-quantize the co-efficient data obtained by the cosine-transformation,
and to encode the quantized coefficient data by variable-length encoding.
Another encoding method has been suggested in which the average data in
each block is determined and the difference between each pixel data and
the average in each block are vector-quantized.
Code outputs resulting from block encoding do not have equal importance. In
ADRC, if dynamic range information in a block is unknown at the
reproducing side, errors extend to all pixels of that block. Therefore,
the dynamic range information which is obtained for every block is more
important than the code signal which is obtained for every pixel. In one
type of ADRC in which the number of bits for quantization varies depending
upon the dynamic range, if there is an error in the dynamic range
information, the number of bits for quantization of that block cannot be
identified at the receiving side. As a result, the boundaries between that
block and other blocks become unknown so that errors extend to the other
blocks. Among coefficient data generated in DCT encoding, a DC (direct
current) component is more important than AC (alternating current)
components. A refresh data in DPCM (Differential Pulse Code Modulation)
encoding is also important data.
When the outputs of block encoding are recorded/reproduced by a digital
VTR, for example, an error correction code is used to protect data against
recording/reproducing errors. When important data happens to have an error
which the error correction code cannot correct, the error extends to the
whole block. To cure this, the same important data is recorded twice at
locations sufficiently separate as not to be subject to a burst error.
However, this increases redundancy and lowers the efficiency of data
compression.
If the important data in a block contains an error, the important data is
estimated, or statistically presumed, based upon spacial correlation
between that block and peripheral blocks. More specifically, a
least-squares method using the code data of the error block and the
decoded data located at boundaries of the peripheral blocks may be used to
estimate the important data in the error block. The maximum and minimum
values of boundary data of the peripheral blocks may be used to presume
the important data. The estimated, or presumed, important data is used for
decoding. Even though the important data is estimated with high accuracy,
the original important data cannot be restored completely. In addition,
finding boundaries between each data block correctly is necessary to
estimate the important data. Therefore, if an error extends to several
blocks, the important data cannot be estimated.
When digital video signals are recorded/reproduced in a digital VTR, for
example, it is also conventional to use error correction coding for
correcting errors. As an error correction code, simple parity,
Reed-Solomon code and a combination of these along with interleaving have
been practically used.
However, when an error correction code is used, redundancy of data
increases due to an increase in the number of parity bits needed to
improve the error correction ability. When the error cannot be corrected
by the error correction code, a conceal circuit is necessary to
interpolate the erroneous pixel with peripheral correct pixel data. Data
such as computer software generally exhibits no correlation. However,
video signals exhibit reasonably good correlation in space and in time.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention is to provide a data transmission
apparatus for transmitting (including recording and/or reproducing) block
code data, which can correct errors that may be present in important data
or quantized data, with only a limited increase in redundancy.
Another object of the present invention is to provide a data transmission
apparatus for transmitting (including recording and/or reproducing)
digital video signals without using an error correction code, taking
advantage of the spacial correlation of the video signals.
There is provided a data transmission apparatus for transmitting block code
data generated by block encoding in which a block of pixels proximate in
space is encoded as a unit to compress the amount of data needed for
transmission, wherein the block code data includes important data (e.g.
dynamic range DR, minimum value MIN, DC coefficient, etc.) which has high
importance for the purpose of decoding. In accordance with this invention,
a sum data of the plural important data is formed and is transmitted in
time and space different from that of the important data, for example, the
sum data is transmitted over a different channel; and the original
important data are restored from the received sum data and the received
important data.
As one aspect of the present invention, the block code data is transmitted
in plural channels. The sum data is formed by providing a fewer number of
the important data than the number of channels; and the sum data is
transmitted in a channel separate from the channels over which the
important data is transmitted.
In another aspect of the present invention, a weighted average data is
formed from the plural important data; the weighted average data being
transmitted in time and space different from the transmission of the
plural important data (e.g. over a different channel) and the important
data are restored from the received weighted average data and the received
plural important data.
In a further aspect of the present invention, the sum data is formed for a
unit of the plural important data by processing the plural important data
in that unit and at least one important data in another unit; the sum data
being transmitted in time and space different from the transmission of the
plural important data (e.g. over a different channel).
In yet another aspect of the present invention, the sum data is formed for
a unit of the plural important data by processing the plural important
data in that unit and at least one important data in another unit, even
though the type of the important data changes regularly.
In a still further aspect of the present invention, the block code data
includes plural data, and sum data is formed from the plural data; the sum
data being transmitted in time and space different from the transmission
of the plural data. When one of the received plural data has an error, the
erroneous data is restored from the sum data and the remaining error-free
plural data; and when a plurality of the received data have errors,
interpolated data is formed by interpolating the erroneous data and the
errors of the received plural data are corrected from the interpolated
data and the sum data.
As an additional aspect of the present invention, the sum data is formed by
adding bit data from MSB (most significant bit) to a predetermined bit
position with respect to the plural data.
As described above, important data in ADRC are data representing dynamic
range DR and data representing minimum value MIN. The sum data of n
dynamic range data DR and the sum data of n minimum value data MIN are
inserted into the transmitted data. If one of DR's and MIN's has an error
but the sum data and the other important data have no error, the correct
important data (DR or MIN) can be reproduced at the receiving side.
Redundancy can be lower than when the same important data (e.g. DR or MIN)
is recorded several times.
A data transmission apparatus for transmitting digital video signals
according to a further aspect of the present invention includes an error
detecting circuit for detecting errors of received or reproduced digital
video signals, the error detecting circuit comprising a clustering circuit
for clustering plural pixel signals proximate in space or in time to a
pixel to be detected, a memory circuit for storing existing-range data
which has been provided in advance by a learning operation for each class,
a reading circuit for reading out the existing-range data for a class
corresponding to address data which is defined by the output of the
clustering circuit, and a comparing circuit for comparing the output of
the reading circuit and the pixel data of the pixel to be detected, the
output of the comparing circuit being useful to detect an error.
As another aspect of the present invention, the memory circuit further
stores information regarding representative data for each class, and the
erroneous pixel data which is detected is replaced by representative data
formed as a function of the output of the comparing circuit.
As a further aspect of the present invention, the reproduced or received
digital video signals are encoded and a decoding circuit is provided for
decoding the encoded video signals. The clustering circuit operates as a
function of the decoded plural pixel data detected as being erroneous.
As an additional aspect of the present invention, encoded video signals are
variable-length encoded DCT coefficient data.
In another aspect of the present invention, the clustering circuit
comprises an ADRC encoding circuit supplied with the erroneous pixel data
and the plural pixel data proximate thereto, with the encoded data
corresponding to the plural pixel data being used as class information.
As a further aspect of the present invention, the existing-range defining
data is the maximum and minimum of the data actually detected for each
class.
In accordance with a still further aspect of the present invention, the
information regarding representative data is an average of the data
actually detected for each class.
In accordance with yet another aspect of the present invention, the
existing-range defining data is coefficient data which is processed with
the plural proximate pixel data and with error allowance information.
As still an additional aspect of the present invention, the information
regarding representative data is coefficient data which is processed with
the plural proximate pixel data and the representative data results from
the processing of the coefficient data and the plural proximate pixel
data.
As another aspect of the present invention, a counter circuit for counting
the number of pixels having detected errors in a certain period, with the
error allowance information being variable in accordance with the output
of the counter circuit.
As described above, by basing clustering on a pixel whose error is detected
and its peripheral data and by comparing the signal level range of the
current pixel provided for each class with its actual level, an error is
detected as a function of its probability; and the pixel having the
detected error is corrected by replacing it with predicted data which had
been provided for each class.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B comprise a block diagram of an example of a recording
circuit for a digital VTR in which the present invention is employed.
FIG. 2 shows an example of a recording pattern in an embodiment of the
present invention.
FIG. 3 is an example of the construction of a ADRC block in an embodiment
of the present invention.
FIG. 4 is an example of the construction of a macro block in an embodiment
of the present invention.
FIGS. 5A and 5B comprise a block diagram of an example of a reproducing
circuit for a digital VTR in which the present invention is employed.
FIG. 6 is a block diagram of an example of a sum data generating circuit in
accordance with an embodiment of the present invention.
FIG. 7 is a timing diagram useful for explanation of the sum data
generating circuit of FIG. 6.
FIG. 8 is a block diagram of an example of a mixed sum data generating
circuit in accordance with the present invention.
FIG. 9 is a timing diagram useful to explain the mixed sum generating
circuit of FIG. 8.
FIG. 10 is a block diagram of another example of a mixed sum generating
circuit in accordance with the present invention.
FIG. 11 is helpful in explaining the example of the mixed sum generating
circuit of FIG. 10.
FIG. 12 is a timing diagram useful to explain the mixed sum generating
circuit of FIG. 10.
FIG. 13 is a block diagram of a still further example of a mixed sum
generating circuit in accordance with the present invention.
FIG. 14 is a timing diagram helpful in explaining the mixed sum generating
circuit of FIG. 13.
FIG. 15 is useful for an explanation of a mixed sum generating circuit used
with quantized data in accordance with this invention.
FIG. 16 is an overall block diagram of a recording/reproducing circuit for
a digital VTR in which the present invention is employed.
FIG. 17 is a block diagram of an example of a correction circuit in
accordance with the present invention.
FIG. 18 is a block diagram of an example of a circuit for data correlation
in accordance with this invention.
FIG. 19 is helpful for an explanation of block formatting used with the
present invention.
FIG. 20 is a block diagram of an example of a 1-bit ADRC encoding circuit
used with the present invention.
FIG. 21 is a block diagram of an example of a practical construction of a
data correction arrangement in accordance with the present invention.
FIG. 22 is a block diagram of another example of a data correction circuit
according to the present invention.
FIG. 23 is a block diagram of still another example of a data correct
circuit used with the present invention.
FIG. 24 is a block diagram of a further example of a correction circuit
according to the present invention.
FIG. 25 is useful to explain the correction circuit of FIG. 24.
FIG. 26 is a graphical explanation of error correction according to the
present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
An embodiment of the present invention will be described, hereinafter.
FIGS. 1A and 1B illustrate a signal processing apparatus for a digital
VTR. Digital video signals are supplied to an input terminal 1 wherein
8-bit data represents each pixel, for example. The input digital video
signals are supplied to a block-formatting circuit 2 which divides a valid
area (i.e. a viewable area) of one video frame into blocks, each formed
of, for example, 4.times.4 pixels, 8.times.8 pixels, or the like.
Block-formatting circuit 2 supplies to an ADRC encoder 3 digital video
signals which had been scan-converted in the order of the blocks. ADRC
encoder 3 compresses the pixel data block by block and supplies its
encoded output to a macro-block formatting circuit 4. A macro block
comprises a plurality of ADRC blocks which have been derived from
block-formatting circuit 2.
ADRC encoder 3 detects the dynamic range DR and minimum value MIN of each
block. ADRC encoder 3 re-quantizes that video data which is less than the
minimum value MIN by a quantizing step. In ADRC using a fixed 4-bit
length, the quantizing step .DELTA. can be obtained by dividing the
dynamic range DR by 16. The video data which is less the minimum value is
divided by the quantizing step .DELTA.. The integral portion of the
quotient is the quantized data DT. The dynamic range DR, minimum value MIN
and quantized data DT comprise the output data of ADRC encoder 3. Each
ADRC block includes the dynamic range DR and minimum value MIN as
"important data."
Macro block-formatting circuit 4 generates coded data formed of macro
blocks. The quantized data DT of the macro blocks are supplied to an error
correction encoder 5 (FIG. 1B). Dynamic range DR and minimum value MIN of
the macro blocks are supplied to an adding circuit 6 which generates the
sum data DR.SIGMA. of plural dynamic ranges DR's and the sum data
MIN.SIGMA. of plural minimum values MIN's included in a macro block.
These sum data are supplied through memories 7 and 8 to mixing circuits 9
and 10. Original important data (DR, MIN) which have been supplied and
merely passed through adding circuit 6, are supplied to mixing circuits 9
and 10. The outputs of mixing circuits 9 and 10 are supplied to error
correction encoder 5.
Error correction encoder 5 generates parity data of an error correction
code. A product code is one example of a suitable error correction code.
In a product code, data are arranged as a matrix and error correction
encoding is used in each of the horizontal and vertical directions of the
matrix. A block sync signal (SYNC) and an ID signal are added to the code
and parity data. Record data having continual sync blocks are supplied
from encoder 5 to a channel encoder 11 which channel-encodes the record
data in order to reduce the direct current component therein.
The output data of channel encoder 11 is supplied to a head interleave
circuit 12 which generates six channels of record data and supplies each
channel of the record data through a recording amplifier 13 to a
respective one of rotary heads H1-H6. Head interleave circuit 12
interleaves the recording data among the plural channels. Rotary heads
H1-H6 simultaneously form six tracks on a magnetic tape T.
FIG. 2 shows the recording pattern formed on magnetic tape T in which the
slant tracks formed by respective heads H1-H6 contain respective channels
CH1-CH6.
In the preferred embodiment, as shown in FIG. 3, one ADRC block is formed
of (4.times.8) pixels. Assuming that a valid (or viewable) area of one
field of video has (240 lines.times.720 pixels), (60.times.90) ADRC blocks
are included in one field, as shown in FIG. 4. Further assuming that a
macro block contains (2.times.2=4) ADRC blocks, adding circuit 6 of FIG.
1A carries out the following calculations to generate the sum data
DR.SIGMA. and MIN.SIGMA..
DR.SIGMA.=DR1+DR2+DR3+DR4
MIN.SIGMA.=MIN1+MIN2+MIN3+MIN4
If each important data DR or MIN is 8-bit data, 10-bit sum data is
generated for DR.SIGMA. and for MIN.SIGMA..
Head interleave circuit 12 distributes four important data DR1, DR2, DR3
and DR4 (or MIN1, MIN2, MIN3 and MIN4) and their sum data DR.SIGMA. (or
MIN.SIGMA.) into different channels. For example, when the code data of
each of the four ADRC blocks in the macro block of the upper-left corner
in FIG. 4 is recorded in channels CH1, CH2, CH3 and CH4, respectively, the
sum data DR.SIGMA. and MIN.SIGMA., which are the sum of the important data
of these ADRC blocks, are recorded in the first channel (CH6) of the
following macro block (the adjacent right-hand sided macro block).
In this way, the four important data DR1-DR4 (or MIN1-MIN4) and the sum
data of them DR.SIGMA. (or MIN.SIGMA.) are recorded in respectively
different channels. Therefore, even if all of the data of the first
channel cannot be reproduced due to a head clog, for example, the
important data of the first channel nevertheless can be recovered as
follows:
DR1=DR.SIGMA.-DR2-DR3-DR4
MIN1=MIN.SIGMA.-MIN2-MIN3-MIN4
When important data of each block has to be recorded twice, as in the prior
art, an additional 16 bits are necessary for each ADRC block. On the other
hand, according to the present invention, since only an additional 20 bits
are necessary for one macro block, only 5 additional bits are needed for
each ADRC block and perfect important data recovery can be achieved.
Referring to FIGS. 5A and 5B, a reproducing circuit compatible with the
recording circuit shown in FIG. 1 will be described. Each channel of data
reproduced from magnetic tape T by one of six rotary heads H1-H6 is
supplied through a reproducing amplifier 14 to a head de-interleave
circuit 15. Head de-interleave circuit 15 de-interleaves the reproduced
data which had been interleaved by head interleave circuit 12 during
recording.
Head de-interleave circuit 15 supplies its deinterleaved output data to a
channel decoder 16 which channel-decodes the supplied data and couples the
decoded data to an error correction circuit (ECC) 17 which decodes the
originally recorded product code. The output data of error correction
circuit 17 includes, in addition to the reproduced data, an error flag to
indicate whether an error exists after the error correction operation.
Important data DR and MIN included in the output data of error correction
circuit 17 are corrected by a conventional correction algorithm. Dynamic
range data DR of a macro block is supplied to a separation circuit 18
(FIG. 5B) which separates the sum data DR.SIGMA. and the dynamic range
data DRi of each ADRC block. A latch 19 latches the sum data DR.SIGMA. and
the error flag and a memory 20 stores DRi and its error flag.
Latch 19 supplies the sum data DR.SIGMA. through a gate circuit 21 to an
operating circuit 25. Latch 19 also supplies the error flag to a detecting
circuit 22 whose output is supplied to gate circuit 21 and to operating
circuit 25. Memory 20 supplies DRi and its error flag to a gate circuit 23
and to a detecting circuit 24. Gate circuit 23 is controlled by detecting
circuit 24. Outputs of gate circuit 23 and detecting circuit 24 are
supplied to operating circuit 25.
The same circuit construction as just explained for the error correction of
dynamic range date DR is provided for the error correction of minimum
value data MIN. And in the interest of brevity, the minimum value error
correction circuitry, although illustrated, is not described.
Corrected dynamic range data DR from operating circuit 25, corrected
minimum value data MIN from operating circuit 35 and code data DT from
error correction circuit 17 are supplied to a macro block deformatting
circuit 26. Macro block deforming circuit 26 separates each recovered
macro block into its component ADRC blocks. The reproduced data of each
ADRC block are supplied to an ADRC decoder 27 for ADRC decoding.
In ADRC decoding where the bit number of the quantized code is 4 bits,
decoded data Li is generated for every pixel. Decoded data Li is expressed
as follows:
Li=[(DR/2.sup.4).times.xi+MIN+0.5]=[.DELTA..times.xi+MIN+0.5]
Xi is the value of the code signal, .DELTA. is the quantizing step and [ ]
means a guassian mark. Calculation inside [ ] mark can be achieved by
using a ROM, for example. ADRC decoder 27 adds the minimum value MIN.
The output of ADRC decoder 27 is supplied to a block deformatting circuit
28 which returns the order of the data in each ADRC block from a block
order to a raster-scan order. The reproduced data is obtained at an output
terminal 29 of block deformatting circuit 28. If necessary, output
terminal 29 may be coupled to an error interpolation circuit which
interpolates an erroneous pixel from peripheral pixel data.
FIG. 6 shows one example of gate circuits 21 and 23 and operating circuit
25. Dynamic range data DRi is supplied to an input terminal 41 and the
error flag from detecting circuit 24 is supplied to an input terminal 42.
The sum data DR.SIGMA. is supplied to an input terminal 43 and the error
flag from detecting circuit 22 is supplied to an input terminal 44. Gate
circuit 23 supplies DRi to an accumulating circuit 47 and to an
arrangement control circuit 48. The accumulated output of accumulating
circuit 47 and the output of gate circuit 21 are supplied to a subtracting
circuit 49 which, in turn, supplies its output to arrangement control
circuit 48. Corrected important data (dynamic range DR) is derived at an
output terminal 50 of arrangement control circuit 48.
As an example, if DR3 among DR1-DR4 has an error, as shown in FIG. 7, gate
circuit 23 receives the error flag which becomes high at the location
corresponding to DR3. When this signal is high, gate circuit 23 is turned
OFF so that accumulating circuit 47 and arrangement control circuit 48
receive DRi other than DR3. Because it is assumed here that DR.SIGMA. has
no error, DR.SIGMA. will pass through gate circuit 21.
Accumulating circuit 47 generates an accumulated output (DR1+DR2+DR4) and
subtracting circuit 49 subtracts the accumulated output from DR.SIGMA.1 to
recover DR3 (referred to as corrected DR3) at its output. Arrangement
control circuit 48 replaces erroneous DR3 in original DRi with the
corrected DR3. Regarding minimum value MIN, operating circuit 35 (FIG. 5B)
operates to correct an erroneous minimum value MIN in the same manner as
explained above. Correction is possible when the sum data DR.SIGMA. (or
MIN.SIGMA.) has no error and only one of plural important data
constituting the sum data DR1, DR2, DR3 and DR4 (or MIN1, MIN2, MIN3 and
MIN4) has an error.
In the above embodiment, one macro block is formed of (2.times.2) four ADRC
blocks. It is possible to change the size of the macro blocks. It is also
possible to record the sum data and the plural important data from which
the sum data is produced in separate channels to improve the error
correction ability against a burst error that may be present in one
channel. For example, if one macro block is formed of sixteen ADRC blocks
and six channels of data can be recorded in parallel, 12-bit sum data is
generated as follows:
DR.SIGMA.=Dr1+DR2+- - -+DR16
MIN.SIGMA.=MIN1+MIN2+- - -+MIN16
DR1-DR6 and MIN1-MIN6 are recorded in channels CH1-CH6, respectively.
DR7-DR12 and MIN7-MIN12 are recorded in channels CH1-CH6. DR13-DR16 are
recorded in channels CH1-CH4 and the sum data DR.SIGMA. is recorded in
channel CH5. This results in only a 1.5 bit per ADRC block increase. In
this way, when the size of the macro block becomes larger, important data
can be completely corrected with only a small increase in redundancy in
the event a burst error occurs, due to tape damage or the like.
As explained above, when the sum data generated by simple adding is
recorded, the number of bits which represent the sum data is increased,
for example, from 8-bits to 10-bits. One method of avoiding this problem
of increased bits is to record an 8-bit average of the sum data. When the
average is used, a small error is introduced by rounding-off. In order to
avoid this rounding-off problem, the sum data of plural important data
which had been weighted is averaged to form the average.
When one macro block is formed of four ADRC blocks, the averaged sum data
is obtained by the following equation (shown with reference to dynamic
range DR; but the sum data of minimum values MIN is obtained in the same
way):
DR.SIGMA.=(DR1.times.2+DR2.times.1+DR3.times.1+DR4.times.1)/5
FIG. 8 shows an example of circuitry to achieve this calculation. DRi is
supplied to an input terminal 51 and from there to a circuit 52 for
multiplying by the factor "2" and to a circuit 53 (which merely has a
buffer function). Circuits 52 and 53 supply their outputs to two input
terminals of a switching circuit 54 which is controlled by a control
signal supplied from a terminal 55.
As shown in FIG. 9, switching circuit 54 selects the output of circuit 52
at the timing of DR1 and selects the output of circuit 53 otherwise.
Switching circuit 54 supplies its output to an accumulating circuit 56 and
the sum data of weighted DRi is derived at an output terminal 57. Although
not shown in FIG. 8, a division circuit for dividing by 5 preferably is
connected to the output of accumulating circuit 56.
In forming the average of the weighted sum, an important data which is more
important than any other important data should have a larger weighting
factor. In forming four ADRC blocks, for example, if the first ADRC block
comprises pixel data in the frame, the second ADRC block comprises the
difference data representing the difference in pixel data between the
first and second ADRC blocks and the third and fourth ADRC blocks likewise
comprise similar difference data, then the important data DR1 and MIN1 of
the first ADRC block are considered more important.
When plural (e.g. two) sum data derived from important data are formed for
two macro blocks, some of the important data used to generate the sum data
may be used to form the sum data for both macro blocks. FIGS. 10 and 11
show such an example. As shown in FIG. 11, let it be assumed there are two
adjacent macro blocks in the vertical direction. If the same reference
numerals identify the important data generated from each ADRC block, the
sum data for the two illustrated macro blocks are formed as follows:
DR.SIGMA.=DR1+DR2+DR3+DR4+DR1'
DR.SIGMA.=DR1'+DR2'+DR3'+DR4'+DR1
The sum data of the minimum values MIN are similarly formed. In this way,
when both DR1 and DR2 in one macro block have errors, they can be
corrected if the dynamic range data in the other macro block have no
error. Although DR1 and DR1' are used twice in both equations, the
particular dynamic range DR to be used twice may change on a regular
basis.
Referring to FIG. 10, an example of a circuit for forming this sum data
will be described. The ADRC encoder supplies its code output to macro
block-formatting circuit 4 which generates dynamic range DR, minimum value
MIN and quantized data DT for each macro block. Dynamic range DR and
minimum value MIN are supplied to sum data generating circuits 60a and
60b, respectively.
In sum data generating circuit 60a, also referred to as a mixed sum data
generator, a timing aligning circuit aligns or phase adjusts, the timing
of the two vertically adjacent macro blocks. Timing aligning circuit 65
provides at one output terminal dynamic range DR's of the macro block
comprised of ADRC blocks 1-4 and also provides at its other output
terminal dynamic range DR's of the macro block formed of ADRC blocks
1'-4'. Timing aligning circuit 65 comprises four line memories.
DR's of one macro block are supplied to an adding circuit 66 and to a gate
circuit 70; while Dr's of the other macro block are supplied to an adding
circuit 69 and to a gate circuit 67. Terminals 68 and 71 supply control
signals to gate circuits 67 and 70 so that only DR1 passes through gate
circuit 70, as shown in FIG. 12. Although not shown in the drawings, the
control signal is supplied to gate circuit 67 so that only DR1' pass
through gate circuit 67.
Accordingly, adding circuit 66 generates the summation
(DR1+DR2+DR3+DR4+DR1') and adding circuit 69 generates the summation
(DR1'+DR2'+DR3'+DR4'+DR1). The output of adding circuit 66 is supplied to
a mixing circuit 73 via a delay circuit (DL) 72 having a delay of one
macro block whereat it is mixed with an undelayed signal. Similarly, the
output of adding circuit 69 is supplied via a delay circuit (DL) 74 to a
mixing circuit 75 whereat it is mixed with an undelayed signal. Hence,
mixed sum data is obtained at the timing of the first ADRC block upon the
occurrence of the next macro block.
The output of mixing circuit 73 is supplied to a rearranging circuit 76 and
the output of mixing circuit 75 is supplied through delay circuit (DL) 77
to the rearranging circuit. Delay circuit 77 has a delay of two lines.
Thus, output data composed of important data and their mixed data is
generated selectively at output terminal 62 of rearranging circuit 76.
As to minimum value MIN, mixed sum data generating circuit 60b is similar
to the above-explained mixed sum data generator 60a and generates minimum
values MIN and their mixed sum data at an output terminal 63. Quantized
code DT is supplied to an output terminal 64 by a delay circuit (DL) 61
provided for timing.
By adding plural upper bits of important data to produce the sum data, an
increase in the number of bits forming the sum data can be limited without
degrading the quality of video ultimately reproduced. For example, if a
macro block has sixteen ADRC blocks, the number of bits forming the same
data is increased from 8 bits to 12 bits by simple adding. But, if the
upper 4 bits of sixteen DC components are added, the bit number of the sum
data can remain at 8 bits. If a lesser number of bits is selected,
accuracy would be lowered, but nearly correct data can be restored.
FIGS. 13 and 14 are used to explain how the sum data is formed from the
upper 4 bits. FIG. 13 shows a circuit for dynamic range DR only and a
similar circuit is used for minimum value MIN. Dynamic range DR from macro
block formatting circuit 4 is supplied to a gate circuit 81. Gate circuit
81, which is controlled by a control signal supplied from an input
terminal 82, supplies its output to an accumulating circuit 83.
FIG. 14 shows the control signal from input terminal 82 used to control
gate circuit 81. Serial bits of DR1, DR2, DR3, Dr4, . . . are supplied to
gate circuit 81 and the control signal is at a high level during the
period of the upper 4 bits of DRi. Only when the control signal is at the
high level is gate circuit 81 ON so that accumulating circuit 83 generates
the sum data produced by summing (accumulating) the upper 4 bits of DRi.
The sum data of pixel data also may be formed. FIG. 15 shows the
construction of a (4.times.4) ADRC block. Reference numerals identify the
quantized data DT (4 bits) of respective pixels. The sum data is formed
according to the following equation:
DT.SIGMA.=DT1+DT2+DT3+. . .+DT15+DT16
Sum data DT.SIGMA. of these quantized data is also transmitted.
According to this method, DR, MIN, DT.SIGMA. and the quantized data
generated in one ADRC bock are transmitted so that an error that may be
present in the quantized data can be corrected. In addition, errors that
may be present in two quantized data can be compensated by interpolation.
For example, if DT7' and DT10' have errors, interpolated data is formed by
using peripheral pixel data. That is:
DT7*=(DT3+DT6+DT8+DT11)/4
DT10*=(DT6+DT9+DT11+DT14)/4
(Mark * means interpolation). The ratio of these interpolated data
(DT7*/DT10*) is calculated and the sum data DT.SIGMA. is apportioned
according to the ratio. In this way, proper interpolation can be achieved.
According to the above-described embodiments of the present invention,
because the sum data of plural important data are recorded, redundancy
increases slightly due to the recording of the sum data. However,
redundancy is lower than when the same important data is recorded several
times.
Another embodiment of the present invention is described in conjunction
with FIG. 16 which shows an embodiment of a signal processing system for a
digital VTR. Digital video signals are produced by quantizing one sample
into eight bits, for example, and are supplied to a block formatting
circuit 102 from an input terminal 101. In this embodiment, block
formatting circuit 102 divides a valid area of one field or one frame into
DCT blocks formed of (8.times.8) pixels.
Block formatting circuit 102 supplies to a DCT (Discrete Cosine Transform)
circuit 103 the digital video signals which have been scan-converted in
the order of the blocks. DCT circuit 103 generates coefficient data
comprising one direct current component and sixty-three alternating
current components for each 8.times.8 block. These coefficient data are
supplied | | |
