Shared register architecture for a dual-instruction-set CPU

Claims

We claim:

1. A shared register system for a dual-instruction-set processor, the shared register system comprising:

a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set, the first instruction set having a first encoding of operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes;

first means, coupled to the shared register, for accessing the shared register from the first instruction set, the first means writing information into the shared register responsive to a first subset of instructions from the first instruction set; and

second means, coupled to the shared register, for accessing the shared register from the second instruction set, the second means reading information from the shared register responsive to a second subset of instructions from the second instruction set,

wherein each instruction in the first subset of instructions from the first instruction set comprises a first opcode field indicating the operation encoded and a destination field specifying the shared register, and wherein each instruction in the second subset of instructions from the second instruction set comprises a second opcode field indicating the operation encoded and a source field specifying the shared register;

wherein the first subset of instructions have first opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations and wherein the second subset of instructions have second opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations;

wherein the shared register is in a plurality of general-purpose registers in the dual-instruction-set processor, the source field and the destination field selecting any one register in the plurality of general-purpose registers, the one register selected being the shared register for transferring information between the first program and the second program;

wherein the first means for accessing the shared register from the first instruction set includes means for reading and means for writing information into the shared register;

and wherein the second instruction set is a reduced instruction set computer (RISC) instruction set and the first instruction set is a complex instruction set computer (CISC) instruction set,

whereby information is transferred from the first program to the second program using the shared register.

2. The shared register system of claim 1 wherein the plurality of general-purpose registers comprise eight freely-accessible registers and six segment registers for holding segment base addresses.

3. The shared register system of claim 1 wherein the second instruction set is a PowerPC.TM. RISC instruction set, and the first instruction set is an x86 CISC instruction set.

4. A shared register system for a dual-instruction, set processor, the shared register system comprising;

a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set, the first instruction set having a first encoding operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes;

first means, coupled to the shared register, for accessing the shared register from the first instruction set, the first means writing information into the shared register responsive to a first subset of instructions from the first instruction set; and

second means, coupled to the shared register, for accessing the shared register from the second instruction set, the second means reading information from the shared register responsive to a second subset of instructions from the second instruction set,

wherein the shared register comprises a first flags field for storing first flags implicitly set by arithmetic-logic-unit (ALU) operations encoded by opcodes in the first subset of instructions from the first instruction set, and wherein the shared register further comprises a second flags field for storing second flags implicitly set by arithmetic-logic-unit (ALU) operations encoded by opcodes in a third subset of instructions from the second instruction set, the second means for accessing the shared register from the second instruction set writing information to the shared register in response to instructions from the third subset of instructions from the second instruction set;

wherein the second instruction set is a reduced instruction set computer (RISC) instruction set and the first instruction set is a complex instruction set computer (CISC) instruction set;

wherein the first flags field in the shared register is implicitly read by first instructions having opcodes encoding conditional branch operations, and wherein the second flags field in the shared register is implicitly read by second instructions having opcodes encoding conditional branch operations;

wherein the first flags include a zero flag indicating that one of the ALU operations encoded by opcodes in the first subset of instructions from the first instruction set had a zero-valued result and the second flags included zero flag indicating that one of the ALU operations encoded by opcodes in the first subset of instructions from the first instruction set had a zero-valued result;

wherein the second means for accessing the shared register from the second instruction set reads the first flags set by first instructions and reads the second flags set by second instructions, whereby the second program can read both the first flags set by ALU operations encoded by the first instruction set and the second flags set by ALU operations encoded by the second instruction set,

whereby information is transferred from the first program to the second program using the shared register.

5. A central processing unit (CPU) for executing first instructions from a first instruction set and for executing second instructions from a second instruction set, the CPU comprising:

a first instruction decoder, receiving the first instructions from the first instruction set, the first instruction decoder providing decoded first instructions;

a second instruction decoder, receiving the second instructions from the second instruction set, the second instruction decoder providing decoded second instructions;

an execution unit for executing first instructions and for executing second instructions, the execution unit receiving decoded first instructions from the first instruction decoder, the execution unit receiving decoded second instructions from the second instruction decoder; and

a condition code register comprising a first condition code and a second condition code, the first condition code being set by the execution unit when the execution unit receives a decoded first instruction and an arithmetic operation is executed, the second condition code being set by the execution unit when the execution unit receives a decoded second instruction and an arithmetic operation is executed,

the first condition code being read by the execution unit when the execution unit receives a decoded first instruction having a first opcode indicating that the first condition code be read;

the first condition code also being read by the execution unit when the execution unit receives a decoded second instruction having a second opcode that the first condition code be read;

the second condition code being read by the execution unit when the execution unit receives a decoded second instruction having a third opcode indicating that the second condition code be read,

wherein the first opcode designates an ALU operation that implicitly writes the first condition code, the second opcode and the third opcode encoding operations for a conditional branch operation that reads the condition code register to determine if a branch is taken;

wherein the first instruction set has a first encoding of operations to opcodes, the second instruction set has a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes;

whereby the first condition code set by execution of the first instruction set may be read by the first instruction set or the second instruction set.

6. A shared register system for a dual-instruction-set processor, the shared register system comprising:

a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set, the first instruction set having a first encoding of operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes;

first means, coupled to the shared register, for accessing the shared register from the first instruction set, the first means writing information into the shared register responsive to a first subset of instructions from the first instruction set; and

second means, coupled to the shared register, for accessing the shared register from the second instruction set, the second means reading information from the shared register responsive to a second subset of instructions from the second instruction set,

wherein each instruction in the first subset of instructions from the first instruction set comprises a first opcode field indicating the operation encoded and a destination field specifying the shared register, and wherein each instruction in the second subset of instructions from the second instruction set comprises a second opcode field indicating the operation encoded and a source field specifying the shared register;

wherein the first subset of instructions have first opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations and wherein the second subset of instructions have second opcode fields with encodings for integer operations, arithmetic-logic-unit (ALU) operations, and register-to-register move operations;

wherein the shared register is in a plurality of general-purpose registers in the dual-instruction-set processor, the source field and the destination field selecting any one register in the plurality of general-purpose registers, the one register selected being the shared register for transferring information between the first program and the second program;

wherein the first means for accessing the shared register from the first instruction set includes means for reading and means for writing information into the shared register;

and wherein the first instruction set is a reduced instruction set computer (RISC) instruction set and the second instruction set is a complex instruction set computer (CISC) instruction set,

whereby information is transferred from the first program to the second program using the shared register.

7. A shared register system for a dual-instruction-set processor, the shared register system comprising:

a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set, the first instruction set having a first encoding of operations to opcodes, the second instruction set having a second encoding of operations to opcodes, the first encoding of operations to opcodes being substantially independent from the second encoding of operations to opcodes;

first means, coupled to the shared register, for accessing the shared register from the first instruction set, the first means writing information into the shared register responsive to a first subset of instructions from the first instruction set; and

second means, coupled to the shared register, for accessing the shared register from the second instruction set, the second means reading information from the shared register responsive to a second subset of instructions from the second instruction set,

wherein the shared register comprises a first flags field for storing first flags implicitly set by arithmetic-logic-unit (ALU) operations encoded by opcodes in the first subset of instructions from the first instruction set, and wherein the shared register further comprises a second flags field for storing second flags implicitly set by arithmetic-logic-unit (ALU) operations encoded by opcodes in a third subset of instructions from the second instruction set, the second means for accessing the shared register from the second instruction set writing information to the shared register in response to instructions from the third subset of instructions from the second instruction set;

wherein the first instruction set is a reduced instruction set computer (RISC) instruction set and the second instruction set is a complex instruction set computer (CISC) instruction set;

wherein the first flags field in the shared register is implicitly read by first instructions having opcodes encoding conditional branch operations, and wherein the second flags field in the shared register is implicitly read by second instructions having opcodes encoding conditional branch operations;

wherein the first flags include a zero flag indicating that one of the ALU operations encoded by opcodes in the first subset of instructions from the first instruction set had a zero-valued result and the second flags include a zero flag indicating that one of the ALU operations encoded by opcodes in the first subset of instructions from the first instruction set had a zero-valued result;

wherein the second means for accessing the shared register from the second instruction set reads the first flags set by first instructions and reads the second flags set by second instructions, whereby the second program can read both the first flags set by ALU operations encoded by the first instruction set and the second flags set by ALU operations encoded by the second instruction set,

whereby information is transferred from the first program to the second program using the shared register.

BACKGROUND OF THE INVENTION--RELATED APPLICATION

This application is related to copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, hereby incorporated by reference. This related application has a common inventor and is assigned to the same assignee as the present application.

BACKGROUND OF THE INVENTION--FIELD OF THE INVENTION

This invention relates to computing hardware, and more particularly to the architecture of registers in a processor capable of executing from two instruction sets.

BACKGROUND OF THE INVENTION--DESCRIPTION OF THE RELATED ART

Processors, or central processing units (CPU's) that are capable of executing instructions from two separate instruction sets are highly desired at the present time. For example, a desirable processor would execute user applications for the x86 instruction set and the PowerPC.TM. instruction set. It would be able to execute the tremendous software base of x86 programs that run under the DOS.TM. and WINDOWS.TM. operating systems from Microsoil of Redmond, Wash., and it could run future applications for PowerPC.TM. processors developed by IBM, Apple, and Motorola.

Such a processor is described in the related to the copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926. That dual-instruction-set CPU has a pipeline which is capable of executing instructions from either a complex instruction set computer (CISC) instruction set, such as the x86 instruction set, or from a reduced instruction set computer (RISC) instruction set, such as the PowerPC.TM. instruction set.

Two instruction decode units are provided so that instructions from either instruction set may be decoded. Two instruction decoders are required when the instruction sets are separate because the instruction sets each have an independent encoding of operations to opcodes. For example, both instruction sets have an ADD operation or instruction. However, the binary opcode number which encodes the ADD operation is different for the two instruction sets. In fact, the size and location of the opcode field in the instruction word is also different for the two instruction sets. In the x86 CISC instruction set, the opcode 03 hex is the ADD r,v operation or instruction for a long operand. This same opcode, 03 hex, corresponds to a completely different instruction in the PowerPC.TM. RISC instruction set. In CISC the 03 hex opcode is an addition operation, while in RISC the 03 hex opcode is TWI--trap word immediate, a control transfer instruction. Thus two separate decode blocks are necessary for the two separate instruction sets.

Programs may run in either or both instruction sets. Data and other information may be shared between RISC programs and CISC programs. One way to share data and other information is to store the data in a register within the CPU before switching to the alternate instruction set, and making all registers readable by either instruction set. Unfortunately, this requires that the instruction sets be extended to provide instructions to read the additional registers. The shared data could also be saved to a stack in memory, but this decreases performance due to the time required to transfer the data to memory and to adjust the stack pointers.

Two sets of registers could be provided; one set for the use of CISC programs and a second set for the use of RISC programs. This is an expensive approach since the registers reside on the CPU die, which has a limited space available for registers. The additional registers would require increasing the size of the CPU die, or deleting another function such as floating point processing.

What is desired is a way to share some of the registers between a CISC and a RISC architecture on a dual-instruction-set CPU. It is further desired to have shared registers for data and system information. The shared registers should not be extra registers in addition to the registers already defined by the CISC or RISC architectures, but should be registers already existing in the architectures. The shared registers must not cause conflicts between use in the two instruction sets or other undesirable effects.

SUMMARY OF THE INVENTION

Certain CPU registers defined by a RISC and a CISC architecture are shared. CISC and RISC programs may alter and read these shared registers, allowing data and system information to be exchanged between programs running in the two instruction sets.

A shared register system for a dual-instruction-set processor has a shared register for storing information to be transferred between a first program comprised of instructions from a first instruction set and a second program comprised of instructions from a second instruction set. The first instruction set has a first encoding of operations to opcodes, while the second instruction set has a second encoding of operations to opcodes. The first encoding of operations to opcodes is substantially independent from the second encoding of operations to opcodes.

A first means is for accessing the shared register from the first instruction set. The first means writes information into the shared register responsive to a first subset of instructions from the first instruction set. A second means is for accessing the shared register from the second instruction set. The second means reads information from the shared register responsive to a second subset of instructions from the second instruction set and.

The invention allows information to be transferred from the first program to the second program using the shared register. In other aspects of the invention, the shared register may be any one of the general-purpose registers accessible to both instruction sets, while the source and destination fields in the instruction words specify which general-purpose register to access. In still further aspects of the invention, the shared register is the flags register which stores flags or condition codes that are implicitly written by arithmetic-logic-unit (ALU) operations. Although the shared flags register contains a first flags field for flags from the first instruction set and a second flags field for the flags from the second instruction set, either instruction set can access the flags in the shared register regardless of which instruction set the flags are from.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a RISC register set.

FIG. 2 is a diagram of a CISC register set.

FIG. 3 is a diagram of a CISC condition flag register and a RISC condition register.

FIG. 4 shows shared registers in a dual-instruction-set CPU.

DETAILED DESCRIPTION

The present invention relates to an improvement in processor architecture. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

This application is related to the copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, hereby incorporated by reference.

A dual-architecture central processing unit (CPU) is capable of operating in three modes--RISC mode, CISC mode, and emulation mode. A first instruction decoder decodes instructions when the processor is in RISC mode, while a second instruction decoder decodes instructions while the processor is in CISC mode. Two instruction decoders are needed since the RISC and CISC instruction sets have an independent encoding of instructions or operations to binary opcodes.

The third mode of operation, emulation mode, also uses the first instruction decoder for RISC instructions, but emulation mode executes a superset of the RISC instruction set. Using emulation mode, individual CISC instructions may be emulated with RISC instructions. Thus, not all CISC instructions need to be directly supported in the CPU's hardware. Unsupported CISC instructions cause a jump to an emulation mode routine to emulate the unsupported CISC instruction. Upon completion of the emulation mode routine, control is returned to the CISC program with the next CISC instruction.

RISC INSTRUCTIONS NEED ACCESS TO CISC REGISTERS

Emulation of CISC instructions with RISC instructions creates a need for the RISC instructions to have access to CISC registers. For example, a CISC branch instruction may be emulated by an emulation routine of RISC instructions. The CISC branch instruction may be a conditional branch that only branches if a certain bit in a condition code register is set, perhaps by a previous CISC instruction. Since the CISC condition code register is part of the CISC architecture, but not the RISC architecture, the condition code register would not be visible to the RISC instructions in the emulation routine. However, the RISC emulation routine must have access to this CISC condition code register to determine if the branch should be taken.

RISC REGISTER SET

FIG. 1 is a diagram of a register set for a RISC architecture such as the PowerPC.TM.. Registers that are visible to a user program are shown as user register space 10. Supervisory programs such as operating systems are able to see all of the registers in the user register space 10 and the registers in the supervisor's register space 12. The user registers include general-purpose registers 14 which are used by programs for temporary storage of operands and results, and for address formation. Floating point registers 16 are provided for storing floating point numbers that a numeric processor operates on. Condition register 20 contains condition codes set by various instructions and is useful for setting and checking conditions for conditional branch instructions. Integer exception register 18 contains bits that are set when an exception is caused by execution of an instruction. It contains information on overflows and carries that occurred in an arithmetic-logic-unit (ALU) when the instruction causing the exception was executed. Link register 22 contains the branch target address when a special branch to link register instruction is executed. Count register 24 holds a value for a loop count which can be decremented, providing a simple way of programming loops.

A supervisory program such as an operating system has access to additional registers in the supervisor's register space 12. Supervisor general-purpose registers 26 are for general use by the supervisory program. Segment registers 28 and block-address translation registers 32 are for address translation functions. Machine state register 36 defines the state of the processor, including reset, and CISC/RISC/emulation mode. Machine state register 36 contains a privlege-level bit, the PR bit, to indicate if a the processor is running in user or supervisor mode when RISC mode is active. An additional bit, the xE bit, is included in machine state register 36 to indicate CISC and emulation modes. The xE bit and the PR bit are encoded as shown in Table 1.

TABLE 1 ______________________________________ Machine Status xE bit PR bit Processor Mode ______________________________________ 0 0 RISC Supervisor 0 1 RISC User 1 0 x86 Emulation 1 1 x86 CISC ______________________________________

Machine status save restore 0 register 30 saves the effective address of the instruction following the instruction causing an exception or a system call instruction. Machine status save restore 1 register 34 saves part of machine state register 36 and other information on the cause of