Integrated circuit package with via interconnections formed in a substrate

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BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic devices such as integrated circuit devices, hybrid circuits and multichip integrated circuit modules, and, in particular, to the electrical connection of integrated circuits to other integrated circuits, conductive components and conductive leads within a single package. Most specifically, the invention relates to electronic device packages which include a single layer or multilayer substrate in which vias are used to interconnect the substrate to package leads or interconnect layers within the substrate, and to a method for forming such packages.

2. Related Art

An integrated circuit is formed on a semiconductor die. Usually, the die is enclosed in a package. Typically, electrical connection to components (i.e., active components such as integrated circuits, transistors and diodes, and passive components such as resistors, capacitors and inductors) outside an integrated circuit package is made via individual leads (originally part of a leadframe) extending from the package. The leads are electrically connected to the integrated circuit on the die inside the package. Historically, this electrical connection has been made by affixing bond wires between an inner portion of selected leads and bond pads on the die.

This type of electrical connection between the leads and the integrated circuit within the package was designed for use with packages: containing a single semiconductor die. The development: of multichip integrated circuit packages, where a plurality of semiconductor die are mounted on an electrically insulative surface (interconnection substrate) and enclosed in a package, necessitated a more ellaborate approach. The integrated circuits in a multichip package are typically connected to traces (conductive off-chip interconnecting paths) on the electrically insulative surface using either wire bonding technology, tape automated bonding (TAB), or flip chip technology. Electrical connection is then made between the traces on the interconnection substrate and the leads of the package by affixing bond wires between selected leads and bond pads located on the periphery of the interconnection substrate. An example of such a method is shown in U.S. Pat. No. 4,754,317 to Comstock et al.

As the complexity of integrated circuits grew, multilayer substrates were developed to improve performance and make routing easier between components. Each layer of a multilayer substrate typically comprises dielectric and conductive material. An example of such a substrate is shown in U.S. Pat. No. 4,975,761 to Chu. The additional layers allow the crossing of traces so that circuit components (i.e., active components such as integrated circuits, transistors and diodes, and passive components such as resistors, capacitors and inductors) can be placed and interconnected closer together (i.e., circuit density is increased) than would be the case if these components were mounted on a single metal layer substrate, or individually packaged and mounted to a printed circuit board.

Eventually, the density of leads for a given substrate was increased by interconnecting leads to the substrate with a copper plated "through hole" (a mechanically drilled hole extending through all layers of the substrate and leads). An example of such a method is shown in U.S. Pat. No. 4,908,933 to Sagisaka et al. However, this method became impractical as the need for higher density increased since the process of drilling through holes cannot provide the close spacing needed. Further, the space opposite to the interconnect side of the substrate is unable to be utilized because the electrical connection within the hole extends through all layers.

Forming through holes by mechanical drilling has limitations. Through holes smaller than a certain size cannot be formed because of limitations on the size of the drill bits used to form the through holes. As the bits get smaller and smaller, they are increasingly likely to break during drilling, making mechanical drilling impractical for very small through holes. Further, the spacing between through holes is limited. If the spacing is too small, the material lying between an existing through hole and one being drilled will deform due to the forces imparted by the drilling process. For these reasons, the density of through holes (and thus electrical interconnections) is limited. In a one square inch substrate in which through holes have been formed in staggered rows by mechanical drilling, the number of leads (i.e., vias) is typically limited to approximately 256.

Additionally, the speed of through hole formation is limited when mechanical drilling is used. Through holes can only be drilled one at a time. If it is attempted to increase the speed of through hole formation by increasing the speed with which the drilling motion is repeated, the likelihood of breaking drill bits increases.

In response to these problems, a new technique was developed in which vias (small concave depressions in insulative material which connect a first conductive region to a second conductive region) are formed in the substrate at locations at which it is desired to make electrical interconnection between the leads and the substrate. Vias can also be formed in the substrate at locations at which it is desired to make interconnection between electrically conductive portions of various layers of the multilayer substrate. After forming the vias, electrically conductive material is deposited to connect the interior of each via or through hole to the inner portion of one of the leads or to an electrically conductive portion of a substrate layer.

Lasers may be used to form vias spaced more closely together so that greater via density is achieved than possible with mechanical drilling of through holes. Thermal lasers, such as CO.sub.2 lasers or Nd:YAG lasers, have been used to form vias in inorganic substrates. Thermal lasers emit laser energy that penetrates a material by heating the material to produce melting and evaporation.

Preferably, organic material is used to form the dielectric layers of multilayered substrates because of the lower cost, superior dielectric properties and ease of penetration of organic material. However, the use of a thermal laser in forming vias in organic materials produces undesirable side effects due to the heating of the material. These side effects include, but are not limited to, dielectric degradation, charring and surface reflow.

Further, prior use of lasers to form vias has been implicitly limited by the mechanical drilling model in that vias have been formed one at a time by a laser beam directed at the substrate. This approach is unnecessarily slow because it requires repositioning of the laser before forming each via, and each via must be completely formed before another is begun.

Therefore, there is a need for a method of forming vias in a single layer or multilayer substrate that is fast, achieves high via density, and does not overheat the substrate or cause other quality or reliability problems during formation of the vias. There is also a need for an integrated circuit package including a single layer or multilayer substrate in which vias are formed to achieve high interconnection density between electrical components within the package and between electrical components and the package leads.

SUMMARY OF THE INVENTION

In accordance with the invention, there is provided an integrated circuit package including a single layer or multilayer substrate in which vias are formed to interconnect electrically conductive components in the substrate to the electrically conductive package leads so that high electrical interconnect density is achieved.

The vias are formed by a method according to the invention. Focused laser energy is swept across one surface of a mask in which holes have been formed. As the laser energy is swept:, laser energy passes through the holes of the mask. The laser energy passing through the holes strikes the surface of a substrate held in place below the mask. The laser energy penetrates the substrate to form vias. A set of leads is preferably laminated into an interior region of the substrate or attached to a side of the substrate opposite the side which is struck by the laser energy. The sheet of laser energy is swept at such a speed and is maintained at such an energy level that the laser energy forms vias in the substrate, but does not penetrate the leads.

In accordance with the invention, the mask may be disposed relative to the substrate in any of a number of ways. In one method according to the invention, the mask is held in place above the surface of the substrate which is to be contacted by the laser energy. In another method according to the invention, the mask is held by mechanical pressure to the surface of the substrate which is to be penetrated by the laser energy. In yet another embodiment according to the invention, the mask is formed integrally with the substrate. In this method, again the mask contacts the surface of the substrate which is to be penetrated by the laser energy. However, the mask is not held in place by mechanical pressure, but rather is attached to the surface of the substrate. In this method according to the invention, the mask is preferably left on the substrate surface after via formation so that the mask may be subject to further processing.

Additionally, other methods of via formation could be used to make an integrated circuit package according to the invention which includes a single layer or multilayer substrate in which interconnecting vias are formed. These methods include etching or chemical milling, as well as pre-drilling of vias prior to lamination of the substrate to the package leads.

The method according to the invention may be used to form interconnections between the outer surface of the substrate and the leads, inner metal surfaces of the substrate and the leads, and two conductive surfaces of the substrate. The method according to the invention may be used to form vias with circular or elongated cross-sectional shapes. The elongated cross-sectional shape has the advantage of allowing interconnection density to be increased without adversely affecting the reliability of the electric interconnections. Slightly oversized vias may also be formed according to the invention to allow interconnection of package leads and inner metal layers with one via rather than two. The method according to the invention may also be used to form cavities in the substrate in which integrated circuit devices may be disposed.

Further in accordance with the invention, the substrate in one embodiment is formed of an organic resin and the laser energy is emitted from a non-thermal laser. The non-thermal laser is preferably an excimer laser. The organic resin is preferably either a thermosetting or a thermoplastic resin. Of the thermosetting resins, epoxy resin, polyimide resin, polyamide resin, polyetherimide resin or polycyanurate resin may be used. Of the thermoplastic resins, polyester resin, polyamide resin, polysulfone resin, polyetherimide resin or polycarbonate resin may be used. Epoxy resin is preferred. The resin may also include reinforcing fibers. The fibers may be organic (e.g., aramid, polyester, polyamide, poly-ether-ether-ketone, polyimide, polyetherimide or polysulfone) or they may be inorganic (e.g., alumina, silica) if the inorganic fibers do not greatly impede the laser penetration.

In accordance with the invention, substrates may be formed on one or both sides of the set of leads. If substrates are formed on both sides of the leads, a single laser may be used to form the vias (via formation taking place through first one substrate and then the other) or two lasers may be used to form the vias (in which case the vias may be formed through the substrates simultaneously).

Once vias are formed in the substrate or substrates, the vias are coated with an electrically conductive material (by electroplating copper, electroless copper plating, or screening and filling vias with conductive material) so that electrical connection is established between particular leads and locations on or within each substrate at which it is desired to make electrical contact. Coating a via with electrically conductive material may also be done to establish contact between two or more electrical contact points which are all disposed within or on the substrate.

The method according to the invention is faster than prior methods because many vias may be formed simultaneously in the substrate. Further, high via density is achieved because of the ability to form holes smaller and closer together than possible with mechanical drills. Additionally, overheating of the substrate during via formation is avoided since a non-thermal laser is preferably used. Last, the method according to the invention is inexpensive because of the fast via formation and elimination of the need to clean out extraneous material that would be left in the vias if they were formed by a thermal laser.

Lead and substrate combinations formed with organic material according to the invention are even more inexpensive to produce than if inorganic material is used because of the low cost of organic materials relative to inorganic materials and the greater ease with which the organic materials may be penetrated. Lead and substrate combinations with substrates formed on both sides of the leads achieve even greater via density than combinations formed with a substrate on only one side.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cutaway view of a section of a lead and multilayer substrate combination in which vias are formed to connect the multilayered substrate to the leads, connect the leads to an inner layer of the substrate, and connect two inner layers of the substrate.

FIG. 2 is a cutaway view of a lead and multilayer substrate combination in which vias are formed through the substrate layers by using a mask imaging technique.

FIG. 3 is a cutaway view of a lead and multilayer substrate combination in which vias are formed through the substrate layers by using a contact mask technique.

FIG. 4 is a cutaway view of a lead and multilayer substrate combination in which vias are formed through the substrate layers by using a conformal mask technique.

FIG. 5 is a perspective view of another embodiment of the invention in which integrated circuit chips are disposed within cavities formed in the substrate of a lead and substrate combination.

FIGS. 6A, 6B and 6C are perspective, top and side views of another embodiment of the invention in which the electrical connection between a lead and an electrically conductive portion of an inner substrate layer of a lead and multilayer substrate combination is made through the formation of a single via.

FIG. 7 is a perspective view of a lead and multilayer substrate combination according to another embodiment of the invention in which the vias have an elongated cross-sectional shape.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a cutaway view of a section of a lead and multilayer substrate combination 100 in which vias 105 are formed to connect the multilayered substrates 102, 103 to the leads 101, connect the leads 101 to an inner layer 110 of the substrate 102, and connect two inner layers 110, 111 of the substrates 102, 103. Vias 105 are formed by a method according to the invention to, for instance, electrically connect leads 101 to traces 107 that extend along an outer surface, e.g., surface 102a, of the substrate 102 from vias 105 to integrated circuit connection areas 112. An integrated circuit 120 is connected by bond wires 114 from bond pads 113 to connection areas 112 so that electrical connection can be made from the integrated circuit 120 to the exterior of the package through the leads 101. An encapsulant 109 encases the substrates 102, 103, integrated circuit 120, bond wires 114, and an inner portion of leads 101.

Though the combination 100 shown has substrates 102, 103 attached on opposite sides of the set of leads 101, and the substrates 102, 103 have multiple layers, e.g., layers 110, 111, it is to be understood that the invention encompasses lead and substrate combinations in which a substrate is formed on only one side of the set of leads 101 and/or the substrate(s) has only one layer, e.g., layer 110.

Each layer, e.g., layer 110 of the multilayered substrates 102, 103 is comprised of a layer of dielectric material and a generally conductive layer which includes conductive paths and/or electronic interconnections. As shown in FIG. 1, vias such as via 105 can be formed through one or more of the layers, e.g., layer 110, of each substrate 102, 103 to, but not through, the set of leads 101, so that via 105 intersects a location on one of the conductive layers at which it is desired to make electrical connection to a lead 101.

Via 105a is used to connect an electrically conductive trace 107 to a lead 101a. Vias 105b, 105c, 105d are used to connect electrically conductive portions of various layers of the substrates 102, 103 to other electrically conductive portions of the substrates 102, 103. Electrically conductive plating material 108 (e.g., copper) covers the interior surface of each via 105.

FIG. 2 illustrates one method, the mask imaging technique, according to the invention for forming vias 105 in the substrates 102, 103 of the lead and multilayer substrate combination 100. The method will be described only with respect to formation of vias such as via 105 between the substrate 102 and lead 101; however, it is understood that the same method is used to form vias in substrate 103. A mask 201 is patterned so that holes 202 are formed at locations at whi